The World Leader in High Performance Signal Processing Solutions ADV7510 to ADV7511Differences September, 2010 Overview Pin Out and other Hardware Changes Audio Return Channel 3D Format Support Improved Electrical Characteristics CEC 3 Buffers HDMI 1.4 CEC Features HDCP CSC and Packet Update Feature Video Input Detection Video Data Range Clipping Miscellaneous Chip ID and Revision Registers TMDS Clock Inversion Internal HPD Pulldown Changes 2 in Fixed Registers Pinout Differences ADV7511 and ADV7510 share a “pin-similar” 100-pin LQFP package HEAC+/- and SPDIF_OUT pins added Changed from GND and NC pin now includes an internal pull-down resistor (see slide 24) 100 GND 99 GND 98 HSYNC 97 DE 96 D0 95 D1 94 D2 93 D3 92 D4 91 D5 90 D6 89 D7 88 D8 87 D9 86 D10 85 D11 84 D12 83 D13 82 D14 81 D15 80 D16 79 CLK 78 D17 77 DV DD 76 DV DD HPD PIN 1 INDICATOR ADV7511 TOP VIEW (Not to Scale) BGV DD 26 GND 27 R_EXT 28 AVDD 29 HPD 30 GND 31 TXC– 32 TXC+ 33 AVDD 34 TX0– 35 TX0+ 36 GND 37 PD 38 TX1– 39 TX1+ 40 AV DD 41 TX2– 42 TX2+ 43 GND 44 INT 45 SPDIF_OUT 46 DVDD_3V 47 CEC_IN 48 DVDD 49 CEC_CLK 50 DVDD 1 VSYNC 2 DSD0 3 DSD1 4 DSD2 5 DSD3 6 DSD4 7 DSD5 8 DSD_CLK 9 SPDIF 10 MCLK 11 I2S0 12 I2S1 13 I2S2 14 I2S3 15 SCLK 16 LRCLK 17 GND 18 DVDD 19 GND 20 PVDD 21 GND 22 GND 23 PVDD 24 PVDD 25 3 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 GND D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 SDA SCL DDCSDA DDCSCL HEAC+ HEAC- Audio Return Channel ADV7511 adds the ARC function from HDMI 1.4a PCB Change Add the following circuit to incorporate the ARC function in hardware ADV7511 HEAC+ To SPDIF Receiver (3.3V CMOS) 1uF 52 SPDIF_ OUT 46 ARC Receiver 1.8V 50 ohms 1uF 51 HEAC- ARC 4 Registers From HDMI connector 3D Format Support (1) ADV7510 does not work with all 3D structures at all resolutions ADV7511 works with all 3D structures at all video resolutions defined in CEA 861E, assuming the TMDS clock is within the allowable range for the ADV7511 (< 225 MHz) Registers for DE Generation, Embedded Sync Generation, and Sync Adjustment have been expanded in order to support all 3D modes. This is shown in the following tables: 5 DE Generation Parameter ADV7510 ADV7511 Hsync Delay 10 bit: (0x35[7:0],0x36[7:6]) 11 bit: (0xFB[7],0x35[7:0],0x36[7:6]) Vsync Delay 6 bit: (0x36[5:0]) 8 bit: (0xFB[6:5], 0x36[5:0] Active Width 12 bit: (0x37[4:0],0x38[7:1]) 13 bit: (0xFB[4], 0x37[4:0],0x38[7:1]) Active Height 12 bit: (0x39[7:0],0x3A[7:4]) 13 bit: (0xFB[3], 0x39[7:0],0x3A[7:4]) 3D Format Support (2) Parameter ADV7510 ADV7511 Hsync Placement 10 bit: (0xD7[7:0],0xD8[7:6]) 13 bit: (0xFA[4:2],0xD7[7:0],0xD8[7:6]) Vsync Window 9 bit: (0xDC[4:0],0xDD[7:4]) 11 bit: (0xFA[1:0],0xDC[4:0],0xDD[7:4]) 6 Sync Adjustment Embedded Sync Decoding Parameter ADV7510 ADV7511 Hsync Placement 10 bit: (0x30[7:0],0x31[7:6]) 13 bit: (0xFA[7:5],0x30[7:0],0x31[7:6]) Improved Electrical Characteristics Rise time and fall time have been decreased for more margin on the 1080p 12-bit color eye diagram. The ESD 7 R_EXT sensitivity to noise has been decreased protection has been improved on the R_EXT pin CEC Section Functionality Changes 2 Rx message buffers added I2C Controls to handle 2 buffers are added (detailed in Register Changes section) Interrupts for user defined Op Codes are added Rx Enable is now a read only bit. It does not need to be written to enable the Rx. Tx Enable is no longer self clearing, and must be cleared manually 8 CEC Register Map Changes – CEC Rx (1) ADV7510: Address Address 0x2B 0x2C 0x2D-0x2E 0x2F-0x30 0x31-0x32 0x33-0x34 0x35-0x36 0x37-0x38 0x39-0x3A 0x3B-0x3C 0x3D-0x3E 0x3F-0x40 0x41-0x42 0x43-0x44 0x45-0x46 0x47-0x48 0x49 0x4A-0x4B 0x4C 0x4D-0x4E Register Name Logical Address Mask Error Report Mode Error Detect Mode Force NACK Force Ignore Logical Address1 Logical Address0 Logical Address2 Clock Divider Power Mode Glitch Filter Ctrl Soft Reset St Total St Total Min St Total Max St Low St Low Min St Low Max Bit Total Bit Total Min Bit Total Max Bit Low One Bit Low Zero Bit Low Max Sample Time Line Error Time Fixed Rise Time Bit Low Detection Mode Bit Low One Min 0x4F-0x50 R/W [15:0] 0x51-0x52 R/W [15:0] 0x28 0x29 9 To make room for register controls for the additional CEC Rx buffers, the CEC timing related registers in the CEC Register Map were moved from 0x27-0x52 to 0x4B – 0x76 ADV7511: Type Bits [6:4] [3] R/W [2] [1] [0] [7:4] R/W [3:0] R/W [3:0] [7:2] R/W [1:0] R/W [5:0] R/W [0] R/W [15:0] R/W [15:0] R/W [15:0] R/W [15:0] R/W [15:0] R/W [15:0] R/W [15:0] R/W [15:0] R/W [15:0] R/W [15:0] R/W [15:0] R/W [15:0] R/W [15:0] R/W [15:0] R/W [0] R/W [15:0] R/W [0] R/W [15:0] 0x27 0x2A 0x4F 0x50 0x51-0x52 0x53-0x54 0x55-0x56 0x57-0x58 0x59-0x5A 0x5B-0x5C 0x5D-0x5E 0x5F-0x60 0x61-0x62 0x63-0x64 0x65-0x66 0x67-0x68 0x69-0x6A 0x6B-0x6C 0x6D 0x6E-0x6F 0x70 0x71-0x72 Type Bits [6:4] [3] R/W [2] [1] [0] [7:4] R/W [3:0] R/W [3:0] [7:2] R/W [1:0] R/W [5:0] R/W [0] R/W [15:0] R/W [15:0] R/W [15:0] R/W [15:0] R/W [15:0] R/W [15:0] R/W [15:0] R/W [15:0] R/W [15:0] R/W [15:0] R/W [15:0] R/W [15:0] R/W [15:0] R/W [15:0] R/W [0] R/W [15:0] R/W [0] R/W [15:0] Register Name Logical Address Mask Error Report Mode Error Detect Mode Force NACK Force Ignore Logical Address1 Logical Address0 Logical Address2 Clock Divider Power Mode Glitch Filter Ctrl Soft Reset St Total St Total Min St Total Max St Low St Low Min St Low Max Bit Total Bit Total Min Bit Total Max Bit Low One Bit Low Zero Bit Low Max Sample Time Line Error Time Fixed Rise Time Bit Low Detection Mode Bit Low One Min Bit Low One Max 0x73-0x74 R/W [15:0] Bit Low One Max Bit Low Zero Min 0x75-0x76 R/W [15:0] Bit Low Zero Min 0x4B 0x4C 0x4D 0x4E CEC Register Map Changes – CEC Rx (2) 2 new CEC Rx buffers have been added The 3 buffers are named 1, 2, and 3 The Length, Header, and Data for buffer 1 are the same as the controls for the buffer on ADV7510 (0x15-0x25) Added Message Length for buffers 2 and 3 (0x37[4:0] and 0x48[4:0]) Added Message Header for buffers 2 and 3 (0x27 and 0x38) Added Message Data [14:0] for buffers 2 and 3 (0x28-0x36 and 0x39-47) ADV7510 and ADV7511 (buffer 1 registers): Address Type Bits Register Name 10 0x15 RO 0x16 RO 0x17 RO 0x18 RO 0x19 RO 0x1A RO 0x1B RO 0x1C RO 0x1D RO 0x1E RO [7:0 ] [7:0 ] [7:0 ] [7:0 ] [7:0 ] [7:0 ] [7:0 ] [7:0 ] [7:0 ] [7:0 ] [7:0 Rx Frame Header (Buffer 1) Rx Frame Data0 (Buffer 1) Rx Frame Data1 (Buffer 1) Rx Frame Data 2 (Buffer 1) Rx Frame Data3 (Buffer 1) Rx Frame Data4 (Buffer 1) Rx Frame Data5 (Buffer 1) Rx Frame Data6 (Buffer 1) Rx Frame Data7 (Buffer 1) Rx Frame Data8 (Buffer 1) CEC Register Map Changes – CEC Rx (3) Added on ADV7511 (buffer 2 and buffer 3 registers): Address Type Bits Register Name Address Type Bits Register Name 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 Rx Frame Header (Buffer 2) Rx Frame Data0 (Buffer 2) Rx Frame Data1 (Buffer 2) Rx Frame Data 2 (Buffer 2) Rx Frame Data3 (Buffer 2) Rx Frame Data4 (Buffer 2) Rx Frame Data5 (Buffer 2) Rx Frame Data6 (Buffer 2) Rx Frame Data7 (Buffer 2) Rx Frame Data8 (Buffer 2) Rx Frame Data9 (Buffer 2) Rx Frame Data10 (Buffer 2) Rx Frame Data11 (Buffer 2) Rx Frame Data12 (Buffer 2) Rx Frame Data13 (Buffer 2) Rx Frame Data14 (Buffer 2) Rx Frame Length (Buffer 2) 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 Rx Frame Header (Buffer 3) Rx Frame Data0 (Buffer 3) Rx Frame Data1 (Buffer 3) Rx Frame Data 2 (Buffer 3) Rx Frame Data3 (Buffer 3) Rx Frame Data4 (Buffer 3) Rx Frame Data5 (Buffer 3) Rx Frame Data6 (Buffer 3) Rx Frame Data7 (Buffer 3) Rx Frame Data8 (Buffer 3) Rx Frame Data9 (Buffer 3) Rx Frame Data10 (Buffer 3) Rx Frame Data11 (Buffer 3) Rx Frame Data12 (Buffer 3) Rx Frame Data13 (Buffer 3) Rx Frame Data14 (Buffer 3) Rx Frame Length (Buffer 3) 11 RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [4:0] RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO RO [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [4:0] CEC Register Map Changes – CEC Rx (4) The Rx Enable bit was also removed (R0x26[0]) The ADV7511’s CEC Rx is ready to receive messages upon power-up Added three 2-bit Time Stamp registers for Buffers 3, 2, and 1 (0x26[5:4],0x26[3:2],0x26[1:0]) Specifies the order in which the message in the current buffer was received relative to the other buffers 00 – no valid message 01 – first received of current buffered messages 10 – second received of current buffered messages 11 – third received of current buffered messages Added 12 on ADV7511: Address Type Bits Register Name 0x26 [5:4] [3:2] [1:0] Rx 3 Time Stamp Rx 2 Time Stamp Rx 1 Time Stamp R/W CEC Register Map Changes – CEC Rx (5) Added Rx Ready (0x49[2], 0x49[1], and 0x49[0]) and Clear Rx Ready (0x4A[2], 0x4A[1], and 0x4A[0]) for buffers 3, 2, and 1 Status Added register and clearing register for available messages Use All Buffers (0x4A[3]) Selects between 1 message buffering and 3 message buffering mode Added on ADV7511: Address 0x49 0x4A 13 Type R/W R/W Bits Register Name [2] Rx 3 Ready [1] Rx 2 Ready [0] Rx 1 Ready [3] Use All Buffers [2] Clear Rx 3 Ready [1] Clear Rx 2 Ready [0] Clear Rx 1 Ready CEC Register Map Changes – Op Code Interrupts Added eight one byte “Wake Up Op Code” registers (0x77 – 0x7E) These registers set op codes to trigger interrupts (found in register 0x92 and 0x93 of the main register map) Standard CEC op codes requiring a response are the default The user can customize the op codes using I2C writes 14 Added on ADV7511 (CEC Map): Address Type Bits Register Name 0x77 RO [7:0] Wake Up Op Code 1 0x78 RO [7:0] Wake Up Op Code 2 0x79 RO [7:0] Wake Up Op Code 3 0x7A RO [7:0] Wake Up Op Code 4 0x7B RO [7:0] Wake Up Op Code 5 0x7C RO [7:0] Wake Up Op Code 6 0x7D RO [7:0] Wake Up Op Code 7 0x7E RO [7:0] Wake Up Op Code 8 Main Register Map Changes (for CEC) CEC Interrupt Registers Added Interrupt Enables for Opcode Wakeup (0x92) Added Interrupts for Opcode Wakeup (0x93) Added Interrupt Enables for Rx Ready 2-0 (0x95[2:0]) Added Interrupts for Rx Ready 2-0 (0x97[2:0]) 15 Added on ADV7511 (Main Map): Address Type Bits [7] [6] [5] [4] 0x92 R/W [3] [2] [1] [0] [7] [6] [5] [4] 0x93 R/W [3] [2] [1] [0] [2] 0x95 R/W [1] [0] [2] 0x97 R/W [1] [0] Register Name Wake Up Op Code 1 Interrupt Enable Wake Up Op Code 2 Interrupt Enable Wake Up Op Code 3 Interrupt Enable Wake Up Op Code 4 Interrupt Enable Wake Up Op Code 5 Interrupt Enable Wake Up Op Code 6 Interrupt Enable Wake Up Op Code 7 Interrupt Enable Wake Up Op Code 8 Interrupt Enable Wake Up Op Code 1 Interrupt Wake Up Op Code 2 Interrupt Wake Up Op Code 3 Interrupt Wake Up Op Code 4 Interrupt Wake Up Op Code 5 Interrupt Wake Up Op Code 6 Interrupt Wake Up Op Code 7 Interrupt Wake Up Op Code 8 Interrupt Rx Ready 3 Interrupt Enable Rx Ready 2 Interrupt Enable Rx Ready 1 Interrupt Enable Rx Ready 3 Interrupt Rx Ready 2 Interrupt Rx Ready 1 Interrupt CEC CDC HPD and Arbitration In HDMI 1.4, special rules for CDC message arbitration were defined ADV7511 can either enable or disable this special arbitration using CDC Arbitration Enable Register 0x7F[7] in the CEC Register Map Added HPD Control Register 0xD6[7:6] in the Main Register Map 00 = HPD is from both HPD pin and CDC HPD 01 = HPD is from CDC HPD 10 = HPD is from HPD pin 16 11 = HPD is always high CEC CDC HPD and Arbitration New Registers in CEC Map Address 0x7F 0x80 Type R/W R/W Default Value Register Name Function 1******* CDC Arbitration Enable Controls whether to do special CDC messsage arbitration upon receiving CDC messsage 1 = enable 0 = disable [6] *1****** CDC HPD Response Enable Controls whether to toggle internal HPD signals when receving CDC HPD messsage 1 = enable 0 = disable [15:0] 00000000 CEC Physical Address Physical address of CEC device Bits [7] 0x81 17 00000000 0x82 R/W [7:0] 00000001 CDC HPD Timer Count Controls the time CDC HPD stays low when receiving CDC HPD toggle message. HPD low = CDC_HPD_Timer_Count * CEC_CLK. CEC_CLK is 760KHz by default. 0x83 RO [7] 0******* CDC HPD HPD signal from CEC interface HDCP Adjustments Added Delay can be controlled throughout each step of the HDCP authentication procedure New Registers HDCP Ri Checking Frequency 0xFC[7:6] HDCP Ri Checking Position Delay 0xFC[5:3] HDCP BCAPS Read Delay 0xFC[2:0] HDCP An Write Delay 0xFD[7:5] HDCP AKSV Write Delay 0xFD[4:2] HDCP Start Delay 0xFE[7:5] 18 HDCP New Registers Address Type Bits Default Value Register Name Function 0xFC R/W [7:6] 00****** Ri Checking Freqyency [5:3] **000*** Ri Checking Position Delay [2:0] *****000 BCAPS Read Delay [7:5] 000***** An Write Delay [4:2] ***000** ASKV Write Delay [7:5] 000***** HDCP Start Delay Ri Checking Freqyency 00 = 128 frames 10 = 64 frames 10 = 32 frames 11 = 16 frames Ri Checking Position Delay in Units of Hsync 0 = no delay 1 = 8 Hsyncs 2 = 16 Hsyncs 3 = 32 Hsyncs 4 = 64 Hsyncs 5 = 128 Hsyncs 6 = 256 Hsyncs 7 = 512 Hsycns Delay Between Reading of BKSV and BCAPs 000 = no delay 001 = 1ms 010 = 2ms 011 = 5ms 100 = 10ms 101 = 25ms 110 = 50ms 111 = 100ms Delay Between Reading of BCAPS and Writing of An 000 = no delay 001 = 1ms 010 = 2ms 011 = 5ms 100 = 10ms 101 = 25ms 110 = 50ms 111 = 100ms Delay Between Writing of An and Writing of AKSV 000 = no delay 001 = 1ms 010 = 2ms 011 = 5ms 100 = 10ms 101 = 25ms 110 = 50ms 111 = 100ms Delay Between Setting Enable HDCP Register 0xAF[7] = 1 and Reading of BKSV 000 = no delay 001 = 1ms 010 = 2ms 011 = 5ms 100 = 10ms 101 = 25ms 110 = 50ms 111 = 100ms 0xFD 0xFE 19 R/W R/W CSC and Packet Update Feature To avoid sending partially updated packets, a packet update features has been added for CSC and all HDMI packets The packet/CSC update bit should be set to 1 before updating registers related to the packet or CSC, then set to 0 when updating is complete CSC CSC Coefficient Update register –0x1A[5] The CSC Coefficient Update includes timing control to ensure that the coefficients are updated during the blanking period Does not include the “scaling factor” bits (R0x18[6:5]) – changes to these bits take effect immediately Added 20 CSC and Packet Update Feature Note: Since Packet Update Memory is shared, only one packet can use the feature at one time 21 Packet Type Control Bits AVI InfoFrame Main map 0x4A[6] Audio InfoFrame Main Map 0x4A[5] General Control Packet Main Map 0x4A[4] Source Product Description Packet Packet Memory 0x1F[7] MPEG InfoFrame Packet Memory 0x3F[7] Audio Content Protection Packet Packet Memory 0x5F[7] ISRC 1 Packet Packet Memory 0x7F[7] ISRC 2 Packet Packet Memory 0x9F[7] Gamut Metadata Packet Packet Memory 0xBF[7] Spare Packet 1 Packet Memory 0xDF[7] Spare Packet 2 Packet Memory 0xFF[7] Video Input Detection Low Refresh Rate (VID Detection) – Register 0xFB[2:1] Added 00 = Non Low Refresh Rate 01 = 24Hz 10 = 25Hz 11 = 30Hz Removed 22 Low Refresh Rate Video Register (0x48[7]) Video Data Range Clipping Video Data Range Clipping registers were moved from 0x530x5A in the CEC map to 0xC0-0xC7 in the CEC Map Address Type Bits Default Value Register Name Function 0x53 R/W [11:0] ****0000 Y or RGB Minimum Minumum value for Y or RGB for video data clipping. Y or RGB Maximum Maximum value for Y or RGB for video data clipping. CbCr Minimum Minimum value for Cb/Cr for video data clipping CbCr Maximum Maximum value for Cb/Cr for video data clipping. 0x54 ADV7510 ADV7511 0x55 00000000 R/W [11:0] R/W [11:0] R/W [11:0] Address Type Bits Default Value Register Name Function 0xC0 R/W [11:0] ****0000 Y or RGB Minimum Minumum value for Y or RGB for video data clipping. Y or RGB Maximum Maximum value for Y or RGB for video data clipping. CbCr Minimum Minimum value for Cb/Cr for video data clipping CbCr Maximum Maximum value for Cb/Cr for video data clipping. 0x56 0x57 0x58 0x59 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 23 ****1111 11111111 ****0000 00000000 ****1111 00000000 R/W [11:0] R/W [11:0] R/W [11:0] ****1111 11111111 ****0000 00000000 ****1111 Miscellaneous Changes Chip ID Added Chip ID 0xF5-0xF6 = 0x7511 Added Chip ID Suffix 0xF7 = 0x00 Added TMDS Clock Inversion bit 0xDE[3] Address Type Bits Default Value Register Name Function 0xDE R/W [3] ****0*** TMDS Clock Inversion TMDS Clock Inversion 0 = Normal TMDS Clock 1 = Inverted TMDS Clock Added Internal HPD Pull-down Resistor Allows user to remove recommended 10k pull-down Controlled by register 0xE0[0] Address 0xE0 24 Type R/W Bits [0] Default Value *******0 Register Name Function HPD Pull Down HPD Pull Down 0 = No Internal HPD Pulldown 1 = Weak Internal HDP Pulldown Active Fixed Register Changes The following tables reflect changes to the “fixed” registers and their recommended settings 25 Register ADV7510 Setting ADV7511 Setting 0x9A[7:1] Default Set to 0b1110000 0xDE Set 0x9C Default 0xE0 Default Set to 0xD0 0xF9 Default Set to 0x00