Product Overview MC100LVEP14: 2.5 V / 3.3 V 1:5 Differential ECL/PECL/HSTL Clock / Data Fanout Buffer For complete documentation, see the data sheet Product Description The MC100LVEP14 is a low skew 1 to 5 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The ECL/PECL input signals can be either differential or single-ended (if the VBB output is used). HSTL inputs can be used when the LVEP14 is operating under PECL conditions. Features • • • • • • • • 100 ps Device-to-Device Skew 25 ps Within Device Skew 400 ps Typical Propagation Delay Maximum Frequency > 2 GHz Typical PECL and HSTL Mode: VCC = 2.375 V to 3.8 V with VEE = 0 V NECL Mode: VCC = 0 V with VEE = -2.375 V to -3.8 V LVDS Input Compatible Open Input Default State Part Electrical Specifications Product Compliance Status Type Chann els Input / Input Output Level Ratio Output VCC Level Typ (V) tJitterR MS Typ (ps) tskew(oo) Max (ps) tpd Typ (ns) tR & tF Max (ps) fmaxClo fmaxDat Packa ck Typ a Typ ge (MHz) (Mbps) Type MC100LVEP14DTG Pb-free Active Buffer 1 2:1:5 ECL 0.181 25 0.4 225 2000 TSSO P-20 0.181 25 0.4 225 2000 TSSO P-20 Halide free HST L 2.5 3.3 CML ECL LVD S MC100LVEP14DTR2G Pb-free Halide free Active Buffer 1 2:1:5 LVD S ECL 3.3 2.5 HST L CML ECL For more information please contact your local sales support at www.onsemi.com Created on: 6/30/2016