MM908E621ACDWBTAD, Thermal Data, Integrated Quad Half-Bridge and Triple High-Side with Embedded MCU and LIN for High End...

908E621ACDWBTAD
Rev 1.0, 09/2005
Freescale Semiconductor
Technical Data
Integrated Quad Half-Bridge and
Triple High-Side with Embedded MCU
and LIN for High End Mirror
Thermal Addendum
908E621ACDWB
54-TERMINAL
SOICW-EP
Introduction
This thermal addendum ia provided as a supplement to the MM908E621
technical data sheet. The addendum provides thermal performance information
that may be critical in the design and development of system applications. All
electrical, application and packaging information is provided in the data sheet.
Package and Thermal Considerations
This MM908E621 is a dual die package. There are two heat sources in the
package independently heating with P1 and P2. This results in two junction
temperatures, TJ1 and TJ2, and a thermal resistance matrix with RθJAmn.
For m, n = 1, RθJA11 is the thermal resistance from Junction 1 to the reference
temperature while only heat source 1 is heating with P1.
For m = 1, n = 2, RθJA12 is the thermal resistance from Junction 1 to the
reference temperature while heat source 2 is heating with P2. This applies to
RθJ21 and RθJ22, respectively.
TJ1
TJ2
=
RθJA11 RθJA12
RθJA21 RθJA22
.
DWB SUFFIX
98ARL105910
54-TERMINAL SOICW-EP
Note For package dimensions, refer to the
908E621 device datasheet.
P1
P2
The stated values are solely for a thermal performance comparison of one package to another in a standardized environment.
This methodology is not meant to and will not predict the performance of a package in an application-specific environment. Stated
values were obtained by measurement and simulation according to the standards listed below.
Standards
Table 1. Thermal Performance Comparison
1.0
1 = Power Chip, 2 = Logic Chip [°C/W]
Thermal
Resistance
m = 1,
n=1
m = 1, n = 2
m = 2, n = 1
m = 2,
n=2
RθJAmn (1)(2)
23
20
24
(2)(3)
9.0
6.0
10
RθJAmn (1)(4)
52
47
52
RθJCmn (5)
1.0
0
2.0
RθJBmn
Notes:
1. Per JEDEC JESD51-2 at natural convection, still air
condition.
2. 2s2p thermal test board per JEDEC JESD51-7and
JESD51-5.
3. Per JEDEC JESD51-8, with the board temperature on the
center trace near the power outputs.
4. Single layer thermal test board per JEDEC JESD51-3 and
JESD51-5.
5. Thermal resistance between the die junction and the
exposed pad, “infinite” heat sink attached to exposed pad.
© Freescale Semiconductor, Inc., 2005. All rights reserved.
1.0
0.2
0.2
* All measurements
are in millimeters
Soldermast
openings
Thermal vias
connected to top
buried plane
54 Terminal SOIC-EP
0.65 mm Pitch
17.9 mm x 7.5 mm Body
10.3 mm x 5.1 mm Exposed Pad
Figure 1. Thermal Land Pattern for Direct Thermal
Attachment Per JEDEC JESD51-5
PTC4/OSC1
PTC3/OSC2
PTC2/MCLK
PTB5/AD5
PTB4/AD4
PTB3/AD3
1
54
2
53
3
52
4
51
5
50
6
49
IRQ
RST
7
48
8
47
(PTD0/TACH0/BEMF -> PWM)
PTD1/TACH1
9
46
10
45
RST_A
IRQ_A
11
44
LIN
A0CST
A0
GND1
HB4
VSUP1
GND2
HB3
VSUP2
NC
NC
TESTMODE
GND3
HB2
VSUP3
13
12
14
15
43
42
Exposed
Pad
41
40
16
39
17
38
18
37
19
36
20
35
21
34
22
33
23
32
24
31
25
30
26
29
27
28
A
PTA0/KBD0
PTA1/KBD1
PTA2/KBD2
FLSVPP
PTA3/KBD3
PTA4/KBD4
VDDA/VREFH
EVDD
EVSS
VSSA/VREFL
(PTE1/RXD <- RXD)
VSS
VDD
HVDD
L0
H0
HS3
VSUP8
HS2
VSUP7
HS1b
HS1a
VSUP6
VSUP5
GND4
HB1
VSUP4
908E621 Terminal Connections
54-Terminal SOICW-EP
0.65 mm Pitch
17.9 mm x 7.5 mm Body
10.3 mm x 5.1 mm Exposed Pad
Figure 2. Thermal Test Board
Device on Thermal Test Board
Material:
Outline:
Single layer printed circuit board
FR4, 1.6 mm thickness
Cu traces, 0.07 mm thickness
80 mm x 100 mm board area,
including edge connector for
thermal testing
Area A:
Cu heat-spreading areas on board
surface
Ambient Conditions:
Natural convection, still air
Table 2. Thermal Resistance Performance
Thermal
Resistance
RθJAmn
RθJSmn
Area A
(mm2)
1 = Power Chip, 2 = Logic Chip (°C/W)
m = 1,
n=1
m = 1, n = 2
m = 2, n = 1
m = 2,
n=2
0
53
48
53
300
39
34
38
600
35
30
34
0
21
16
20
300
15
11
15
600
14
9.0
13
RθJA is the thermal resistance between die junction and
ambient air.
RθJSmn is the thermal resistance between die junction and
the reference location on the board surface near a center
lead of the package (see Figure 2)
This device is a dual die package. Index m indicates the
die that is heated. Index n refers to the number of the die
where the junction temperature is sensed.
908E621ACDWB
2
Analog Integrated Circuit Device Data
Freescale Semiconductor
Thermal Resistance [ºC/W]
60
50
40
30
20
10
0
x
RθJA11
RθJA22
RθJA12 = RθJA21
0
300
600
Heat spreading area A [mm²]
Figure 3. Device on Thermal Test Board RθJA
Thermal Resistance [ºC/W]
100
10
1
x
0.1
1.00E-03
1.00E-02
RθJA11
RθJA22
RθJA12 = RθJA21
1.00E-01 1.00E+00 1.00E+01 1.00E+02 1.00E+03 1.00E+04
Time[s]
Figure 4. Transient Thermal Resistance RθJA (1.0 W Step Response)
Device on Thermal Test Board Area A = 600 (mm2)
908E621ACDWB
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
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908E621ACDWBTAD
Rev 1.0
09/2005
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