ANALOG IP BLOCK LVDS_RX - CMOS LVDS Receiver DATA SHEET PROCESS DESCRIPTION C35B3 (0.35um) The LVDS_RX is a differential line receiver designed for applications requiring high data rates. The device supports data rates up to 1Gb/s (500MHz). The LVDS_RX accepts (350mV) differential input signals and translates them to CMOS output levels. FEATURES LVDS_RX area: 0.084mm2, LVDS_RX size: x = 241.1µm y = 345.7µm RXBIAS area: 0.08mm2, RXBIAS size: x = 332.4µm y = 239.3µm 3.3V ±10% supply voltage Accepts small swing (100mV) differential signal levels 1Gb/s maximum transmission speed 1.7ns maximum propagation delay Power dissipation 30mW at 3.3V, static, without RXBIAS Junction temperature –40 - 125°C Compatible with IEEE 1596.3 SCI LVDS standard except Common Mode Input Voltage range Internal 100Ω termination resistor Power down mode Revision E, 02.11.2004 With the companion line driver (LVDS_TX ) it provides a new alternative to high power pseudo-ECL devices for high speed applications. The LVDS_RX requires the cell RXBIAS for biasing. RXBIAS can drive up to 3 LVDS_RX cells. An external voltage reference must be used. The LVDS_RX is designed as pad cell and has the same high (y-size) as austriamicrosystems AG standard pad cells with separated substrate. page 1 of 6 Datasheet: LVDS_RX - C35 TECHNICAL DATA FOR LVDS_RX (Tjunction = −40 to 125°C, VDDA = 3.0V to 3.6V, VSSA = VSUB = 0V, VREF = 1.25V, PD = low, unless otherwise specified) DC CHARACTERISTICS Symbol VID Parameter VICM Conditions Differential Input VID = |VINP – VINN| Min 100 Typ 350 Max 450 Units mV Common Mode Input Voltage 0.05 1.25 1.95 V 0.1 1.425 2 V 1.075 1.9 VICM = (VINP + VINN) / 2 VIH Input Voltage High VIL Input Voltage Low 0 VHYS Hysteresis 1) 25 VOH Output Voltage High VOL Output Voltage Low V mV V CMOS levels V AC CHARACTERISTICS Symbol tPLHD Parameter Different. Propagation Delay Low to High Conditions Cload = 1pF 2) tPHLD Different. Propagation Delay High to Low Cload = 1pF 2) Min Max 1.7 Unit ns 1.1 1.7 ns 2) 350 ps 380 ps tSKD1 Differential Pulse Skew |tPLHD – tPHLD| 3) Cload = 1pF @ 1Gb/s tSKD2 Differential Channel to Channel Skew Cload = 1pF @ 1Gb/s 1) 2) 4) Typ 1.1 tTLHD Differential Output Rise Time Cload = 1pF 300 600 ps tTHLD Differential Output Fall Time Cload = 1pF 2) 4) 300 600 ps tP Power Up Time Cload = 1pF 8 20 ns Cload Load Capacitance @1Gb/s Cin Input Capacitance fMAX TXS 1 pF 700 fF Maximum Operating Frequency 5) 500 MHz Transmission Rate 1000 Mb/s Max 36 30 Unit mA mA 550 POWER REQUIREMENTS Symbol IOS IOSD Parameter Output Short Circuit Current Differential Output Short Circuit Current Conditions Outputs shorted to VSSA VOUTP and VOUTN shorted No RXBIAS Min Typ 24 20 ICCDC DC Current Consumption ICCAC AC Current Consumption Cload = 1pF @1Gb/s, no RXBIAS ICCPD Power Down Current Consumption PD = high, no RXBIAS Pdiss_DC DC Power Consumption No RXBIAS 29.7 50.4 mW Pdiss_AC AC Power Consumption No RXBIAS 56.1 93.6 mW Pdiss_PD Power Consumption in Power Down Mode PD = high, no RXBIAS 36 µW 9 14 mA 17 26 mA 10 µA 1) 25mV hysteresis means that an differential input signal must change by more than this value to change the receiver output stage Including the package: SOIC28, pins 5–10 or 19–24 for VINP and VINN 3) tSKD1 is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the same channel 4) Specified at 20% and 80% of the output voltage (IEEE 1596.3 SCI LVDS Standard) 5) fMAX generator input conditions: tr = tf < 500ps, 50% duty cycle, output criteria: VOL < 0.4V, VOH > 2.7V 2) Revision E, 02.11.2004 Page 2 of 6 Datasheet: LVDS_RX - C35 TECHNICAL DATA FOR RXBIAS (Tjunction = −40 to 125°C, VDDA = 3.0V to 3.6V, VSSA = VSUB = 0V, PD = low, unless otherwise specified) POWER REQUIREMENTS Symbol ICC Parameter Current Consumption ICCPD Power Down Current Consumption Pdiss Power Consumption Pdiss_PD Power Consumption in Power Down Mode Conditions Min Typ 0.5 1.65 PD = high Max 1 Unit mA 200 nA 3.3 mW 720 nW Max 1.3 Unit V EXTERNAL REFERENCE CHARACTERISTICS Symbol VREF Parameter External Reference Voltage Conditions Min 1.2 Typ 1.25 AC WAVEFORMS FOR LVDS_RX VINN VIH = 1.425V 1.25V 1.25V VID = 350mV VINP VIL = 1.075V tPLHD tPHLD VOUTN VOH = 3V 1.5 V 1.5 V VOUTP VOL = 0V +3V 80% VOUTP - VOUTN 80% 0V 0V 20% 20% -3V tTLHD Revision E, 02.11.2004 tTHLD Page 3 of 6 Datasheet: LVDS_RX - C35 TYPICAL PERFORMANCE CURVES 50,0 VID 3,60 = 350mV VOL Output Voltage Low [mV] VOH Output Voltage High [V] 3,80 Tjunc = 25°C IOH = 1mA 3,40 3,20 3,00 VID 48,0 = -350mV Tjunc = 25°C IOL = 1mA 46,0 44,0 42,0 2,80 40,0 3,0 3,1 3,2 3,3 3,4 3,5 3,6 3,0 3,1 VDD Power Supply Voltage [V] 3,3 3,4 3,5 3,6 VDD Power Supply Voltage [V] Output Voltage High vs. Power Supply Voltage Output Voltage Low vs. Power Supply Voltage 17,0 24,0 23,0 16,0 VOD = 0V T 22,0 ICCAC AC Current Consumption [mA IOSD Differential Output Short Circuit Current [mA 3,2 = 25°C 21,0 20,0 19,0 18,0 17,0 VDDA = 3.3V 15,0 VID = | 350mV | 14,0 CL = 1pF 13,0 Tjunc = 25°C 12,0 11,0 10,0 9,0 16,0 3,0 3,1 3,2 3,3 3,4 3,5 3,6 VDD Power Supply Voltage [V] Differential Output Short Circuit Current vs. Power Supply Revision E, 02.11.2004 8,0 0,01 0,10 1,00 10,00 100,00 Frequency [MHz] Current Consumption vs. Frequency Page 4 of 6 1000,00 Datasheet: LVDS_RX - C35 SYMBOL OF LVDS_RX PIN LIST OF LVDS_RX PD Low VINP High VINN Low VOUTP High VOUTN Low Low Low High Low High High High Low High Low High Low High High Low SYMBOL OF RXBIAS Pin IB_140u Description Bias Current Type Analog VCM Common Mode Voltage Analog VINP Positive LVDS Input Analog VINN Negative LVDS Input Analog PD Power Down Digital VOUTP Positive Output Digital VOUTN Negative Output Digital The LVDS_TX is designed as a pad cell and so there are no supply pins shown on the symbol. The cell is compatible to the austriamicrosystems AG power bus with additional substrate bus. PIN LIST OF RXBIAS PD Low VCM VREF IBx_140u 140uA High Low High-Z Pin VDDA Description Positive Supply Type Supply VSSA Negative Supply Supply VSUB Substrate Supply IB1_140u IB2_140u IB3_140u Bias Current Analog VCM Common Mode Voltage Analog PD Power Down Digital VREF External Reference Voltage Analog THEORY OF OPERATION The LVDS_RX is a differential line receiver which accepts low voltage input signals according to the IEEE 1596.3 SCI LVDS standard. The 100Ω differential input termination is provided internally, therefore only 50Ω transmission lines are needed (no external termination resistor is necessary). Revision E, 02.11.2004 Page 5 of 6 Datasheet: LVDS_RX - C35 APPLICATION High Speed Backplane Driver Complementary Clock Drivers Level Translator System Interconnects ATM Applications Revision E, 02.11.2004 SDH Applications High-Resolution Imaging Applications Laser Printers Digital Copiers Page 6 of 6 TYPICAL APPLICATION 1)2)3)4)5) external chip internal SNAP BACK 3) VREF 4) VREF (ext. reference) 1nF 180pF VSSA CLK complementary CMOS signals (to digital core) 50Ω transmission lines CLK_N from transmitter SDATA complementary CMOS signals (to digital core) 50Ω transmission lines SDATA_N from transmitter SYNC complementary CMOS signals (to digital core) 50Ω transmission lines SYNC_N from transmitter 2) 5) 5) 5) VSSA 1) VDDA 1 µF 100pF 1) VDDA 22pF 4) 5) 4) 5) VSSA SNAP BACK 3) 1) The two supply pads can be bonded to one package pin (double bonding) The substrate pin must be connected on PCB level to VSSA 3) The LVDS part of the chip has to be separated from the rest of the chip using snap back devices (cell PWRCUT_DIG_P_SNAP_SNAP_3B) 4) The cells VDD3R1_3B, VDD3R2O_3B and APRIO200P_3B_R2O are not in the standard library, they are part of the IP-block 5) The supply pads are connected to the LVDS_TX via the periphery power supply bus 2) © Austria Mikro Systeme International AG Page 7 of 7 Datasheet: LVDS_RX - C35 Contact Copyright austriamicrosystems AG A 8141 Schloss Premstätten, Austria T. +43 (0) 3136 500 5333 F. +43 (0) 3136 500 5755 [email protected] Copyright © 2004 austriamicrosystems. Trademarks registered ®. All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. To the best of its knowledge, austriamicrosystems asserts that the information contained in this publication is accurate and correct. Revision E, 02.11.2004 Page 8 of 6