AMSCO FLASH6_C3

ANALOG IP BLOCK
FLASH6 - CMOS 6-Bit FLASH A/D CONVERTER
DATA SHEET
PROCESS
DESCRIPTION
C35B3 (0.35um)
The FLASH6 is a complete analog to digital converter
cell which operates from a single supply. It performs
sampling, analog-to-digital conversion, generating a
6 bit value in parallel form. The output word rate can be
up to 100MS/s. The output data format is compatible
FEATURES
!
Small Area < 0.257 mm2
!
!
!
!
!
!
!
Size x= 361 µm y= 710 µm
Supply Voltage 3.0-3.6 V
Junction Temp. Range -40 - 125°C
Resolution 6-Bit
Maximum Sampling Rate 100MS/s
Low Input Capacitance < 5pF
Output Code Binary
with most µP and digital signal processors.
VREFP
VREFN
IB IA S
R e s is to r L a d d e r
PD
O VL
C o m p a ra t o rs
V IN
VDD A
C LK
E rro r C o rre c tio n /R O M /O u tp u t L a tc h
VSSA
T im in g
VD D
6 B it B u s
STROBE
VSS
D AT A<0> D AT A<1> D AT A<2> D AT A <3> D A T A<4> D AT A<5>
Revision B, 07.09.02
Page 1 of 9
Data Sheet : FLASH6 - C35
TECHNICAL DATA
(Tjunction = -40 to 125 °C, VDDA=VDD=+3.0V to +3.6V, fclk = 100MHz, VREFP and VREFN as specified, pad resistors as specified in the
functional block diagram, unless otherwise specified)
DC ACCURACY
Symbol
Parameter
Resolution (No missing Code)
DNL
Differential Linearity Error
Conditions
Min
6
Typ
6
Max
6
Units
Bit
-0.8
±0.4
+0.8
LSB
±0.4
INL
Integral Linearity Error
-0.8
+0.8
LSB
OFF
Offset Error
-2
+2
LSB
GAINERR
Gain Error
-2
+2
LSB
Max
Units
uA
CHARACTERISTICS
Symbol
IBIAS
Parameter
Bias sink current
Conditions
Min
Typ
30
Conditions
Min
1.8
Typ
2.4
Max
2.8
Units
V
0.35
0.4
0.6
V
1.2
2
2.45
V
REFERENCE CHARACTERISTICS
Symbol
VREFP
Parameter
Pos. Reference Voltage
VREFN
Neg. Reference Voltage
VREF
Difference between VRP and VRN
Rref
Reference Impedance
VREFP-VREFN
1)
TKRref
380
Ohm
1.2
mOhm/K
ANALOG INPUT
Symbol
Vin
Parameter
Input Voltage Range
Rin
Input Impedance
Conditions
Min
VREFN
Typ
Max
VREFP
100
Units
V
MOhms
Cin
5
pF
Max
Units
dB
AC ACCURACY (VREFP=2.4V, VREFN=0.4V)
Symbol
THD
Parameter
Total Harmonic Distortion
Conditions
fin=1MHz
Min
Typ
-41.3
THD
Total Harmonic Distortion
fin=30MHz
SFDR
Spurious Free Dynamic Range
fin=1MHz
46.2
dB
SFDR
Spurious Free Dynamic Range
fin=30MHz
46.2
dB
SNR
Signal to Noise Ratio
fin=1MHz
35.88
dB
SNR
Signal to Noise Ratio
fin=30MHz
34.1
dB
SINAD
Signal to (Noise+Dist.) Ratio
fin=1MHz
34.8
dB
SINAD
Signal to (Noise+Dist.) Ratio
fin=30MHz
33.3
dB
ENOB
Effective Number of Bits
fin=1MHz
5.5
Bit
ENOB
Effective Number of Bits
fin=30MHz
5.24
Bit
-41.3
dB
1) VREFP to VREFN
Revision B, 07.09.02
Page 2 of 9
Data Sheet : FLASH6 - C35
DIGITAL INPUTS AND OUTPUTS
Symbol
VDD
Parameter
Pos. digital Supply Voltage
Conditions
VDD=VDDA
Min
3.0
Typ
3.3
Max
3.6
Units
V
VSS
Neg. digital Supply Voltage
VSS=VSSA
0
0
0
V
VIL
Digital Input Level
0.3*VDD
V
VSS
VIH
0.7*VDD
VOL
Digital Output Level
VOH
VDD
V
VSS
V
VDD
V
POWER REQUIREMENTS
Symbol
VDDA
Parameter
Pos. analog Supply Voltage
Conditions
VDD=VDDA
Min
3.0
Typ
3.3
Max
3.6
Units
V
VSSA
Neg. analog Supply Voltage
VSS=VSSA
0
IDD
1) 3)
IDDA
1) 3)
0
0
V
Supply Current Digital
7.5
15
mΑ
Supply Current Analog
4
8
mA
Psup 1) 3)
Supply Power Consumption Power Up
Mode
38
82,8
mW
IREF 1) 3)
Reference Current
5
10
mA
Pdiss_tot 1) 3)
Total Power Consumption
54,5
118,8
mW
Pdiss_pd 2) 3)
Total Power Consumption
Power Down Mode
30
60
mW
incl. Ref.
TIMING CHARACTERISTICS
Symbol
1/Tconv
Parameter
Conversion Rate
Conditions
Min
0.1
Typ
80
Max
100
Units
MS/sec
fclk
Master CLOCK Frequency
Tdap
Aperture Delay
0.1
80
100
MHz
Tconv
Total Conversion Time
1
clk cycle
Tpwhclk
CLOCK Pulse width High
5
6.5
nsec
Tpwlclk
CLOCK Pulse width Low
5
6.5
1.8
ns
nsec
1*e-3/fin
Jclk
CLOCK Jitter
Tdcs
Delay Time CLOCK to STROBE
5.5
nsec
Tsuds
Setup Time DATA to STROBE
0.8
nsec
Tdp
Delay Time Pipeline
1
nsec
Twakeupall
Wake up Time all
50
nsec
Twakeup
Wake up Time
Twkupall Tdap
nsec
1)
Measured during a conversion with 100MHz clock frequency.
2)
3)
After 10µs power down.
The measurement includes 8 digital (8mA) output pads.
Revision B, 07.09.02
Page 3 of 9
sec
Data Sheet : FLASH6 - C35
CODE TABLE
1LSB = (VREFP - VREFN) / 64.
Revision B, 07.09.02
Output Code
00 0000
Input Voltage: VIN-VINB
VREFN…..0.5LSB
00 0001
0.5LSB…..1.5LSB
00 0010
1.5LSB…..2.5LSB
…
…
11 1111
62.5LSB…..VREFP
Page 4 of 9
Data Sheet : FLASH6 - C35
TYPICAL PERFORMANCE CHARACTERISTICS
INL [LSB]
DNL [LSB]
(Tjunction=25°C, VDDA=VDD=+3.3V, fclk=100MHz, VREFP=+2.4V and VREFN=0.4V, unless otherwise specified)
Digital Code
Digital Code
FFT [dBc]
INL
FFT [dBc]
DNL
Input Signal Frequency [Hz]
Input Signal Frequency [Hz]
Spectrum @30MHz 1)
ENOB [Bit]
ENOB [Bit]
Spectrum @1MHz 1)
pg
VREFP-VREFN [V]
ENOB vs (VREFP-VREFN) @30MHz
1)
Input Signal Frequency [Hz]
ENOB vs Input Signal Frequency
The spectrum consists of 1024 pins
Revision B, 07.09.02
Page 5 of 9
Data Sheet : FLASH6 - C35
SYMBOL
PINLIST
VDDA
Pin
VIN
Description
Input Voltage
Typ
AIN
VREFP
Pos. Reference
Voltage
AIN
VREFN
Neg. Reference
Voltage
AIN
IBIAS
Bias Current
AIN
PD
Power down
Signal
DIN
0.1pF
CLK
Master Clock
DIN
0.1pF
DATA<5:0>
Data Output
(DATA<5>=MSB)
DOUT
OVL
OVL
Overload
DOUT
STROBE
STROBE
Data Strobe Signal
DOUT
VDDA
Pos. Analog
Supply
S
VSSA
Neg. Analog
Supply
S
SHIELD
Connect to VSSA
S
VDD
Pos. Digital
Supply
S
VSS
Neg. Digital
Supply
S
VDD
VREFP
VIN
6
A
DATA<5:0>
D
VREFN
Cap
5pF
IBIAS
FLASH6
PD
CLK
SHIELD
VSSA
VSS
THEORY OF OPERATION
The Macro Cell FLASH6 is a 6-bit single step parallel analog to
digital converter. The architecture is based on a 380 Ohm
polysilicon resistor reference ladder and static CMOS comparators.
The thermometer code of the comparator outputs is encoded in a
fast ROM encoder into straight binary code with CMOS logic signal
levels. The last comparator output is connected unlatched to the
OVL output. The area of the converter is small. The comparators do
not need auto zeroing and therefore are fast and perform minimal
kickback on the analog signal input. The conversion range is set by
the reference inputs VREFP and VREFN. The output OVL indicates
an overload condition when Vin > (VREFP - 0.5*LSB).
POWER SUPPLIES
The converter requires a single +3.3V power supply. The supplies
for analog and digital are separated and may be connected
together. However, for maximum noise immunity it is
Revision B, 07.09.02
recommended to wire them on chip to separated pins, especially
when the block is embedded in a large digital circuit. The supplies
may then be connected together on PC-board level.
The proper use of blocking capacitors in the application is important
REFERENCE VOLTAGE
Both input pads VREFP and VREFN must have a 0 Ohm protection
resistor. The ESD test was performed with ±1kV (Norm: MIL 883 E
method 3015).
The proper use of blocking capacitors in the application is
important !
INPUT VOLTAGE
The input pad VIN must have a 0 Ohm protection resistor. The ESD
test was performed with ±1kV (Norm: MIL 883 E method 3015).
Page 6 of 9
Data Sheet : FLASH6 - C35
FUNCTIONAL BLOCK DIAGRAM
FLASH6
VIN
OVL
VREFP
Rref
.
.
.
.
.
.
.
.
.
E
R
R
O
R
C
O
R
R.
VREFN
VDDA
VSSA
ROM
VDD
VSS
6
LATCH
DATA<5:0>
PD
IBIAS
CLK
STR
TIMING
TIMING DIAGRAM OF FLASH6
Sample N
Sample N+1
Vin
Sample N+2
Tdap
Tdcs
Tpwlclk
Tpwhclk
CLK
STROBE
DATA<0:5>
Sample N-2
Sample N-1
Sample N
Tsuds
Revision B, 07.09.02
Page 7 of 9
Data Sheet : FLASH6 - C35
TYPICAL APPLICATION
+3.3V
+3.3V
VDDA
15nF
VDD
1.2nF
0.47pF
0.22pF
10uF
100nF
VSSA
15nF
1.2nF
0.47pF
+3.3V
0.22pF
+3.3V
VSS
VDD
100nF
VDDA
10uF
VREFP
A
VIN
VIN
6
DATA<5:0>
D
3)
VREFN
IBIAS
2)
2.4V
2.5nF
1)
1)
0.1nF
30pF
1)
2)
0.4V
1)
1)
2.5nF
FLASH6
1)
0.1nF
30pF
PD
OVL
1)
0.3nF
1)
50pF
30uA
3)
1.4V
100MHz
1)
63pF
STROBE
VSS
1)
50pF
VSSA
1)
0.3nF
SHIELD
CLK
GROUND
Configuration: Continuous Conversion at 100MS/sec
1)
1) The value of the capacitor depends on the input frequency.
For SMD capacitors use the type NPO and for normal capacitors use the type MKT for best performance.
2) The accuracy for both reference voltages must be higher than the resolution of the ADC. In the typical application
both voltages are filtered by a second order low pass filter (fc=5Hz) and buffered with an AD711.
3) The accuracy for the input voltage must be higher than the resolution of the ADC. In the typical application
the input voltage is filtered by a seven order low pass filter (fc=32MHz) and buffered with a THS3001.
Revision B, 07.09.02
Page 8 of 9
Data Sheet : FLASH6 - C35
Contact
Copyright
austriamicrosystems AG
A 8141 Schloss Premstätten, Austria
T. +43 (0) 3136 500 5333
F. +43 (0) 3136 500 5755
[email protected]
Copyright © 2002 austriamicrosystems. Trademarks registered ®.
All rights reserved. The material herein may not be reproduced,
adapted, merged, translated, stored, or used without the prior
written consent of the copyright owner. To the best of its
knowledge, austriamicrosystems asserts that the information
contained in this publication is accurate and correct.
Revision B, 07.09.02
Page 9 of 9