AN407
A Design Guide to I2C F-RAM™ Processor Companions
Author: Harsha Medu
Associated Part Family: FM3164, FM31256, FM31276, FM31278, FM31L276, and FM31L278
Associated Code Examples: CE211423
Related Application Notes: click here
2
AN407 provides an overview of and design guidelines for the I C F-RAM™ real-time clock (RTC) Processor Companion
parts: FM3164, FM31256, FM31276, FM31278, FM31L276, and FM31L278. This document also includes a typical
application, and an example code.
Contents
1
2
3
4
5
6
7
1
Introduction ..................................................................1
Two Logical Devices in One ........................................2
Typical Application.......................................................2
Processor Companion Features ..................................3
4.1 System Power-On Reset with
Pin ...............3
4.2 Early Power-Fail Warning ...................................4
4.3 Event Counters ...................................................4
4.4 Serial Number .....................................................5
Real-Time Clock ..........................................................5
5.1 Backup Power .....................................................6
5.2 RTC Calibration ..................................................6
5.3 Setup Example....................................................6
Summary .....................................................................7
Related Application Notes ...........................................7
8
9
Datasheets .................................................................. 7
PSoC 3-Based Application Code Examples ................ 8
9.1 Enable RTC Oscillator ........................................ 8
9.2 Set RTC Time/Date............................................. 8
9.3 Set VTP Voltage Detect Trip Point ...................... 9
9.4 Read RTC Registers ........................................... 9
9.5 Calibrate RTC ................................................... 10
9.6 Configure Event Counters................................. 10
9.7 Read Event Counters........................................ 11
2
9.8 I C Processor Companion Write ....................... 12
2
9.9 I C Processor Companion Read ....................... 13
Document History............................................................ 14
Worldwide Sales and Design Support ............................. 15
Introduction
The FM31xx F-RAM product families offer F-RAM memory in 256-Kbit and 64-Kbit densities, with an integrated
processor companion and an RTC. The processor companion comprises a power-on system reset, low-voltage
detect, a watchdog timer, an early power-fail warning, two event counters, automatic switchover to backup power,
2
and a lockable 64-bit serial number. It employs an industry-standard I C interface, which is used to access the
memory, the processor companion, and the RTC.
The FM3164 and FM31256 operate over a supply voltage range of 2.7 V to 5.5 V, the FM3127x family over 4.0 V to
5.5 V and the FM31L27x family over 2.7 V to 3.6 V. Table 1 summarizes the product families and their major feature
2
sets. The application note AN405 – Comparison between F-RAM I C Processor Companion Devices describes the
differences between each family.
Table 1. Summary of Part Types and Features
Part No.
Memory
FM3164
64 Kb
FM31256
256 Kb
FM31276
64 Kb
FM31278
256 Kb
FM31L276
64 Kb
FM31L278
256 Kb
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Companion
RTC
Voltage
I2C Speed
Package
2.7 V–5.5 V
1 MHz
SOIC-14
4.0 V–5.5 V
1 MHz
SOIC-14
2.7 V–3.6 V
1 MHz
SOIC-14
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A Design Guide to I2C F- AM™ Processor Companions
2
Two Logical Devices in One
All FM31xx devices are internally organized as two logical devices, as shown in Figure 1: the memory and the
companion/RTC. This helps to integrate both the functionalities without affecting each other. Each has their own
2
address space and is accessed via an I C interface, with each using a unique slave ID: 1010b for the memory and
1101b for the companion/RTC.
Figure 1. Two Logical Devices with Unique Slave IDs
Slave ID
1101b
Slave ID
1010b
Companion
F-RAM
RTC
2
A slave address is required for every transaction in the I C protocol. The 8-bit slave address is composed of a slave
ID, device select bits, and an R/W bit, as shown in Figure 2.
Figure 2. Slave Addresses
Device Select
Slave ID
Memory
1
0
1
0
X
A1
A0
R/W
Comp/RTC
1
1
0
1
X
A1
A0
R/W
7
6
5
4
3
2
1
0
2
The device select bits A1 and A0 are used to allow multiple devices on the I C bus to share the same slave ID for
memory expansion, yet they are individually addressed. Since the FM31xx devices have two address (device select)
2
pins, up to four devices can share the same I C bus. This means that you can add three expansion memory devices
in addition to an FM31xx device.
3
Typical Application
A typical application of FM31xx (Figure 3) shows external components, their typical values, and connections to other
system devices. This application is a line-operated (AC-powered) system with a microcontroller, a FM31278 device,
2
and other passive components. The example microcontroller has a dedicated I C interface. All microcontrollers may
2
not have this port; in such cases, the I C protocol may be implemented in firmware and bit-banged through GPIO
pins.
Note: Bit banging is a technique used for serial communications. It uses firmware instead of a dedicated hardware.
Firmware directly sets and samples the state of pins on the microcontroller, and is responsible for all parameters of
the signal like timing, levels, synchronization and so on.
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A Design Guide to I2C F- AM™ Processor Companions
Figure 3. FM3127x Typical Application Circuit
4
Processor Companion Features
The FM31xx family integrates all the necessary processor supervisor features that a designer may need.
The companion features include:
System power-on reset (POR) with the
o Low-voltage detect (LVD)
o Watchdog
o Manual reset
Early power-fail warning
pin
Event counters
Lockable serial number
The following sections discuss each of these features in detail.
4.1
System Power-On Reset with
Pin
The FM31xx provides a processor-reset signal when the system powers up and whenever a system fault or manual
override (manual hardware reset) occurs. The
pin is primarily used to drive reset to the processor, but can be
used as an input to provide a hardware reset to the system. The
pin does not reset or clear any FM31xx internal
registers.
There are two trigger sources that can drive reset LOW: a low-voltage (LV) detect circuit and the watchdog timer as
shown in Figure 4. At power-up, the
pin is driven LOW as VDD rises toward its nominal operating value. The
point at which
is released is determined by the VTP (voltage trip point), an internal trip voltage that is always
compared to VDD.
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A Design Guide to I2C F- AM™ Processor Companions
Figure 4. Reset Trigger Sources
VDD
~ 150 kΩ
Lockout
LV Detect
+
VDD
VTP
RST
Watchdog
Timer
WDE
An internal pull-up resistor (approximately 150 kΩ) on the
pin eliminates the need for an external resistor. When
tripped, the reset circuit times out after approximately 150 ms (100 ms minimum, 200 ms maximum). You may set VTP
to one of the following values:
FM3164/FM31256 devices: 2.6 V, 2.9 V, 3.9 V or 4.4 V (2 bits, VTP1, VTP0 in register 0Bh)
FM3127x devices: 3.9 V or 4.4 V (VTP in register 0Bh, bit 0)
FM31L27x devices: 2.6 V or 2.9 V (VTP in register 0Bh, bit 0)
The other source of trigger for the
pin is the watchdog timer, a free-running, user-programmable timer that can
be set to time out as soon as 100 ms or as long as 3 seconds. The timer settings and VTP trip voltages are stored in
nonvolatile registers, so there is no need to reinitialize these values. For the watchdog timer to trigger a reset, timer
must expire and the watchdog enable (WDE = 1, register 0Ah, bit 7) bit must be set. The timer may be restarted at
any time within the timeout period by writing 1010b to the Watchdog Restart register (register 09h). To conserve
power, the watchdog counter may be disabled by writing 11111b to the watchdog timeout register.
When a reset condition occurs, the device will set one of two flags to indicate the source of the reset in the register
09h: WTR and POR. These bits are battery-backed during power-down. After power is restored, the system host can
read these bits to determine the cause of the reset. The host must clear these bits with a separate write instruction
after reading them.
Tip During system prototyping and debug, you can clear the WDE bit and still see the watchdog function in action by
reading the WTR flag. A watchdog timer value is set, for example, to 01101b or 1.3 seconds. The cleared WDE bit
2
avoids driving the
pin LOW and locking out the I C interface for a watchdog timer fault, yet you can read the
WTR flag in register 09h to see if the software has a problem.
A manual hardware reset may be provided in the system by simply connecting a momentary contact switch to the
pin. The pin detects an external LOW input condition and responds by driving the signal LOW for 200 ms
(maximum). This effectively filters and debounces a reset switch. Note that in all reset (
) cases, the FM31xx
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internally blocks all I C interface traffic and aborts any pending write accesses to the F-RAM array. A reset (
) that
occurs before all eight data bits and an ACK are received will cause the write to abort. However, write accesses that
have been acknowledged by the F-RAM device will be completed, that is, if a reset occurs after the 9th bit of the data
phase of the write cycle.
4.2
Early Power-Fail Warning
The F-RAM integrated Processor Companion features a general-purpose comparator that can be used to generate
an early power-fail interrupt (PFI). This warning signal can drive a microcontroller interrupt input and must occur
before VDD drops too low to save all critical data to the nonvolatile RAM. he Processor Companion’s early power-fail
interrupt can also be used as a warning to the system to stop conducting critical activity during a brownout condition.
For more information, refer to the application note AN400 - Generating a Power-Fail Interrupt using the F-RAM
Processor Companion.
4.3
Event Counters
The FM31xx devices integrate two 16-bit event counters for tamper-detect or other event logging purposes. Each
counter has an input pin each for the two counters (CNT1 and CNT2), that are edge-triggered and a polarity that is
user-defined. The event, or edge, must be a CMOS logic level. The event counter control register and counter values
are battery backed.
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A Design Guide to I2C F- AM™ Processor Companions
Figure 3 shows a normally open and a normally closed switch, each connected to ground (or a system case or
chassis). The normally open switch is preferred if you do not want extra current pulled from the backup power source.
If the system is powered up (VDD) most of the time, an extra few microamperes may not be a problem. On the other
hand, an extra few microamperes could reduce the total backup time slightly if you are using a capacitor as your
backup source.
At the first power-up with no backup source, the event counters are cleared to all zeroes.
Note: Neither CNT1 nor CNT2 has internal pull-up or pull-down resistors, so they should not be left floating.
4.4
Serial Number
The F-RAM processor companion provides a 64-bit lockable serial number (register 11h to register 18h in Table 2).
The serial number provides a unique way of identifying each product. The serial number has unlimited writes until the
lock-bit is set by the user.
5
Real-Time Clock
A real-time clock (RTC) counts time in steps of seconds and can report time, day of the week, calendar day, week,
and year. It can be programmed to record time when certain system events occur. The RTC consists of an oscillator
and counters that derive the time/calendar information, and several registers that hold the time and RTC control
settings. The RTC will run continuously even if the main power fails as long as a 3-V backup power source is
connected to the VBAK input pin. A backup source can be either a 3-V battery or a super capacitor (see the super
capacitor trickle charge discussion in the Backup Power section).
The default factory settings disable the RTC oscillator. To start and configure the RTC, the
C
bit (register 01h,
bit 7) must first be set to 0. Then, the clock and calendar registers must be written to reflect the current time, day, and
date. The RTC register map is shown in Table 2.
Table 2. RTC Register Map
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The 32.768-kHz oscillator is divided down through a series of counters. The first counter divides it by 32,768 to derive
the 1-Hz signal for the second counter. The next counter uses seconds to drive a signal once per minute to the
minute counter. Subsequent counters continue to divide down until there is one pulse per hour, month, and year
driving their respective counters. The counters hold time and date information that is memory mapped (locations 02h
through 08h) into the RTC address space. Because the FM31xx uses a different device ID for the companion register
space, they do not appear as F-RAM locations. You may read and write the time and date by reading and writing
these locations without affecting the F-RAM locations. The CAL/PFO pin shown in Figure 3 is used to measure the
512-Hz frequency in the calibration mode. This information can be used to correct any offset in the RTC time due to
crystal or temperature drift.
In the FM31xx, the RTC data may be read without interrupting the RTC operation. When the RTC is read by writing a
‘1’ to the ‘R’ bit, a snapshot is taken of the current time-day-date and stored in registers where it can be read by the
host. The snapshot ensures that the time doesn’t change between successive reads from the host. Similarly, during
RTC writes, the registers hold the data written by the host and wait to transfer it to the RTC counters after all the timeday-date information has been written and the ‘W’ bit is cleared. If W = 0, writes to the RTC registers are ignored. For
more information on RTC read and write, see Setup Example.
5.1
Backup Power
The RTC, Event Counter, and various control settings are maintained by using a backup source on the VBAK pin even
if the primary power source is removed. The VBAK source may be a battery or a large-value super capacitor. For more
information, refer to AN404 - F-RAM RTC Backup Supply (VBAK pin) and UL Compliance.
When using a super capacitor as the backup source, the capacitor can discharge over a long period of time to a point
where the VBAK voltage drops out of spec and the RTC stops functioning, resulting in the loss of backup data. To
avoid this situation, the charge on the capacitor needs to be restored. For different types of charging, refer to AN401 Charging Methods for the F-RAM RTC Backup Capacitor.
5.2
RTC Calibration
RTC calibration is required primarily to compensate for the frequency shift due to crystal tolerance, temperate effect,
and load capacitance mismatch. A 512-Hz signal brought out on the CAL/PFO pin is used for calibration purposes.
For more information about calibration, refer to AN402 - F-RAM RTC Oscillator Design Guide.
5.3
Setup Example
The following example is a setup procedure that describes the proper sequence for the power-up, initialization, and
register settings.
1.
Apply VDD power.
2.
Apply battery to VBAK. If a super capacitor is used, you can set the trickle charger (VBC = 1) and optionally the
Fast Charge (FC) bit. If a battery is used, ensure that VBC = 0.
3.
Set the VDD voltage trip point bit, VTP, if you prefer a setting higher than the default setting.
4.
Enable the RTC oscillator (set
5.
Enter the RTC calibration mode (CAL = 1).
6.
Determine the RTC clock error and sign by monitoring the 512-Hz output (CAL/PFO pin). Use a frequency
counter.
7.
Write the error correction value to CALS and CAL (4:0). See the calibration adjustments table in the datasheet.
8.
Exit the calibration mode (CAL = 0).
9.
Set the Write bit (W bit) to enable writing the time-day-date values to the RTC.
C
= 0).
10. Write the time-day-date values to registers 02h–08h.
11. Clear the W bit to start the RTC with new values.
12. Resume Normal operation.
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A Design Guide to I2C F- AM™ Processor Companions
To read the RTC, follow this simple three-step procedure:
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1.
Set the Read bit (R bit), which takes a snapshot of the RTC registers (assumes R is previously at logic 0).
2.
Issue the Read Processor Companion command (slave ID 1101b), starting at address 02h, and read seven RTC
bytes (02h–08h).
3.
Clear the R bit to prepare for the next RTC read.
Summary
This application note summarizes the features of the FM31xx family of devices. This document also provides a typical
application, design guidelines, and example pseudo codes for the FM31xx devices.
7
8
Related Application Notes
AN400 - Generating a Power-Fail Interrupt using the F-RAM Processor Companion
AN401 - Charging Methods for the F-RAM RTC Backup Capacitor
AN402 - F-RAM RTC Oscillator Design Guide
AN404 - F-RAM RTC Backup Supply (VBAK pin) and UL Compliance
AN408 - A Design Guide to SPI F-RAM Processor Companion - FM33256B
Datasheets
FM3164/FM31256: 64-Kbit/256-Kbit Integrated Processor Companion with F-RAM
FM31276/FM31278: 64-Kbit/256-Kbit Integrated Processor Companion with F-RAM
FM31L276/FM31L278: 64-Kbit/256-Kbit Integrated Processor Companion with F-RAM
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9
PSoC 3-Based Application Code Examples
9.1
Enable RTC Oscillator
/************************** Enable RTC Oscillator
*******************************/
data[0] = 0x00;
// Data for clearing the
bit
WRITE_RTC (0xD0,
// 0xD0 is the command for a write to the Companion/RTC
0x01,
// Sets the address pointer to Register 01h
data, // Writes data 0x00 which clears the
bit
0x01); // Number of bytes to be written
9.2
Set RTC Time/Date
/************************** Set RTC time/date *******************************/
// Step #1 Set W bit which allows writes to RTC registers
data[0] = 0x02;
// Data for setting the W bit
WRITE_RTC (0xD0,
// 0xD0 is the command for a write to the Companion/RTC
0x00,
// Sets the address pointer to Register 00h
data, // Writes data 0x02 which sets the W bit
0x01); // Number of bytes to be written
// Step
data[0]
data[1]
data[2]
data[3]
data[4]
data[5]
data[6]
#2 Write time/date to RTC Registers
= 0x00;
// Seconds set to 00
= 0x10;
// Minutes set to 10
= 0x14;
// Hours set to 14 (2 PM)
= 0x03;
// Day set to the third day of the week
= 0x04;
// Date set to the fourth day in March
= 0x03;
// Month set to March
= 0x08;
// Year set to 2008
WRITE_RTC (0xD0,
0x02,
data,
0x07);
// 0xD0 is the command for a write to the Companion/RTC
// Sets the address pointer to Register 02h
// Writes time/date
// Number of bytes to be written
// RTC does not start to run yet.
// Step #3 Clear W bit to start RTC with the exact time
data[0] = 0x00;
// data=0x00 clears the W bit
WRITE_RTC (0xD0,
0x00,
data,
defined
// 0xD0 is the command for a write to the Companion
// Sets the address pointer to Register 00h
// Data=0x00 clears the W bit to start RTC with time
// in Step #2. The 8th clock of data byte defines the
actual
0x01);
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// start of the RTC.
// Number of bytes to be written
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9.3
Set VTP Voltage Detect Trip Point
/********************* Set VTP Voltage Detect Trip Point
**************************/
// From the factory, VTP bit is cleared to 0. If user wants to set trip point
to
// the higher setting, then write VTP bit to 1 in Reg 0Bh control register.
data[0] = 0x01;
// Data for setting VTP bit
WRITE_RTC (0xD0,
// 0xD0 is the command for a write to the Companion/RTC
0x0B,
// Sets the address pointer to Register 0Bh
data, // Writes data 0x01 which sets the VTP bit
0x01); // Number of bytes to be written
9.4
Read RTC Registers
/************************** Read RTC Registers *******************************/
// Step #1 Set R bit which takes snapshot of RTC registers
data[0] = 0x01;
// Data for setting the R bit
WRITE_RTC (0xD0,
// 0xD0 is the command for a write to the Companion/RTC
0x00,
// Sets the address pointer to Register 00h
data, // Writes data 0x01 which sets the R bit
0x01); // Number of bytes to be written
// Step #2 Read RTC Registers
READ_RTC (0xD0,
// 0xD0 is the command for a write to the Companion/RTC
0x02,
// Sets the address pointer to Register 02h
data,
// Data buffer to read RTC registers
0x07);
// Number of bytes to be read
//
//
//
//
//
//
//
//
data
0x59
0x15
0x14
0x03
0x04
0x03
0x08
buffer contains the following
– Seconds
– Minute
– Hour
– Third day of the week
- Fourth day in March
- March
- 2008
// Step #3 Clear R bit
data[0] = 0x00;
WRITE_RTC (0xD0,
0x00,
data,
0x01);
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// data=0x00 clears the W bit
//
//
//
//
0xD0 is the command for a write to the Companion
Sets the address pointer to Register 00h
Data=0x00 clears the R bit to allow RTC read next time
Number of bytes to be written
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9.5
Calibrate RTC
/************************** Calibrate RTC *******************************/
// Step #1 Set CAL bit which turns on the 512Hz sq wave on the CAL/PFO pin.
Setting
// the CAL bit also allows writes to NV bits in Reg 01h CAL/Control register.
data[0] = 0x04;
// Data for setting the CAL bit
WRITE_RTC (0xD0,
// 0xD0 is the command for a write to the Companion/RTC
0x00,
// Sets the address pointer to Register 00h
data, // Writes data 0x04 which sets the CAL bit
0x01); // Number of bytes to be written
// Step #2 Use a freq counter to accurately measure the 512Hz, use lookup table
in
// datasheet to find to that matches your freq measurement, write cal code to
Reg 01h
data[0] = 0x2C;
// Data=0x2C for 511.9722Hz and 511.9744Hz
WRITE_RTC (0xD0,
0x01,
data,
0x01);
// 0xD0 is the command for a write to the Companion/RTC
// Sets the address pointer to Register 01h
// Writes calibration value 0x2C
// Number of bytes to be written
// Step #3 Clear CAL bit to exit cal mode and turn off 512Hz
data[0] = 0x00;
// data=0x00 clears the CAL bit
WRITE_RTC (0xD0,
0x00,
data,
0x01);
9.6
//
//
//
//
0xD0 is the command for a write to the Companion
Sets the address pointer to Register 00h
Data=0x00 clears the CAL bit
Number of bytes to be written
Configure Event Counters
/************************** Configure Event Counters
*******************************/
// Configure polarity bits for rising edge detection on Counter1 and falling
edge
// detection on Counter2
data[0] = 0x01;
// Data for setting C2P to 0, C1P to 1
WRITE_RTC (0xD0,
// 0xD0 is the command for a write to the Companion/RTC
0x0C,
// Sets the address pointer to Register 0Ch
data, // Writes data 0x01 to set C2P to 0, C1P to 1
0x01); // Number of bytes to be written
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A Design Guide to I2C F- AM™ Processor Companions
9.7
Read Event Counters
/************************** Read Event Counters
*******************************/
// Step #1 Set RC bit which takes snapshot of both counter registers
data[0] = 0x09;
// Data for setting the RC bit and keeps C1P=1
WRITE_RTC (0xD0,
// 0xD0 is the command for a write to the Companion/RTC
0x0C,
// Sets the address pointer to Register 0Ch
data, // Writes data 0x09 which sets the R bit
0x01); // Number of bytes to be written
// Step #2 Read Event Counters
READ_RTC (0xD0,
// 0xD0 is the command for a write to the Companion/RTC
0x0D,
// Sets the address pointer to Register 0Dh
data,
// Data buffer to read RTC registers
0x04);
// Number of bytes to be read
//
//
//
//
//
data
0x1A
0x00
0x31
0x02
buffer contains the following
– Counter1 reads out LSB 0x1A (decimal 26)
– Counter1 reads out MSB 0x00
– Counter2 reads out LSB 0x31 (decimal 49)
– Counter2 reads out MSB 0x02
// Step #3 Clear RC bit
data[0] = 0x01;
WRITE_RTC (0xD0,
0x0C,
data,
0x01);
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//
//
//
//
// data=0x01 clears the RC bit
0xD0 is the command for a write to the Companion
Sets the address pointer to Register 0Ch
Data=0x01 clears the RC bit and keeps C1P=1
Number of bytes to be written
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9.8
I2C Processor Companion Write
/*****************PSoC3 Based Pseudo Code for I2C Processor Companion
Write**************/
uint8 WRITE_RTC (uint8 slave_id, uint8 addr, uint8 *data_write_ptr, uint8
total_data_count )
{
uint32 i;
uint8 error_status;
// I2C Start Condition
error_status = nvRAM_I2C_1_I2C_MasterSendStart(slave_id, 0);
if( error_status != nvRAM_I2C_1_I2C_MSTR_NO_ERROR )
{
nvRAM_I2C_1_I2C_MasterSendStop();
return error_status;
}
// Send F-RAM Processor Companion Register Address
error_status = nvRAM_I2C_1_I2C_MasterWriteByte((uint8)(addr));
if( error_status != nvRAM_I2C_1_I2C_MSTR_NO_ERROR )
{
nvRAM_I2C_1_I2C_MasterSendStop();
return error_status;
}
// Send F-RAM Processor Companion Register Data Bytes
for(i = 0; i < total_data_count; i++ )
{
error_status =
nvRAM_I2C_1_I2C_MasterWriteByte((uint8)(data_write_ptr[i]));
if( error_status != nvRAM_I2C_1_I2C_MSTR_NO_ERROR)
{
nvRAM_I2C_1_I2C_MasterSendStop();
return error_status;
}
}
// I2C Stop Condition
nvRAM_I2C_1_I2C_MasterSendStop();
return error_status;
}
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9.9
I2C Processor Companion Read
/*****************PSoC3 Based Pseudo Code for I2C Processor Companion
Read***************/
uint8 READ_RTC (uint8 slave_id, uint8 addr, uint8 *data_read_ptr, uint8
total_data_count)
{
uint32 i;
uint8 error_status;
// I2C Start Condition
error_status = nvRAM_I2C_1_I2C_MasterSendStart(slave_id, 0);
if( error_status != nvRAM_I2C_1_I2C_MSTR_NO_ERROR )
{
nvRAM_I2C_1_I2C_MasterSendStop();
return error_status;
}
// Send F-RAM Processor Companion Register Address
error_status = nvRAM_I2C_1_I2C_MasterWriteByte((uint8)(addr));
if( error_status != nvRAM_I2C_1_I2C_MSTR_NO_ERROR )
{
nvRAM_I2C_1_I2C_MasterSendStop();
return error_status;
}
// I2C Restart Condition
error_status = nvRAM_I2C_1_I2C_MasterSendRestart(slave_id, 1);
if( error_status != nvRAM_I2C_1_I2C_MSTR_NO_ERROR )
{
nvRAM_I2C_1_I2C_MasterSendStop();
return error_status;
}
// Read F-RAM Processor Companion Register Data Bytes
for(i = 0; i < total_data_count - 1; i++ )
{
data_read_ptr[i] = nvRAM_I2C_1_I2C_MasterReadByte(1);
}
// Read is stopped by NACKing the last byte
data_read_ptr[i] = nvRAM_I2C_1_I2C_MasterReadByte(0);
// I2C Stop Condition
nvRAM_I2C_1_I2C_MasterSendStop();
return error_status;
}
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Document No. 001-87421 Rev. *B
13
A Design Guide to I2C F- AM™ Processor Companions
Document History
2
Document Title: AN407 - A Design Guide to I C F-RAM™ Processor Companions
Document Number: 001-87421
Revision
ECN
Orig. of
Change
Submission
Date
Description of Change
**
4039506
MEDU
06/25/2013
New Spec.
*A
4573031
MEDU
11/27/2014
Updated Document itle to read as “A Design Guide to I2C F- AM™ Processor
Companions – AN407”.
Updated Associated Project as “Yes” in page 1.
Updated Associated Part Family as “FM3164, FM31256, FM31276, FM31278,
FM31L276, and FM31L278” in page 1.
Updated Abstract:
Updated description.
Updated Introduction:
enamed “ verview” as “Introduction” in heading.
Updated description and Table 1.
Updated Two Logical Devices in One:
Updated description and Figure 1.
Updated Typical Application:
Updated description.
Updated Processor Companion Features:
Updated description.
Updated Real-Time Clock:
Updated description.
Updated Backup Power:
Updated description.
emoved “Calculating Capacitor Backup Time”.
Added RTC Calibration.
Updated Setup Example:
Updated description.
Added Related Application Notes.
Added Datasheets.
emoved “Pseudo Code Examples”.
Added PSoC 3-Based Application Code Examples.
Added PSoC 3 based user module project as attachment.
*B
5293268
MEDU
06/02/2016
Added a reference to code example CE211423
Updated template
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Document No. 001-87421 Rev. *B
14
A Design Guide to I2C F- AM™ Processor Companions
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Document No. 001-87421 Rev. *B
15