74LVC4245A Octal dual supply translating transceiver; 3-state Rev. 06 — 18 January 2008 Product data sheet 1. General description The 74LVC4245A is an octal dual supply translating transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. It is designed to interface between a 3 V and 5 V bus in a mixed 3 V and 5 V supply environment. The device features an output enable input (pin OE) for easy cascading and a send/receive input (pin DIR) for direction control. Pin OE controls the outputs so that the buses are effectively isolated. In suspend mode, when VCCA is zero, there will be no current flow from one supply to the other supply. The A-outputs must be set 3-state and the voltage on the A-bus must be smaller than Vdiode (typical 0.7 V). VCCA ≥ VCCB, except in suspend mode. 2. Features n 5 V tolerant inputs/outputs, for interfacing with 5 V logic n Wide supply voltage range: u 3 V port (VCCB): 1.5 V to 3.6 V u 5 V port (VCCA): 1.5 V to 5.5 V n CMOS low-power consumption n Direct interface with TTL levels n Inputs accept voltages up to 5.5 V n High-impedance when VCC = 0 V n Complies with JEDEC standard no. JESD8B/JESD36 n ESD protection: u HBM JESD22-A114E exceeds 2000 V u MM JESD22-A115-A exceeds 200 V n Multiple package options n Specified from −40 °C to +85 °C and −40 °C to +125 °C 74LVC4245A NXP Semiconductors Octal dual supply translating transceiver; 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC4245AD −40 °C to +125 °C SO24 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 74LVC4245ADB −40 °C to +125 °C SSOP24 plastic shrink small outline package; 24 leads; body width 5.3 mm SOT340-1 74LVC4245APW −40 °C to +125 °C TSSOP24 plastic thin shrink small outline package; 24 leads; SOT355-1 body width 4.4 mm 74LVC4245ABQ −40 °C to +125 °C DHVQFN24 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 24 terminals; body 3.5 × 5.5 × 0.85 mm SOT815-1 4. Functional diagram 2 DIR OE 3 B0 4 22 2 B1 5 1 6 3 20 B3 5 19 6 18 7 17 8 16 9 15 10 14 7 IEC Logic symbol B7 14 mna453 Fig 2. Logic diagram 74LVC4245A_6 Product data sheet 15 A7 mna452 Fig 1. 16 A6 B6 10 17 A5 B5 9 18 A4 B4 8 19 A3 21 4 20 A2 B2 2 21 A1 G3 3EN1 3EN2 22 A0 © NXP B.V. 2008. All rights reserved. Rev. 06 — 18 January 2008 2 of 17 74LVC4245A NXP Semiconductors Octal dual supply translating transceiver; 3-state 5. Pinning information 5.1 Pinning terminal 1 index area 1 74LVC4245A 24 VCCB VCCA 74LVC4245A DIR 2 VCCA 1 24 VCCB A0 3 23 VCCB 22 OE DIR 2 23 VCCB A1 4 21 B0 A0 3 22 OE A2 5 20 B1 A1 4 21 B0 A3 6 19 B2 A2 5 20 B1 A4 7 18 B3 A3 6 19 B2 A5 8 17 B4 A4 7 18 B3 A6 9 A5 8 17 B4 A7 10 A6 9 16 B5 GND 11 A7 10 15 B6 GND 11 14 B7 GND 12 13 GND 16 B5 GND(1) 15 B6 GND 13 GND 12 14 B7 001aah087 Transparent top view 001aaa349 (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 3. Pin configuration SO24 and (T)SSOP24 Fig 4. Pin configuration DHVQFN24 5.2 Pin description Table 2. Pin description Symbol Pin Description VCCA 1 supply voltage (5 V bus) VCCB 23, 24 supply voltage (3 V bus) GND 11, 12, 13 ground (0 V) DIR 2 direction control A[0:7] 3, 4, 5, 6, 7, 8, 9, 10 data input or output B[0:7] 21, 20, 19, 18, 17, 16, 15, 14 data input or output OE 22 output enable input (active LOW) 74LVC4245A_6 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 06 — 18 January 2008 3 of 17 74LVC4245A NXP Semiconductors Octal dual supply translating transceiver; 3-state 6. Functional description Table 3. Functional table[1] Input Input/output OE DIR An Bn L L A=B input L H input B=A H X Z Z [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCCA supply voltage 5 V port VCCB supply voltage 3 V port IIK input clamping current VI input voltage IOK output clamping current output voltage VO Conditions VI < 0 V [1] Min Max Unit −0.5 +6.5 V −0.5 +4.6 V −50 - mA −0.5 +6.5 V - ±50 mA output HIGH or LOW state [1] −0.5 VCC + 0.5 V output 3-state [1] −0.5 +6.5 V - ±50 mA mA VO > VCC or VO < 0 V IO output current VO = 0 V to VCC ICC supply current - 100 IGND ground current −100 - mA Tstg storage temperature −65 +150 °C Ptot power dissipation - 500 mW Tamb = −40 °C to +125 °C [2] [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For SO24 packages: above 70 °C the value of Ptot derates linearly with 8 mW/K. For (T)SSOP24 packages: above 60 °C the value of Ptot derates linearly with 5.5 mW/K. For DHVQFN24 packages: above 60 °C the value of Ptot derates linearly with 4.5 mW/K. 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit VCCA supply voltage 5 V port (for maximum speed performance) VCCA ≥ VCCB; see Figure 5 1.5 - 5.5 V VCCB supply voltage 3 V port (for low-voltage VCCA ≥ VCCB; see Figure 5 applications) 1.5 - 3.6 V VI input voltage for control inputs 0 - 5.5 V VO output voltage output HIGH or LOW state 0 - VCC V output 3-state 0 - 5.5 V −40 - +125 °C Tamb ambient temperature 74LVC4245A_6 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 06 — 18 January 2008 4 of 17 74LVC4245A NXP Semiconductors Octal dual supply translating transceiver; 3-state Table 5. Recommended operating conditions …continued Symbol Parameter Conditions Min Typ Max Unit ∆t/∆V input transition rise and fall rate VCCB = 2.7 V to 3.0 V - - 20 ns/V VCCB = 3.0 V to 3.6 V - - 10 ns/V VCCA = 3.0 V to 4.5 V - - 20 ns/V VCCA = 4.5 V to 5.5 V - - 10 ns/V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ[1] Max Unit - - V Tamb = −40 °C to +85 °C VIH HIGH-level input voltage VCCB = 2.7 V to 3.6 V 2.0 VCCA = 4.5 V to 5.5 V 2.0 - - V VIL LOW-level input voltage VCCB = 2.7 V to 3.6 V - - 0.8 V VCCA = 4.5 V to 5.5 V - - 0.8 V VOH VOL HIGH-level output voltage VI = VIH or VIL LOW-level output voltage VCCB = 2.7 V to 3.6 V; IO = −100 µA VCCB − 0.2 VCCB - V VCCB = 2.7 V; IO = −12 mA VCCB − 0.5 - - V VCCB = 3.0 V; IO = −24 mA VCCB − 0.8 - - V VCCA = 4.5 V to 5.5 V; IO = −100 µA VCCA − 0.2 VCCA - V VCCA = 4.5 V; IO = −12 mA VCCA − 0.5 - - V VCCA = 4.5 V; IO = −24 mA VCCA − 0.8 - - V VCCB = 2.7 V to 3.6 V; IO = 100 µA - - 0.20 V VI = VIH or VIL VCCB = 2.7 V; IO = 12 mA - - 0.40 V VCCB = 3.0 V; IO = 24 mA - - 0.55 V VCCA = 4.5 V to 5.5 V; IO = 100 µA - - 0.20 V VCCA = 4.5 V; IO = 12 mA - - 0.40 V VCCA = 4.5 V; IO = 24 mA - - 0.55 V - ±0.1 ±5 µA VCCB = 3.6 V; VO = VCCB or GND - ±0.1 ±5 µA VCCA = 5.5 V; VO = VCCA or GND - ±0.1 ±5 µA VCCB = 3.6 V; other inputs at VCCB or GND - 0.1 10 µA VCCA = 5.5 V; other inputs at VCCA or GND - 0.1 10 µA II input leakage current VI = 5.5 V or GND IOZ OFF-state output current VI = VIH or VIL ICC supply current IO = 0 A 74LVC4245A_6 Product data sheet [2] © NXP B.V. 2008. All rights reserved. Rev. 06 — 18 January 2008 5 of 17 74LVC4245A NXP Semiconductors Octal dual supply translating transceiver; 3-state Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol ∆ICC Parameter additional supply current CI input capacitance CI/O input/output capacitance Min Typ[1] Max Unit VCCB = 2.7 V to 3.6 V; VI = VCCB − 0.6 V; other inputs at VCCB or GND - 5 500 µA VCCA = 4.5 V to 5.5 V; VI = VCCA − 0.6 V; other inputs at VCCA or GND - 5 500 µA - 4.0 - pF An and Bn - 5.0 - pF VCCB = 2.7 V to 3.6 V 2.0 - - V VCCA = 4.5 V to 5.5 V 2.0 - - V VCCB = 2.7 V to 3.6 V - - 0.8 V VCCA = 4.5 V to 5.5 V - - 0.8 V VCCB = 2.7 V to 3.6 V; IO = −100 µA VCCB − 0.3 - - V VCCB = 2.7 V; IO = −12 mA VCCB − 0.65 - - V VCCB = 3.0 V; IO = −24 mA VCCB − 1.0 - - V VCCA = 4.5 V to 5.5 V; IO = −100 µA VCCA − 0.3 - - V VCCA = 4.5 V; IO = −12 mA VCCA − 0.65 - - V VCCA = 4.5 V; IO = −24 mA VCCA − 1.0 - - V VCCB = 2.7 V to 3.6 V; IO = 100 µA - - 0.30 V VCCB = 2.7 V; IO = 12 mA - - 0.60 V VCCB = 3.0 V; IO = 24 mA - - 0.80 V VCCA = 4.5 V to 5.5 V; IO = 100 µA - - 0.30 V VCCA = 4.5 V; IO = 12 mA - - 0.60 V VCCA = 4.5 V; IO = 24 mA - - 0.80 V - - ±20 µA VCCB = 3.6 V; VO = VCCB or GND - - ±20 µA VCCA = 5.5 V; VO = VCCA or GND - - ±20 µA VCCB = 3.6 V; other inputs at VCCB or GND - - 40 µA VCCA = 5.5 V; other inputs at VCCA or GND - - 40 µA Conditions per control pin; IO = 0 A [3] Tamb = −40 °C to +125 °C VIH VIL VOH VOL II IOZ ICC HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VI = VIH or VIL LOW-level output voltage input leakage current OFF-state output current supply current VI = VIH or VIL VI = 5.5 V or GND VI = VIH or VIL IO = 0 A 74LVC4245A_6 Product data sheet [2] © NXP B.V. 2008. All rights reserved. Rev. 06 — 18 January 2008 6 of 17 74LVC4245A NXP Semiconductors Octal dual supply translating transceiver; 3-state Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol ∆ICC Parameter Min Typ[1] Max Unit VCCB = 2.7 V to 3.6 V; VI = VCCB − 0.6 V; other inputs at VCCB or GND - - 5000 µA VCCA = 4.5 V to 5.5 V; VI = VCCA − 0.6 V; other inputs at VCCA or GND - - 5000 µA Conditions additional supply current [3] per control pin; IO = 0 A [1] All typical values are measured at VCCA = 5.0 V, VCCB = 3.3 V and Tamb = 25 °C. [2] For transceivers, the parameter IOZ includes the input leakage current. [3] VCCB = 2.7 V to 3.6 V: other inputs at VCCB or GND. VCCA = 4.5 V to 5.5 V: other inputs at VCCA or GND. 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). VCCA = 4.5 V to 5.5 V; tr = tf ≤ 2.5 ns. For test circuit see Figure 8. Symbol Parameter Conditions −40 °C to +85 °C VCCB Min tPHL tPLH tPZL tPZH tPLZ tPHZ HIGH to LOW propagation delay LOW to HIGH propagation delay OFF-state to LOW propagation delay OFF-state to HIGH propagation delay LOW to OFF-state propagation delay HIGH to OFF-state propagation delay Max −40 °C to +125 °C Unit Min Max An to Bn; see Figure 6 2.7 V 3.0 V to 3.6 V 1.0 3.3 6.3 1.0 8.0 ns Bn to An; see Figure 6 2.7 V 1.0 3.4 6.1 1.0 8.0 ns 3.0 V to 3.6 V 1.0 3.4 6.1 1.0 8.0 ns An to Bn; see Figure 6 2.7 V 1.0 3.3 6.7 1.0 8.5 ns 3.0 V to 3.6 V 1.0 2.8 6.5 1.0 8.5 ns Bn to An; see Figure 6 2.7 V 1.0 3.0 5.0 1.0 6.5 ns 3.0 V to 3.6 V 1.0 3.0 5.0 1.0 6.5 ns OE to An; see Figure 7 2.7 V 1.0 4.5 9.0 1.0 11.5 ns 3.0 V to 3.6 V 1.0 4.5 9.0 1.0 11.5 ns OE to Bn; see Figure 7 2.7 V 1.0 4.4 8.7 1.0 11.0 ns 3.0 V to 3.6 V 1.0 3.8 8.1 1.0 10.5 ns OE to An; see Figure 7 2.7 V 1.0 4.5 8.1 1.0 10.5 ns 3.0 V to 3.6 V 1.0 4.5 8.1 1.0 10.5 ns OE to Bn; see Figure 7 2.7 V 1.0 4.3 8.7 1.0 11.0 ns 3.0 V to 3.6 V 1.0 3.2 8.1 1.0 10.5 ns OE to An; see Figure 7 2.7 V 1.0 2.9 7.0 1.0 9.0 ns 3.0 V to 3.6 V 1.0 2.9 7.0 1.0 9.0 ns OE to Bn; see Figure 7 2.7 V 1.0 3.9 7.7 1.0 10.0 ns 3.0 V to 3.6 V 1.0 3.5 7.7 1.0 10.0 ns OE to An; see Figure 7 2.7 V 1.0 2.8 5.8 1.0 7.5 ns 3.0 V to 3.6 V 1.0 2.8 5.8 1.0 7.5 ns OE to Bn; see Figure 7 2.7 V 1.0 3.3 7.8 1.0 10.0 ns 3.0 V to 3.6 V 1.0 2.9 7.8 1.0 10.0 ns 1.0 74LVC4245A_6 Product data sheet Typ[1] 3.6 6.3 1.0 8.0 ns © NXP B.V. 2008. All rights reserved. Rev. 06 — 18 January 2008 7 of 17 74LVC4245A NXP Semiconductors Octal dual supply translating transceiver; 3-state Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V). VCCA = 4.5 V to 5.5 V; tr = tf ≤ 2.5 ns. For test circuit see Figure 8. Symbol Parameter tsk(o) output skew time CPD power dissipation capacitance Conditions −40 °C to +85 °C VCCB −40 °C to +125 °C Unit Min Typ[1] Max Min Max - - 1.0 - 1.5 ns [2] [3] 5 V port: Bn to An; VI = GND to VCCA; VCCA = 5.0 V outputs enabled - - 17 - - - pF outputs disabled - - 5 - - - pF [3] 3 V port: An to Bn; VI = GND to VCCB; VCCB = 3.3 V outputs enabled - - 17 - - - pF outputs disabled - - 5 - - - pF [1] Typical values are measured at Tamb = 25 °C, VCCA = 5.0 V, and VCCB = 2.7 V and 3.3 V respectively. [2] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. [3] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in Volts N = number of inputs switching Σ(CL × VCC2 × fo) = sum of the outputs 11. AC waveforms 3.9 VCCB (V) 3.6 mna454 VCCA ≥ VCCB 3.3 3.0 2.7 2.4 2.1 1.8 1.5 1.2 0.9 1.5 2.1 2.7 Full operation Fig 5. 3.3 3.9 4.5 5.1 5.7 VCCA (V) Complies with TTL levels Supply operation area 74LVC4245A_6 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 06 — 18 January 2008 8 of 17 74LVC4245A NXP Semiconductors Octal dual supply translating transceiver; 3-state VI An, Bn input VM GND t PHL t PLH VOH Bn, An output VM VOL mna366 VM = 1.5 V at 2.7 V ≤ VCCB ≤ 3.6 V; VM = 0.5VCCA at VCCA ≥ 4.5 V. VOL and VOH are typical output voltage drops that occur with the output load. Fig 6. Input (An, Bn) to output (Bn, An) propagation delays VI OE input VM GND t PLZ t PZL VCC output LOW-to-OFF OFF-to-LOW VM VX VOL t PHZ VOH t PZH VY output HIGH-to-OFF OFF-to-HIGH VM GND outputs enabled outputs disabled outputs enabled mna367 VM = 1.5 V at 2.7 V ≤ VCCB ≤ 3.6 V; VM = 0.5VCCA at VCCA ≥ 4.5 V. VX = VOL + 0.3 V at VCCB ≥ 2.7 V; VY = VOH − 0.3 V at VCCB ≥ 2.7 V. VOL and VOH are typical output voltage drops that occur with the output load. Fig 7. 3-state enable and disable times 74LVC4245A_6 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 06 — 18 January 2008 9 of 17 74LVC4245A NXP Semiconductors Octal dual supply translating transceiver; 3-state VEXT VCC VI RL VO G DUT RT CL RL mna616 Test data is given in Table 8. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. Fig 8. Table 8. Load circuitry for switching times Test data Supply voltage Input Load VEXT VCCA VCCB VI [1] CL RL tPLH, tPHL tPZH, tPHZ tPZL, tPLZ [2] < 2.7 V < 2.7 V VCCI 50 pF 500 Ω open GND 2 × VCCO - 2.7 V to 3.6 V 2.7 V 50 pF 500 Ω open GND 2 × VCCO 4.5 V to 5.5 V - 3.0 V 50 pF 500 Ω open GND 2 × VCCO [1] VCCI is the supply voltage associated with the data input port. [2] VCCO is the supply voltage associated with the output port. 74LVC4245A_6 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 06 — 18 January 2008 10 of 17 74LVC4245A NXP Semiconductors Octal dual supply translating transceiver; 3-state 12. Package outline SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 D E A X c HE y v M A Z 24 13 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 12 e detail X w M bp 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 15.6 15.2 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.01 0.019 0.013 0.014 0.009 0.61 0.60 0.30 0.29 0.05 0.419 0.043 0.055 0.394 0.016 inches 0.1 0.012 0.096 0.004 0.089 0.043 0.039 0.01 0.01 Z (1) 0.9 0.4 0.035 0.004 0.016 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. Fig 9. REFERENCES OUTLINE VERSION IEC JEDEC SOT137-1 075E05 MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Package outline SOT137-1 (SO24) 74LVC4245A_6 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 06 — 18 January 2008 11 of 17 74LVC4245A NXP Semiconductors Octal dual supply translating transceiver; 3-state SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm D SOT340-1 E A X c HE y v M A Z 24 13 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 12 bp e detail X w M 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 8.4 8.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 0.8 0.4 8 o 0 o Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION SOT340-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 Fig 10. Package outline SOT340-1 (SSOP24) 74LVC4245A_6 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 06 — 18 January 2008 12 of 17 74LVC4245A NXP Semiconductors Octal dual supply translating transceiver; 3-state TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm D SOT355-1 E A X c HE y v M A Z 13 24 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 12 bp e detail X w M 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 7.9 7.7 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.5 0.2 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT355-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 Fig 11. Package outline SOT355-1 (TSSOP24) 74LVC4245A_6 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 06 — 18 January 2008 13 of 17 74LVC4245A NXP Semiconductors Octal dual supply translating transceiver; 3-state DHVQFN24: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 24 terminals; body 3.5 x 5.5 x 0.85 mm B D SOT815-1 A A E A1 c detail X terminal 1 index area C e1 terminal 1 index area e y1 C v M C A B w M C b 2 y 11 L 12 1 e2 Eh 24 13 23 14 X Dh 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b c D (1) Dh E (1) Eh e e1 e2 L v w y y1 mm 1 0.05 0.00 0.30 0.18 0.2 5.6 5.4 4.25 3.95 3.6 3.4 2.25 1.95 0.5 4.5 1.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT815-1 --- --- --- EUROPEAN PROJECTION ISSUE DATE 03-04-29 Fig 12. Package outline SOT815-1 (DHVQFN24) 74LVC4245A_6 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 06 — 18 January 2008 14 of 17 74LVC4245A NXP Semiconductors Octal dual supply translating transceiver; 3-state 13. Abbreviations Table 9. Abbreviations Acronym Description ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 10. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC4245A_6 20080118 Product data sheet - 74LVC4245A_5 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • • • Legal texts have been adapted to the new company name where appropriate. Section 3: DHVQFN24 package added. Section 7: derating values added for DHVQFN24 package. Section 12: outline drawing added for DHVQFN24 package. 74LVC4245A_5 20040330 Product specification - 74LVC4245A_4 74LVC4245A_4 20040211 Product specification - 74LVC4245A_3 74LVC4245A_3 19990615 Product specification - 74LVC4245A_2 74LVC4245A_2 19980729 Product specification - 74LVC4245A_1 74LVC4245A_1 19980729 Product specification - - 74LVC4245A_6 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 06 — 18 January 2008 15 of 17 74LVC4245A NXP Semiconductors Octal dual supply translating transceiver; 3-state 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 15.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74LVC4245A_6 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 06 — 18 January 2008 16 of 17 74LVC4245A NXP Semiconductors Octal dual supply translating transceiver; 3-state 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Contact information. . . . . . . . . . . . . . . . . . . . . 16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 18 January 2008 Document identifier: 74LVC4245A_6