82582Sxx

GS82582S18/36GE-400/375/333/300/250
288Mb SigmaSIOTM DDR-II
Burst of 2 SRAM
165-Bump BGA
Commercial Temp
Industrial Temp
400 MHz–250 MHz
1.8 V VDD
1.8 V and 1.5 V I/O
Features
Clocking and Addressing Schemes
• Simultaneous Read and Write SigmaSIO™ Interface
• JEDEC-standard pinout and package
• Dual Double Data Rate interface
• Byte Write controls sampled at data-in time
• DLL circuitry for wide output data valid window and future
frequency scaling
• Burst of 2 Read and Write
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation
• Fully coherent read and write pipelines
• ZQ mode pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• RoHS-compliant 165-bump BGA package
A Burst of 2SigmaSIO DDR-II SRAM is a synchronous
device. It employs dual input register clock inputs, K and K.
The device also allows the user to manipulate the output
register clock input quasi independently with dual output
register clock inputs, C and C. If the C clocks are tied high, the
K clocks are routed internally to fire the output registers
instead. Each Burst of 2SigmaSIO DDR-II SRAM also
supplies Echo Clock outputs, CQ and CQ, which are
synchronized with read data output. When used in a source
synchronous clocking scheme, the Echo Clock outputs can be
used to fire input registers at the data’s destination.
SigmaSIO™ Family Overview
GS82582S18/36GE are built in compliance with the SigmaSIO
DDR-II SRAM pinout standard for Separate I/O synchronous
SRAMs. They are 301,989,888-bit (288Mb) SRAMs. These
are the first in a family of wide, very low voltage HSTL I/O
SRAMs designed to operate at the speeds needed to implement
economical high performance networking systems.
Each internal read and write operation in a SigmaSIO DDR-II
B2 RAM is two times wider than the device I/O bus. An input
data bus de-multiplexer is used to accumulate incoming data
before it is simultaneously written to the memory array. An
output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore, the address
field of a SigmaSIO DDR-II B2 is always one address pin less
than the advertised index depth (e.g., the 16M x 18 has an 8M
addressable index).
Parameter Synopsis
Rev: 1.04 4/2016
-400
-375
-333
-300
-250
tKHKH
2.5 ns
2.66 ns
3.0 ns
3.3 ns
4.0 ns
tKHQV
0.45 ns
0.45 ns
0.45 ns
0.45 ns
0.45 ns
1/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology
GS82582S18/36GE-400/375/333/300/250
16M x 18 SigmaQuad SRAM—Top View
1
2
3
4
5
6
7
8
9
10
11
A
CQ
SA
SA
R/W
BW1
K
SA
LD
SA
SA
CQ
B
NC
Q9
D9
SA
NC
K
BW0
SA
NC
NC
Q8
C
NC
NC
D10
VSS
SA
SA
SA
VSS
NC
Q7
D8
D
NC
D11
Q10
VSS
VSS
VSS
VSS
VSS
NC
NC
D7
E
NC
NC
Q11
VDDQ
VSS
VSS
VSS
VDDQ
NC
D6
Q6
F
NC
Q12
D12
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
Q5
G
NC
D13
Q13
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
D5
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
D14
VDDQ
VDD
VSS
VDD
VDDQ
NC
Q4
D4
K
NC
NC
Q14
VDDQ
VDD
VSS
VDD
VDDQ
NC
D3
Q3
L
NC
Q15
D15
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
Q2
M
NC
NC
D16
VSS
VSS
VSS
VSS
VSS
NC
Q1
D2
N
NC
D17
Q16
VSS
SA
SA
SA
VSS
NC
NC
D1
P
NC
NC
Q17
SA
SA
C
SA
SA
NC
D0
Q0
R
TDO
TCK
SA
SA
SA
C
SA
SA
SA
TMS
TDI
11 x 15 Bump BGA—15 x 17 mm2 Body—1 mm Bump Pitch
Notes:
1. BW0 controls writes to D0:D8. BW1 controls writes to D9:D17.
2. A7 is the expansion address.
Rev: 1.04 4/2016
2/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology
GS82582S18/36GE-400/375/333/300/250
8M x 36 SigmaQuad SRAM—Top View
1
2
3
4
5
6
7
8
9
10
11
A
CQ
SA
SA
R/W
BW2
K
BW1
LD
SA
SA
CQ
B
Q27
Q18
D18
SA
BW3
K
BW0
SA
D17
Q17
Q8
C
D27
Q28
D19
VSS
SA
SA
SA
VSS
D16
Q7
D8
D
D28
D20
Q19
VSS
VSS
VSS
VSS
VSS
Q16
D15
D7
E
Q29
D29
Q20
VDDQ
VSS
VSS
VSS
VDDQ
Q15
D6
Q6
F
Q30
Q21
D21
VDDQ
VDD
VSS
VDD
VDDQ
D14
Q14
Q5
G
D30
D22
Q22
VDDQ
VDD
VSS
VDD
VDDQ
Q13
D13
D5
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
D31
Q31
D23
VDDQ
VDD
VSS
VDD
VDDQ
D12
Q4
D4
K
Q32
D32
Q23
VDDQ
VDD
VSS
VDD
VDDQ
Q12
D3
Q3
L
Q33
Q24
D24
VDDQ
VSS
VSS
VSS
VDDQ
D11
Q11
Q2
M
D33
Q34
D25
VSS
VSS
VSS
VSS
VSS
D10
Q1
D2
N
D34
D26
Q25
VSS
SA
SA
SA
VSS
Q10
D9
D1
P
Q35
D35
Q26
SA
SA
C
SA
SA
Q9
D0
Q0
R
TDO
TCK
SA
SA
SA
C
SA
SA
SA
TMS
TDI
11 x 15 Bump BGA—15 x 17 mm2 Body—1 mm Bump Pitch
Notes:
1. BW0 controls writes to D0:D8. BW1 controls writes to D9:D17.
2. BW2 controls writes to D18:D26. BW3 controls writes to D27:D35.
3. A2 is the expansion address.
Rev: 1.04 4/2016
3/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology
GS82582S18/36GE-400/375/333/300/250
Pin Description Table
Symbol
Description
Type
Comments
SA
Synchronous Address Inputs
Input
—
R/W
Read/Write Contol Pin
Input
Write Active Low; Read Active High
BW0–BW1
Synchronous Byte Writes
Input
Active Low
x18 Version
BW0–BW3
Synchronous Byte Writes
Input
Active Low
x36 Version
K
Input Clock
Input
Active High
C
Output Clock
Input
Active High
TMS
Test Mode Select
Input
—
TDI
Test Data Input
Input
—
TCK
Test Clock Input
Input
—
TDO
Test Data Output
Output
—
VREF
HSTL Input Reference Voltage
Input
—
ZQ
Output Impedance Matching Input
Input
—
K
Input Clock
Input
Active Low
C
Output Clock
Output
Active Low
DOFF
DLL Disable
—
Active Low
LD
Synchronous Load Pin
—
Active Low
CQ
Output Echo Clock
Output
Active Low
CQ
Output Echo Clock
Output
Active High
Dn
Synchronous Data Inputs
Input
—
Qn
Synchronous Data Outputs
Output
—
VDD
Power Supply
Supply
1.8 V Nominal
VDDQ
Isolated Output Buffer Supply
Supply
1.8 or 1.5 V Nominal
VSS
Power Supply: Ground
Supply
—
NC
No Connect
—
—
Notes:
1. C, C, K, or K cannot be set to VREF voltage.
2. When ZQ pin is directly connected to VDDQ, output impedance is set to minimum value and it cannot be connected to ground or left
unconnected.
3. NC = Not Connected to die or any other pin
Rev: 1.04 4/2016
4/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology
GS82582S18/36GE-400/375/333/300/250
Background
Separate I/O SRAMs, like SigmaQuad SRAMs, are attractive in applications where alternating reads and writes are needed. On the
other hand, Common I/O SRAMs like the SigmaCIO family are popular in applications where bursts of read or write traffic are
needed. The SigmaSIO SRAM is a hybrid of these two devices. Like the SigmaQuad family devices, the SigmaSIO features a
separate I/O data path, offering the user independent Data In and Data Out pins. However, the SigmaSIO devices offer a control
protocol like that offered on the SigmaCIO devices. Therefore, while SigmaQuad SRAMs allow a user to operate both data ports at
the same time, they force alternating loads of read and write addresses. SigmaSIO SRAMs allow continuous loads of read or write
addresses like SigmaCIO SRAMs, but in a separate I/O configuration.
Like a SigmaQuad SRAM, a SigmaSIO DDR-II SRAM can execute an alternating sequence of reads and writes. However, doing
so results in the Data In port and the Data Out port stalling with nothing to do on alternate transfers. A SigmaQuad device would
keep both ports running at capacity full time. On the other hand, the SigmaSIO device can accept a continuous stream of read
commands and read data or a continuous stream of write commands and write data. The SigmaQuad device, by contrast, restricts
the user from loading a continuous stream of read or write addresses. The advantage of the SigmaSIO device is that it allows twice
the random address bandwidth for either reads or writes than could be acheived with a SigmaQuad version of the device.
SigmaDDR (CIO) SRAMs offer this same advantage, but do not have the separate Data In and Data Out pins offered on the
SigmaSIO SRAMs. Therefore, SigmaSIO devices are useful in psuedo dual port SRAM applications where communication of
burst traffic between two electrically independent busses is desired.
Each of the three SigmaQuad Family SRAMs—SigmaQuad, SigmaDDR, and SigmaSIO—supports similar address rates because
random address rate is determined by the internal performance of the RAM. In addition, all three SigmaQuad Family SRAMs are
based on the same internal circuits. Differences between the truth tables of the different devices proceed from differences in how
the RAM’s interface is contrived to interact with the rest of the system. Each mode of operation has its own advantages and
disadvantages. The user should consider the nature of the work to be done by the RAM to evaluate which version is best suited to
the application at hand.
Burst of 2 SigmaSIO DDR-II SRAM DDR Read
The status of the Address Input, R/W, and LD pins are sampled at each rising edge of K. LD high causes chip disable. A high on
the R/W pin begins a read cycle. The two resulting data output transfers begin after the next rising edge of the K clock. Data is
clocked out by the next rising edge of the C if it is active. Otherwise, data is clocked out at the next rising edge of K. The next data
chunk is clocked out on the rising edge of C, if active. Otherwise, data is clocked out on the rising edge of K.
Burst of 2 SigmaSIO DDR-II SRAM DDR Write
The status of the Address Input, R/W, and LD pins are sampled at each rising edge of K. LD high causes chip disable. A low on the
R/W pin, begins a write cycle. Data is clocked in by the next rising edge of K and then the rising edge of K.
Rev: 1.04 4/2016
5/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology
GS82582S18/36GE-400/375/333/300/250
Special Functions
Byte Write Control
Byte Write Enable pins are sampled at the same time that Data In is sampled. A high on the Byte Write Enable pin associated with
a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be
stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven high or low
during the data in sample times in a write sequence.
Each write enable command and write address loaded into the RAM provides the base address for a 2-beat data transfer. The x18
version of the RAM, for example, may write 36 bits in association with each address loaded. Any 9-bit byte may be masked in any
write sequence.
Example x18 RAM Write Sequence using Byte Write Enables
Data In Sample Time
BW0
BW1
D0–D8
D9–D17
Beat 1
0
1
Data In
Don’t Care
Beat 2
1
0
Don’t Care
Data In
Resulting Write Operation
Beat 1
Beat 2
D0–D8
D9–D17
D0–D8
D9–D17
Written
Unchanged
Unchanged
Written
Output Register Control
SigmaSIO DDR-II SRAMs offer two mechanisms for controlling the output data registers. Typically, control is handled by the
Output Register Clock inputs, C and C. The Output Register Clock inputs can be used to make small phase adjustments in the firing
of the output registers by allowing the user to delay driving data out as much as a few nanoseconds beyond the next rising edges of
the K and K clocks. If the C and C clock inputs are tied high, the RAM reverts to K and K control of the outputs.
Rev: 1.04 4/2016
6/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology
GS82582S18/36GE-400/375/333/300/250
Example Four Bank Depth Expansion Schematic
R/W3
LD3
R/W2
LD2
R/W1
LD1
R/W0
LD0
A0–An
K
D1–Dn
Bank 0
Bank 1
Bank 2
Bank 3
A
A
A
A
R/W
R/W
R/W
R/W
LD
LD
LD
LD
K
D
K
D
K
D
K
Q
C
Q
C
Q
C
D
Q
C
C
Q1–Qn
Note:
For simplicity BWn is not shown.
Rev: 1.04 4/2016
7/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology
Rev: 1.04 4/2016
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
8/31
CQ Bank 2
CQ Bank 2
Q Bank 2
C Bank 2
C Bank 2
CQ Bank 1
CQ Bank 1
Q Bank 1
C Bank 1
C Bank 1
D Bank 2
D Bank 1
BWx Bank 2
BWx Bank 1
R/W Bank 2
R/W Bank 1
LD Bank 2
LD Bank 1
Address
K
K
B
Write B
B
C
B+1
Read C
D
Write D
C
D
E
C+1
D+1
Read E
F
Write F
E
F
G
E+1
F+1
Read G
Read H
H
Burst of 2 SigmaSIO DDR-II SRAM Depth Expansion
G
J
G+1
Read J
H
H+1
NOP
J
GS82582S18/36GE-400/375/333/300/250
© 2012, GSI Technology
GS82582S18/36GE-400/375/333/300/250
FLXDrive-II Output Driver Impedance Control
HSTL I/O SigmaSIO DDR-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected
to VSS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be
5X the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching
with a vendor-specified tolerance is between 175 and 350. Periodic readjustment of the output driver impedance is necessary as
the impedance is affected by drifts in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for
drifts in supply voltage and temperature. A clock cycle counter periodically triggers an impedance evaluation, resets and counts
again. Each impedance evaluation may move the output driver impedance level one step at a time towards the optimum level. The
output driver is implemented with discrete binary weighted impedance steps.
Power-Up Initialization
After power-up, stable input clocks must be applied to the device for 20 s prior to issuing read and write commands. See the tKInit
timing parameter in the AC Electrical Characteristics section.
Note:
The tKInit requirement is independent of the tLock requirement, which specifies how many cycles of stable input clocks (2048)
must be applied after the Doff pin has been driven High in order to ensure that the DLL locks properly (and the DLL must lock
properly before issuing read and write commands). However, tKInit is greater than tKLock, even at the slowest permitted cycle time
of 8.4 ns (2048*8.4 ns = 17.2 s). Consequently, the 20 s associated with tKInit is sufficient to cover the tKLock requirement at
power-up if the Doff pin is driven High prior to the start of the 20 s period.
Also, tKInit only needs to be met once, immediately after power-up, whereas tKLock must be met any time the DLL is disabled/reset
(whether by toggling Doff Low or by stopping K clocks for > 30 ns).
Separate I/O Burst of 2 Sigma SIO-II SRAM Truth Table
A
LD
R/W
Current
Operation
D
D
Q
Q
K
(tn)
K
(tn)
K
(tn)
K
(tn)
K
(tn + 1)
K
(tn + 1½)
K
(tn + 1½)
K
(tn + 2)
X
1
X
Deselect
X
X
Hi-Z
Hi-Z
V
0
1
Read
X
X
Q0
Q1
V
0
0
Write
D0
D1
Hi-Z
Hi-Z
Notes:
1. “1” = input “high”; “0” = input “low”; “V” = input “valid”; “X” = input “don’t care”
2. Q0 and Q1 indicate the first and second pieces of output data transferred during Read operations.
3. D0 and D1 indicate the first and second pieces of input data transferred during Write operations.
4. Users should not clock in metastable addresses.
Rev: 1.04 4/2016
9/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology
GS82582S18/36GE-400/375/333/300/250
B2 Byte Write Clock Truth Table
BW
BW
Current Operation
D
D
K
(tn + 1)
K
(tn + 1½)
K
(tn)
K
(tn + 1)
K
(tn + 1½)
T
T
Write
Dx stored if BWn = 0 in both data transfers
D1
D2
T
F
Write
Dx stored if BWn = 0 in 1st data transfer only
D1
X
F
T
Write
Dx stored if BWn = 0 in 2nd data transfer only
X
D2
F
F
Write Abort
No Dx stored in either data transfer
X
X
Notes:
1. “1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.
2. If one or more BWn = 0, then BW = “T”, else BW = “F”.
Rev: 1.04 4/2016
10/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology
GS82582S18/36GE-400/375/333/300/250
x36 Byte Write Enable (BWn) Truth Table
BW3
BW2
BW1
BW0
D27–D35
D18–D26
D9–D17
D0–D8
1
1
1
1
Don’t Care
Don’t Care
Don’t Care
Don’t Care
0
1
1
1
Don’t Care
Don’t Care
Don’t Care
Data In
1
0
1
1
Don’t Care
Don’t Care
Data In
Don’t Care
0
0
1
1
Don’t Care
Don’t Care
Data In
Data In
1
1
0
1
Don’t Care
Data In
Don’t Care
Don’t Care
0
1
0
1
Don’t Care
Data In
Don’t Care
Data In
1
0
0
1
Don’t Care
Data In
Data In
Don’t Care
0
0
0
1
Don’t Care
Data In
Data In
Data In
1
1
1
0
Data In
Don’t Care
Don’t Care
Don’t Care
0
1
1
0
Data In
Don’t Care
Don’t Care
Data In
1
0
1
0
Data In
Don’t Care
Data In
Don’t Care
0
0
1
0
Data In
Don’t Care
Data In
Data In
1
1
0
0
Data In
Data In
Don’t Care
Don’t Care
0
1
0
0
Data In
Data In
Don’t Care
Data In
1
0
0
0
Data In
Data In
Data In
Don’t Care
0
0
0
0
Data In
Data In
Data In
Data In
x18 Byte Write Enable (BWn) Truth Table
BW0
BW1
D0–D8
D9–D17
1
1
Don’t Care
Don’t Care
0
1
Data In
Don’t Care
1
0
Don’t Care
Data In
0
0
Data In
Data In
Rev: 1.04 4/2016
11/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology
GS82582S18/36GE-400/375/333/300/250
Absolute Maximum Ratings
(All voltages reference to VSS)
Symbol
Description
Value
Unit
VDD
Voltage on VDD Pins
–0.5 to 2.9
V
VDDQ
Voltage in VDDQ Pins
–0.5 to VDD
V
VREF
Voltage in VREF Pins
–0.5 to VDDQ
V
VI/O
Voltage on I/O Pins
–0.5 to VDDQ +0.3 ( 2.9 V max.)
V
VIN
Voltage on Other Input Pins
–0.5 to VDDQ +0.3 ( 2.9 V max.)
V
IIN
Input Current on Any Pin
+/–100
mA dc
IOUT
Output Current on Any I/O Pin
+/–100
mA dc
TJ
Maximum Junction Temperature
125
oC
TSTG
Storage Temperature
–55 to 125
oC
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect
reliability of this component.
Recommended Operating Conditions
Power Supplies
Parameter
Symbol
Min.
Typ.
Max.
Unit
Supply Voltage
VDD
1.7
1.8
1.9
V
I/O Supply Voltage
VDDQ
1.4
—
VDD
V
Reference Voltage
VREF
0.68
—
0.95
V
Note:
The power supplies need to be powered up simultaneously or in the following sequence: VDD, VDDQ, VREF, followed by signal inputs. The power
down sequence must be the reverse. VDDQ must not exceed VDD. For more information, read AN1021 SigmaQuad and SigmaDDR Power-Up.
Operating Temperature
Parameter
Symbol
Min.
Typ.
Max.
Unit
Junction Temperature
(Commercial Range Versions)
TJ
0
25
85
C
Junction Temperature
(Industrial Range Versions)*
TJ
–40
25
100
C
Note:
* The part numbers of Industrial Temperature Range versions end with the character “I”. Unless otherwise noted, all performance specifications
quoted are evaluated for worst case in the temperature range marked on the device.
Rev: 1.04 4/2016
12/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology
GS82582S18/36GE-400/375/333/300/250
Thermal Impedance
Package
Test PCB
Substrate
JA (C°/W)
Airflow = 0 m/s
 JA (C°/W)
Airflow = 1 m/s
 JA (C°/W)
Airflow = 2 m/s
JB (C°/W)
 JC (C°/W)
165 BGA
4-layer
16.10
13.69
12.73
6.54
2.08
Notes:
1. Thermal Impedance data is based on a number of of samples from mulitple lots and should be viewed as a typical number.
2. Please refer to JEDEC standard JESD51-6.
3. The characteristics of the test fixture PCB influence reported thermal characteristics of the device. Be advised that a good thermal path to
the PCB can result in cooling or heating of the RAM depending on PCB temperature.
HSTL I/O DC Input Characteristics
Parameter
Symbol
Min
Max
Units
Notes
DC Input Logic High
VIH (dc)
VREF + 0.1
VDDQ + 0.3
mV
1
DC Input Logic Low
VIL (dc)
–0.3
VREF – 0.1
mV
1
Note:
Compatible with both 1.8 V and 1.5 V I/O drivers
HSTL I/O AC Input Characteristics
Parameter
Symbol
Min
Max
Units
Notes
AC Input Logic High
VIH (ac)
VREF + 0.2
—
mV
2,3
AC Input Logic Low
VIL (ac)
—
VREF – 0.2
mV
2,3
VREF (ac)
—
5% VREF (DC)
mV
1
VREF Peak- to-Peak AC Voltage
Notes:
1. The peak-to-peak AC component superimposed on VREF may not exceed 5% of the DC component of VREF..
2. To guarantee AC characteristics, VIH,VIL, Trise, and Tfall of inputs and clocks must be within 10% of each other.
3. For devices supplied with HSTL I/O input buffers. Compatible with both 1.8 V and 1.5 V I/O drivers.
Undershoot Measurement and Timing
Overshoot Measurement and Timing
VIH
20% tKHKH
VDD + 1.0 V
VSS
50%
50%
VDD
VSS – 1.0 V
20% tKHKH
Rev: 1.04 4/2016
VIL
13/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology
GS82582S18/36GE-400/375/333/300/250
Capacitance
(TA = 25oC, f = 1 MHZ, VDD = 1.8 V)
Parameter
Symbol
Test conditions
Typ.
Max.
Unit
Input Capacitance
CIN
VIN = 0 V
4
5
pF
Output Capacitance
COUT
VOUT = 0 V
6
7
pF
Clock Capacitance
CCLK
—
5
6
pF
Note:
This parameter is sample tested.
AC Test Conditions
Parameter
Conditions
Input high level
VDDQ
Input low level
0V
Max. input slew rate
2 V/ns
Input reference level
VDDQ/2
Output reference level
VDDQ/2
Note:
Test conditions as specified with output loading as shown unless otherwise noted.
AC Test Load Diagram
DQ
50
RQ = 250 (HSTL I/O)
VREF = 0.75 V
VT = VDDQ/2
Input and Output Leakage Characteristics
Parameter
Symbol
Test Conditions
Min.
Max
Input Leakage Current
(except mode pins)
IIL
VIN = 0 to VDD
–2 uA
2 uA
Doff
IILDOFF
VIN = 0 to VDD
–20 uA
2 uA
Output Leakage Current
IOL
Output Disable,
VOUT = 0 to VDDQ
–2 uA
2 uA
Rev: 1.04 4/2016
14/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology
GS82582S18/36GE-400/375/333/300/250
Programmable Impedance HSTL Output Driver DC Electrical Characteristics
Parameter
Symbol
Min.
Max.
Units
Notes
Output High Voltage
VOH1
VDDQ/2 – 0.12
VDDQ/2 + 0.12
V
1, 3
Output Low Voltage
VOL1
VDDQ/2 – 0.12
VDDQ/2 + 0.12
V
2, 3
Output High Voltage
VOH2
VDDQ – 0.2
VDDQ
V
4, 5
Output Low Voltage
VOL2
Vss
0.2
V
4, 6
Notes:
1. IOH = (VDDQ/2) / (RQ/5) +/– 15% @ VOH = VDDQ/2 (for: 175 RQ  350
2. IOL = (VDDQ/2) / (RQ/5) +/– 15% @ VOL = VDDQ/2 (for: 175  RQ  350.
3. Parameter tested with RQ = 250 and VDDQ = 1.5 V or 1.8 V
4. 0RQ  
5. IOH = –1.0 mA
6. IOL = 1.0 mA
Rev: 1.04 4/2016
15/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology
Rev: 1.04 4/2016
IDD
IDD
ISB1
Operating Current (x36):
DDR
Operating Current (x18):
DDR
Standby Current (NOP):
DDR
1.
2.
3.
4.
IOUT = 0 mA, f = Max,
All Inputs 0.2 V or VDD – 0.2 V
470
760
VDD = Max, IOUT = 0 mA
Cycle Time tKHKH Min
Device deselected,
820
490
780
840
–40
to
85°C
-400
0
to
70°C
VDD = Max, IOUT = 0 mA
Cycle Time tKHKH Min
Test Conditions
Power measured with output pins floating.
Minimum cycle, IOUT = 0 mA
Operating current is calculated with 50% read cycles and 50% write cycles.
Standby Current is only after all pending read and write burst operations are completed.
Notes:
Symbol
Parameter
Operating Currents
450
720
780
0
to
70°C
470
740
800
–40
to
85°C
-375
420
660
700
0
to
70°C
440
680
720
–40
to
85°C
-333
400
610
650
0
to
70°C
420
630
670
–40
to
85°C
-300
360
530
560
0
to
70°C
380
550
580
–40
to
85°C
-250
mA
mA
mA
Unit
2, 4
2, 3
2, 3
Notes
GS82582S18/36GE-400/375/333/300/250
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
16/31
© 2012, GSI Technology
GS82582S18/36GE-400/375/333/300/250
Parameter
Symbol
-400
-375
-333
-300
-250
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Units
Notes
AC Electrical Characteristics
Clock
K, K Clock Cycle Time
C, C Clock Cycle Time
tKHKH
tCHCH
2.5
8.4
2.66
8.4
3.0
4.5
3.3
4.5
4.0
8.4
ns
tKC Variable
tKCVar
—
0.2
—
0.2
—
0.2
—
0.2
—
0.2
ns
K, K Clock High Pulse Width
C, C Clock High Pulse Width
tKHKL
tCHCL
1.0
—
1.06
—
1.2
—
1.32
—
1.6
—
ns
K, K Clock Low Pulse Width
C, C Clock Low Pulse Width
tKLKH
tCLCH
1.0
—
1.06
—
1.2
—
1.32
—
1.6
—
ns
K to K High
C to C High
tKHKH
tCHCH
1.5
—
1.13
—
1.35
—
1.49
—
1.8
—
ns
K to K High
C to C High
tKHKH
tCHCH
1.5
—
1.13
—
1.35
—
1.49
—
1.8
—
ns
K, K Clock High to C, C Clock High
tKHCH
0
1.21
0
1.21
0
1.35
0
1.49
0
1.8
ns
DLL Lock Time
tKLock
1024
—
1024
—
1024
—
1024
—
1024
—
cycle
K Static to DLL reset
tKReset
30
—
30
—
30
—
30
—
30
—
ns
tKInit
20
—
20
—
20
—
20
—
20
—
s
9
K, K Clock High to Data Output Valid
C, C Clock High to Data Output Valid
tKHQV
tCHQV
—
0.45
—
0.45
—
0.45
—
0.45
—
0.45
ns
4
K, K Clock High to Data Output Hold
C, C Clock High to Data Output Hold
tKHQX
tCHQX
–0.45
—
–0.45
—
–0.45
—
–0.45
—
–0.45
—
ns
4
K, K Clock High to Echo Clock Valid
C, C Clock High to Echo Clock Valid
tKHCQV
tCHCQV
—
0.45
—
0.45
—
0.45
—
0.45
—
0.45
ns
K, K Clock High to Echo Clock Hold
C, C Clock High to Echo Clock Hold
tKHCQX
tCHCQX
–0.45
—
–0.45
—
–0.45
—
–0.45
—
–0.45
—
ns
CQ, CQ High Output Valid
tCQHQV
—
0.2
—
0.2
—
0.25
—
0.27
—
0.30
ns
8
CQ, CQ High Output Hold
tCQHQX
–0.2
—
–0.2
—
–0.25
—
–0.27
—
–0.30
—
ns
8
CQ Phase Distortion
tCQHCQH
tCQHCQH
1.0
—
1.0
—
1.10
—
1.24
—
1.55
—
ns
tKHQZ
tCHQZ
—
0.45
—
0.45
—
0.45
—
0.45
—
0.45
ns
K, K Clock Initialization
6
7
Output Times
K Clock High to Data Output High-Z
C Clock High to Data Output High-Z
4
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
All Address inputs must meet the specified setup and hold times for all latching clock edges.
Control singles are R/ W, LD.
Control singles are BW0, BW1 (and BW2, BW3 for x36).
If C, C are tied high, K, K become the references for C, C timing parameters
To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus contention because tCHQX1 is a MIN
parameter that is worst case at totally different test conditions (0°C, 1.9 V) than tCHQZ, which is a MAX parameter (worst case at 70°C, 1.7 V). It is not possible for two
SRAMs on the same board to be at such different voltages and temperatures.
Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
VDD slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once VDD and input clock are stable.
Echo clock is very tightly controlled to data valid/data hold. By design, there is a ±0.1 ns variation from echo clock to data. The datasheet parameters reflect tester guard
bands and test setup variations.
After device power-up, 20s of stable input clocks (as specified by tKInit) must be supplied before reads and writes are issued.
Rev: 1.04 4/2016
17/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology
GS82582S18/36GE-400/375/333/300/250
AC Electrical Characteristics (Continued)
Symbol
-400
-375
-333
-300
-250
Units
Notes
Parameter
—
ns
4
0.5
—
ns
1
—
0.5
—
ns
2
0.3
—
0.35
—
ns
3
—
0.3
—
0.35
—
ns
0.4
—
0.4
—
0.5
—
ns
1
—
0.4
—
0.4
—
0.5
—
ns
2
0.28
—
0.28
—
0.3
—
0.35
—
ns
3
0.28
—
0.28
—
0.3
—
0.35
—
ns
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
tKHQX1
tCHQX1
–0.45
—
–0.45
—
–0.45
—
–0.45
—
–0.45
Address Input Setup Time
tAVKH
0.4
—
0.4
—
0.4
—
0.4
—
Control Input Setup Time(R/ W) (LD)
tIVKH
0.4
—
0.4
—
0.4
—
0.4
Control Input Setup Time
(BWX) (NWX)
tIVKH
0.28
—
0.28
—
0.28
—
Data Input Setup Time
tDVKH
0.28
—
0.28
—
0.28
Address Input Hold Time
tKHAX
0.4
—
0.4
—
Control Input Hold Time (R/ W) (LD)
tKHIX
0.4
—
0.4
Control Input Hold Time
(BWX) (NWX)
tKHIX
0.28
—
Data Input Hold Time
tKHDX
0.28
—
K Clock High to Data Output Low-Z
C Clock High to Data Output Low-Z
Setup Times
Hold Times
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
All Address inputs must meet the specified setup and hold times for all latching clock edges.
Control singles are R/ W, LD.
Control singles are BW0, BW1 (and BW2, BW3 for x36).
If C, C are tied high, K, K become the references for C, C timing parameters
To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus contention because tCHQX1 is a MIN
parameter that is worst case at totally different test conditions (0°C, 1.9 V) than tCHQZ, which is a MAX parameter (worst case at 70°C, 1.7 V). It is not possible for two
SRAMs on the same board to be at such different voltages and temperatures.
Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
VDD slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once VDD and input clock are stable.
Echo clock is very tightly controlled to data valid/data hold. By design, there is a ±0.1 ns variation from echo clock to data. The datasheet parameters reflect tester guard
bands and test setup variations.
After device power-up, 20s of stable input clocks (as specified by tKInit) must be supplied before reads and writes are issued.
Rev: 1.04 4/2016
18/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology
GS82582S18/36GE-400/375/333/300/250
K Controlled Read-First Timing Diagram
Read A
Write B
Read C
Read E
Deselect
Deselect
KHKL
KHKH
KLKH
K
KH#KH
K
AVKH
KHAX
Address
A
B
C
IVKH
KHIX
IVKH
KHIX
D
E
LD
R/W
IVKH
KHIX
B
BWx
B+1
DVKH
KHDX
B
D
B+1
KHQX1
A
Q
KHQZ
A+1
KHQV
C
C+1
KHQX
D
D+1
CQ
KHCQV
KHCQX
CQHQV
CQHQX
CQ
Rev: 1.04 4/2016
19/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology
GS82582S18/36GE-400/375/333/300/250
K Controlled Write-First Timing Diagram
NOP
Write A
Read B
Read C
Write D
Write E
Deselect
KHKL
KHKH
KLKH
K
KH#KH
K
AVKH
KHAX
A
Address
IVKH
B
C
D
E
KHIX
LD
IVKH
KHIX
R/W
KHIX
IVKH
A
BWx
A+1
D
D+1
E
E+1
D
D+1
E
E+1
KHDX
DVKH
A
D
A+1
KHQV
KHQX1
B
Q
KHQX
B+1
C
KHQZ
C+1
KHCQX
KHCQV
CQ
KHCQX
KHCQV
CQHQX
CQHQV
CQ
Rev: 1.04 4/2016
20/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology
GS82582S18/36GE-400/375/333/300/250
C Controlled Read-First Timing Diagram
Read A
Write B
Read C
Read D
Deselect
Deselect
KHKL
KHKH
KLKH
K
KHKH#
K
AVKH
KHAX
A
Address
B
C
D
IVKH
KHIX
LD
IVKH
KHIX
R/W
KHIX
IVKH
B
BWx
B+1
KHDX
DVKH
B
D
B+1
CLCH
KHCH
CHCL
CHCH
C
CHCH#
C
CHQX1
A
Q
CHQZ
A+1
CHQV
C
CHQX
C+1
D
D+1
CQ
CHCQX
CHCQV
CQHCV
CQHQX
CQ
Rev: 1.04 4/2016
21/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology
GS82582S18/36GE-400/375/333/300/250
C Controlled Write-First Timing Diagram
NOP
Write A
Read B
Write C
Write D
Read E
Deselect
KHKL
KHKH
KLKH
K
KH#KH
K
KHAX
AVKH
A
Addr
IVKH
B
C
D
E
KHIX
LD
IVKH
KHIX
R/W
KHIX
IVKH
A
BWx
A+1
C
C+1
D
D+1
C
C+1
D
D+1
KHDX
DVKH
A
D
A+1
KHKL
KHKH
KLKH
C
KH#KH
C
CHQX1
CHQZ
CHQX
CHQV
B
Q
B+1
CQ
CQHQV
CQHQX
CQ
Rev: 1.04 4/2016
22/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology
GS82582S18/36GE-400/375/333/300/250
JTAG Port Operation
Overview
The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan
interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output
drivers are powered by VDD.
Disabling the JTAG Port
It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless
clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG
Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected.
JTAG Pin Descriptions
Pin
Pin Name
I/O
Description
TCK
Test Clock
In
Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate
from the falling edge of TCK.
TMS
Test Mode Select
In
The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP
controller state machine. An undriven TMS input will produce the same result as a logic one input
level.
In
The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers
placed between TDI and TDO. The register placed between TDI and TDO is determined by the
state of the TAP Controller state machine and the instruction that is currently loaded in the TAP
Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce
the same result as a logic one input level.
TDI
Test Data In
TDO
Test Data Out
Output that is active depending on the state of the TAP state machine. Output changes in
Out response to the falling edge of TCK. This is the output side of the serial registers placed between
TDI and TDO.
Note:
This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is
held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.
JTAG Port Registers
Overview
The various JTAG registers, refered to as Test Access Port or TAP Registers, are selected (one at a time) via the sequences of 1s
and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the
rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the
TDI and TDO pins.
Instruction Register
The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or
the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the
TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the
controller is placed in Test-Logic-Reset state.
Bypass Register
The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through
the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.
Rev: 1.04 4/2016
23/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology
GS82582S18/36GE-400/375/333/300/250
Boundary Scan Register
The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins.
The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The
Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the
device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan
Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in
Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z,
SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.
JTAG TAP Block Diagram
·
·
·
·
·
·
Boundary Scan Register
·
·
0
Bypass Register
0
108
·
1
·
·
2 1 0
Instruction Register
TDI
TDO
ID Code Register
31 30 29
·
· ··
2 1 0
Control Signals
TMS
TCK
Test Access Port (TAP) Controller
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
Rev: 1.04 4/2016
24/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology
GS82582S18/36GE-400/375/333/300/250
GSI Technology
JEDEC Vendor
ID Code
See BSDL Model
Bit #
Presence Register
ID Register Contents
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
0
X
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0 0 1 1 0 1 1 0 0 1
Tap Controller Instruction Set
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load
address, data or control signals into the RAM or to preload the I/O buffers.
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this
device is listed in the following table.
Rev: 1.04 4/2016
25/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology
GS82582S18/36GE-400/375/333/300/250
JTAG Tap Controller State Diagram
1
0
Test Logic Reset
0
Run Test Idle
1
Select DR
1
Select IR
0
0
1
1
Capture DR
Capture IR
0
0
Shift DR
1
1
Shift IR
0
1
1
Exit1 DR
0
Exit1 IR
0
0
Pause DR
1
Exit2 DR
1
Update DR
1
1
0
0
Pause IR
1
Exit2 IR
0
1
0
0
Update IR
1
0
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This
occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is
loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and
I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and
are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because
the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents
while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will
not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the
TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP
operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then
places the boundary scan register between the TDI and TDO pins.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with
all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is
still determined by its input pins.
Rev: 1.04 4/2016
26/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology
GS82582S18/36GE-400/375/333/300/250

Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command.
Then the EXTEST command is used to output the Boundary Scan Register’s contents, in parallel, on the RAM’s data output
drivers on the falling edge of TCK when the controller is in the Update-IR state.

Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected, the sate of all the RAM’s input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR
state, the RAM’s output pins drive out the value of the Boundary Scan Register location with which each output pin is associated.
IDCODE
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and
places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction
loaded in at power up and any time the controller is placed in the Test-Logic-Reset state.
SAMPLE-Z
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (highZ) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR
state.
JTAG TAP Instruction Set Summary
Instruction
Code
Description
Notes
EXTEST
000
Places the Boundary Scan Register between TDI and TDO.
1
IDCODE
001
Preloads ID Register and places it between TDI and TDO.
1, 2
SAMPLE-Z
010
Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.
Forces all RAM output drivers to High-Z.
1
GSI
011
GSI private instruction.
1
SAMPLE/PRELOAD
100
Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO.
1
GSI
101
GSI private instruction.
1
GSI
110
GSI private instruction.
1
BYPASS
111
Places Bypass Register between TDI and TDO.
1
Notes:
1. Instruction codes expressed in binary, MSB on left, LSB on right.
2. Default instruction automatically loaded at power-up and in test-logic-reset state.
Rev: 1.04 4/2016
27/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology
GS82582S18/36GE-400/375/333/300/250
JTAG Port Recommended Operating Conditions and DC Characteristics
Parameter
Symbol
Min.
Max.
Unit Notes
Test Port Input Low Voltage
VILJ
–0.3
0.3 * VDD
V
1
Test Port Input High Voltage
VIHJ
0.7 * VDD
VDD +0.3
V
1
TMS, TCK and TDI Input Leakage Current
IINHJ
–300
1
uA
2
TMS, TCK and TDI Input Leakage Current
IINLJ
–1
100
uA
3
TDO Output Leakage Current
IOLJ
–1
1
uA
4
Test Port Output High Voltage
VOHJ
VDD – 0.2
—
V
5, 6
Test Port Output Low Voltage
VOLJ
—
0.2
V
5, 7
Test Port Output CMOS High
VOHJC
VDD – 0.1
—
V
5, 8
Test Port Output CMOS Low
VOLJC
—
0.1
V
5, 9
Notes:
1. Input Under/overshoot voltage must be –1 V < Vi < VDDn +1 V not to exceed 2.9 V maximum, with a pulse width not to exceed 20% tTKC.
2. VILJ  VIN VDDn
3. 0 V VIN VILJn
4. Output Disable, VOUT = 0 to VDDn
5. The TDO output driver is served by the VDD supply.
6. IOHJ = –2 mA
7. IOLJ = + 2 mA
8. IOHJC = –100 uA
9. IOLJC = +100 uA
JTAG Port AC Test Conditions
Parameter
Conditions
Input high level
VDD – 0.2 V
Input low level
0.2 V
Input slew rate
1 V/ns
Input reference level
VDD/2
Output reference level
VDD/2
JTAG Port AC Test Load
TDO
50
30pF*
VDD/2
* Distributed Test Jig Capacitance
Notes:
1. Include scope and jig capacitance.
2. Test conditions as shown unless otherwise noted.
Rev: 1.04 4/2016
28/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology
GS82582S18/36GE-400/375/333/300/250
JTAG Port Timing Diagram
tTKC
tTKH
tTKL
TCK
tTH
tTS
TDI
tTH
tTS
TMS
tTKQ
TDO
tTH
tTS
Parallel SRAM input
JTAG Port AC Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
TCK Cycle Time
tTKC
50
—
ns
TCK Low to TDO Valid
tTKQ
—
20
ns
TCK High Pulse Width
tTKH
20
—
ns
TCK Low Pulse Width
tTKL
20
—
ns
TDI & TMS Set Up Time
tTS
10
—
ns
TDI & TMS Hold Time
tTH
10
—
ns
Rev: 1.04 4/2016
29/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology
GS82582S18/36GE-400/375/333/300/250
Package Dimensions—165-Bump FPBGA (Package GE)
A1 CORNER
TOP VIEW
BOTTOM VIEW
Ø0.10 M C
Ø0.25 M C A B
Ø0.40~0.60 (165x)
1 2 3 4 5 6 7 8 9 10 11
A1 CORNER
11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
1.0
14.0
17±0.05
1.0
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
1.0
1.0
10.0
0.15 C
B
C
Rev: 1.04 4/2016
0.20(4x)
0.36~0.46
1.50 MAX.
SEATING PLANE
15±0.05
30/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology
GS82582S18/36GE-400/375/333/300/250
Ordering Information—GSI SigmaSIO DDR-II SRAM
Org
Part Number1
Type
Package
Speed (MHz)
TJ2
16M x 18
GS82582S18GE-400
SigmaSIO DDR-II SRAM
RoHS-compliant 165-bump BGA
400
C
16M x 18
GS82582S18GE-375
SigmaSIO DDR-II SRAM
RoHS-compliant 165-bump BGA
375
C
16M x 18
GS82582S18GE-333
SigmaSIO DDR-II SRAM
RoHS-compliant 165-bump BGA
333
C
16M x 18
GS82582S18GE-300
SigmaSIO DDR-II SRAM
RoHS-compliant 165-bump BGA
300
C
16M x 18
GS82582S18GE-250
SigmaSIO DDR-II SRAM
RoHS-compliant 165-bump BGA
250
C
16M x 18
GS82582S18GE-400I
SigmaSIO DDR-II SRAM
RoHS-compliant 165-bump BGA
400
I
16M x 18
GS82582S18GE-375I
SigmaSIO DDR-II SRAM
RoHS-compliant 165-bump BGA
375
I
16M x 18
GS82582S18GE-333I
SigmaSIO DDR-II SRAM
RoHS-compliant 165-bump BGA
333
I
16M x 18
GS82582S18GE-300I
SigmaSIO DDR-II SRAM
RoHS-compliant 165-bump BGA
300
I
16M x 18
GS82582S18GE-250I
SigmaSIO DDR-II SRAM
RoHS-compliant 165-bump BGA
250
I
8M x 36
GS82582S36GE-400
SigmaSIO DDR-II SRAM
RoHS-compliant 165-bump BGA
400
C
8M x 36
GS82582S36GE-375
SigmaSIO DDR-II SRAM
RoHS-compliant 165-bump BGA
375
C
8M x 36
GS82582S36GE-333
SigmaSIO DDR-II SRAM
RoHS-compliant 165-bump BGA
333
C
8M x 36
GS82582S36GE-300
SigmaSIO DDR-II SRAM
RoHS-compliant 165-bump BGA
300
C
8M x 36
GS82582S36GE-250
SigmaSIO DDR-II SRAM
RoHS-compliant 165-bump BGA
250
C
8M x 36
GS82582S36GE-400I
SigmaSIO DDR-II SRAM
RoHS-compliant 165-bump BGA
400
I
8M x 36
GS82582S36GE-375I
SigmaSIO DDR-II SRAM
RoHS-compliant 165-bump BGA
375
I
8M x 36
GS82582S36GE-333I
SigmaSIO DDR-II SRAM
RoHS-compliant 165-bump BGA
333
I
8M x 36
GS82582S36GE-300I
SigmaSIO DDR-II SRAM
RoHS-compliant 165-bump BGA
300
I
8M x 36
GS82582S36GE-250I
SigmaSIO DDR-II SRAM
RoHS-compliant 165-bump BGA
250
I
Notes:
1. For Tape and Reel add the character “T” to the end of the part number. Example: GS82582S36GE-300T.
2. C = Commercial Temperature Range. I = Industrial Temperature Range.
SigmaSIO DDR-II Revision History
File Name
Format/Content
Description of changes
Creation of datasheet
82582Sxx_r1
82582Sxx_r1_01
Content
Updated speed bin offerings
82582Sxx_r1_02
Content
Removed x8 and x9 configurations
82582Sxx_r1_03
Content
• Removed leaded part numbers
• Added Power-Up Initialization section on page 10
• Added tKInit specification
82582Sxx_r1_04
Content
• Removed Preliminary banner
• Added Op Current CZ data
Rev: 1.04 4/2016
31/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2012, GSI Technology