LT1949-1 - 1.1MHz, 1A SwitchPWM DC/DC Converter

Final Electrical Specifications
LT1949-1
1.1MHz, 1A Switch
PWM DC/DC Converter
June 2000
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DESCRIPTIO
FEATURES
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1A, 0.5Ω, 30V Internal Switch
1.1MHz Fixed Frequency Operation
Operates with VIN as Low as 1.5V
Low-Battery Detector Stays Active in Shutdown
Low VCESAT Switch: 410mV at 800mA
Pin-for-Pin Compatible with the LT1317B
Uses Ceramic Capacitors
Small 8-Lead MSOP Package
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APPLICATIO S
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LCD Bias Supplies
GPS Receivers
Battery Backup
Portable Electronic Equipment
Diagnostic Medical Instrumentation
The LT1949-1 includes a low-battery detector that stays
alive when the device goes into shutdown. Quiescent
current in shutdown is 50µA, while operating current is
8mA.
, LTC and LT are registered trademarks of Linear Technology Corporation.
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The LT ®1949-1 is a fixed frequency step-up DC/DC converter with a 1A, 0.5Ω internal switch. Capable of generating 10V at 175mA from a 3.3V input, the LT1949-1 is
ideal for generating bias voltages for large screen LCD
panels. Constant frequency 1.1MHz operation results in a
low noise output that is easy to filter and the 30V switch
rating allows output voltage up to 28V using a single
inductor. The high switching frequency allows the use of
ceramic output capacitors. An external compensation pin
gives the user flexibility in optimizing loop compensation,
allowing small, low ESR ceramic capacitors to be used at
the output. The 8-lead MSOP package ensures a low
profile overall solution.
TYPICAL APPLICATIO
90
VIN
3.3V
L1
4.7µH
C1
3.3µF
CERAMIC
VIN
SHUTDOWN
SHDN
VOUT = 10V
D1
80
SW
VOUT
10V
175mA
FB
GND
VC
3pF
EFFICIENCY (%)
LT1949-1
3.6VIN 4.2VIN 3VIN
70
R1
196k
1%
60
50
40
84.5k
R2
28k
1%
50pF
C2
3.3µF
CERAMIC
30
20
C1, C2: TAIYO YUDEN LMK325BJ335MD
D1: MBRM120LT3
L1: SUMIDA CLQ4D10-4R7
1949-1 F01
Figure 1. 3.3V to 10V/175mA DC/DC Converter
5
10
50
100
LOAD CURRENT (mA)
300
1949-1 F02
Figure 2. 3.3V to 10V Converter Efficiency
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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LT1949-1
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ABSOLUTE
RATI GS
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PACKAGE/ORDER I FOR ATIO
(Note 1)
VIN, LBO Voltage ..................................................... 12V
SW Voltage ............................................... – 0.4V to 30V
FB Voltage .................................................... VIN + 0.3V
VC Voltage ................................................................ 2V
LBI Voltage ............................................ 0V ≤ VLBI ≤ 1V
SHDN Voltage ........................................................... 6V
Junction Temperature .......................................... 125°C
Operating Temperature Range (Note 2) ...–40°C to 85°C
Storage Temperature ........................... – 65°C to 150°C
Lead Temperature (Soldering, 10sec).................. 300°C
ORDER PART
NUMBER
TOP VIEW
VC
FB
SHDN
GND
1
2
3
4
8
7
6
5
LBO
LBI
VIN
SW
LT1949-1EMS8
MS8 PACKAGE
8-LEAD PLASTIC MSOP
MS8 PART MARKING
TJMAX = 125°C, θJA = 120°C/W
LTQX
Consult factory for Industrial and Military grade parts.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 2V, VSHDN = 2V unless otherwise noted.
SYMBOL
PARAMETER
IQ
Quiescent Current
CONDITIONS
●
●
VSHDN = 0V
VFB
MIN
Feedback Voltage
●
IB
FB Pin Bias Current (Note 3)
●
Input Voltage Range
gm
Error Amp Transconductance
AV
Error Amp Voltage Gain
∆I = 5µA
Maximum Duty Cycle
Switch Current Limit (Note 4)
fOSC
8
50
14
80
1.24
1.24
1.26
1.26
V
V
24
150
nA
12
V
280
480
µmhos
mA
µA
1.7
140
700
V/V
●
80
85
%
1
1.1
1.5
A
0.85
●
●
LBI Threshold Voltage
●
190
180
1.1
1.35
MHz
0.015
–5
0.1
– 14
µA
µA
200
200
210
220
mV
mV
LBO Output Low
ISINK = 10µA
●
0.15
0.25
V
LBO Leakage Current
VLBI = 250mV, VLBO = 5V
●
20
100
nA
LBI Input Bias Current (Note 5)
VLBI = 150mV
●
30
120
Low-Battery Detector Gain
1MΩ Pull-Up
Switch Leakage Current
VSW = 5V
Switch VCESAT
ISW = 800mA
ISW = 500mA
Reference Line Regulation
1.8V ≤ VIN ≤ 12V
nA
2000
●
0.01
●
410
270
V/V
3
µA
400
mV
mV
0.08
SHDN Input Voltage High
●
SHDN Input Voltage Low
●
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The LT1949-1E is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications over the – 40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
2
UNITS
●
●
VSHDN = VIN
VSHDN = 0V
MAX
●
VIN = 2.5V, Duty Cycle = 30%
Switching Frequency
Shutdown Pin Current
1.22
1.20
TYP
1.4
%/V
6
V
0.4
V
Note 3: Bias current flows into FB pin.
Note 4: Switch current limit guaranteed by design and/or correlation to
static tests. Duty cycle affects current limit due to ramp generator.
Note 5: Bias current flows out of LBI pin.
LT1949-1
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TYPICAL PERFOR A CE CHARACTERISTICS
Oscillator Frequency
85°C
25°C
1.1
–40°C
1.0
0.9
1.3
1.3
1.2
1.2
SWITCH CURRENT (A)
SWITCH CURRENT (A)
OSCILLATOR FREQUENCY (MHz)
1.3
1.2
Switch Current Limit,
Duty Cycle = 30%
Switch Current Limit
1.1
1.0
0.8
–50
0.8
2
4
6
8
INPUT VOLTAGE (V)
10
12
1.0
0.9
0.9
0
1.1
0
20
60
40
DUTY CYCLE (%)
1949-1 G01
80
100
–25
0
25
50
TEMPERATURE (°C)
75
1949-1 G03
1949-1 G02
Switch Voltage Drop (VCESAT)
Feedback Voltage
1.0
1.25
0.8
1.24
100
Quiescent Current, SHDN = 2V
8.5
85°C
0.6
25°C
0.4
–40°C
0.2
QUIESCENT CURRENT (mA)
FEEDBACK VOLTAGE (V)
SWITCH VOLTAGE (V)
8.0
1.23
1.22
1.21
7.5
7.0
6.5
6.0
5.5
5.0
0
0
0.2
0.4
0.6
0.8
SWITCH CURRENT (A)
1.0
1.20
–50
1.2
–25
0
25
50
TEMPERATURE (°C)
1949-1 G04
75
4.5
–50
100
–25
0
25
50
TEMPERATURE (°C)
75
1949-1 G06
1949-1 G05
Quiescent Current, SHDN = 0V
SHDN Pin Current
FB Pin Bias Current
60
100
60
2
55
50
45
40
35
50
SHDN PIN CURRENT (µA)
FB PIN BIAS CURRENT (nA)
QUIESCENT CURRENT (µA)
55
45
40
35
30
25
1
0
–2
–4
20
15
30
–50
–25
0
25
50
TEMPERATURE (°C)
75
100
1949-1 G07
10
–50
–6
–25
0
25
50
TEMPERATURE (°C)
75
100
1949-1 G08
0
1
2
4
3
SHDN PIN VOLTAGE (V)
5
6
1949-1 G09
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LT1949-1
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TYPICAL PERFOR A CE CHARACTERISTICS
Transient Response
VOUT
100mV/DIV
AC COUPLED
IL
500mA/DIV
20µs/DIV
VIN = 3.3V
VOUT = 10V
40mA TO 140mA LOAD STEP
CIRCUIT FIGURE 1
1949-1 G10
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PI FU CTIO S
VC (Pin 1): Compensation Pin for Error Amplifier. Connect a series RC network from this pin to ground. Typical
values for compensation are a 30k/330pF combination
when using ceramic output capacitors. Minimize trace
area at VC.
FB (Pin 2): Feedback Pin. Reference voltage is 1.24V.
Connect resistor divider tap here. Minimize trace area at
FB. Set VOUT according to: VOUT = 1.24V(1 + R1/R2).
SHDN (Pin 3): Shutdown. Pull this pin low for shutdown
mode (only the low-battery detector remains active).
Leave this pin floating or tie to a voltage between 1.4V and
6V to enable the device. SHDN pin is logic level and need
only meet the logic specification (1.4V for high, 0.4V for
low).
4
GND (Pin 4): Ground. Connect directly to local ground
plane.
SW (Pin 5): Switch Pin. Connect inductor/diode here.
Minimize trace area at this pin to keep EMI down.
VIN (Pin 6): Supply Pin. Must be bypassed close to the
pin.
LBI (Pin 7): Low-Battery Detector Input. 200mV reference. Voltage on LBI must stay between ground and
700mV. Low-battery detector remains active in shutdown
mode.
LBO (Pin 8): Low-Battery Detector Output. Open collector, can sink 10µA. A 1MΩ pull-up is recommended.
LT1949-1
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BLOCK DIAGRA
LBI
1.24V
REFERENCE
+
FB
2
1
ERROR
AMPLIFIER
+
–
+
7
VC
gm
LBO
8
–
200mV
A4
ENABLE
SHDN
VOUT
BIAS
R1
(EXTERNAL)
–
SHUTDOWN
SW
FB
R2
(EXTERNAL)
3
A1
COMPARATOR
5
–
RAMP
GENERATOR
+
Σ
+
+
FF
R
A2
COMPARATOR
DRIVER
Q3
Q
S
+
A=2
1.1MHz
OSCILLATOR
0.06Ω
–
4
1949-1 BD
GND
Figure 3. LT1949-1 Block Diagram
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OPERATIO
The LT1949-1 is a current mode, fixed frequency step-up
DC/DC converter with an internal 1A NPN power transistor. Operation can best be understood by referring to the
Block Diagram.
At the beginning of each oscillator cycle, the flip-flop is set
and the switch is turned on. Current in the switch ramps
up until the voltage at A2’s positive input reaches the VC
pin voltage, causing A2’s output to change state and the
switch to be turned off. The signal at A2’s positive input is
a summation of a signal representing switch current and
a ramp generator (introduced to avoid subharmonic oscillations at duty factors greater than 50%). If the load
increases, VOUT (and FB) will drop slightly and the error
amplifier will drive VC to a higher voltage, causing current
in the switch to increase. In this way, the error amplifier
drives the VC pin to the voltage necessary to satisfy the
load. Frequency compensation is provided by an external
series RC network connected between the VC pin and
ground.
Layout Hints
The LT1949-1 switches current at high speed, mandating
careful attention to layout for proper performance. You
will not get advertised performance with careless layouts.
Figure 4 shows recommended component placement for
a boost (step-up) converter. Follow this closely in your PC
layout. Note the direct path of the switching loops. Input
capacitor C1 must be placed close (< 5mm) to the IC
package. As little as 10mm of wire or PC trace from CIN to
VIN will cause problems such as inability to regulate or
oscillation.
The ground terminal of output capacitor C2 should tie
close to Pin 4 of the LT1949-1. Doing this reduces dI/dt in
the ground copper which keeps high frequency spikes to
a minimum. The DC/DC converter ground should tie to the
PC board ground plane at one place only, to avoid introducing dI/dt in the ground plane.
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LT1949-1
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OPERATIO
LBI LBO
GROUND PLANE
C1
VIN
1
8
R1
2
7
L1
LT1949-1
R2
SHUTDOWN
3
6
4
5
MULTIPLE
VIAs
C2
GND
VOUT
1949-1 F04
Figure 4. Recommended Component Placement for Boost
Converter. Note Direct High Current Paths Using Wide PC
Traces. Minimize Trace Area at Pin 1 (VC) and Pin 2 (FB).
Use Multiple Vias to Tie Pin 4 Copper to Ground Plane. Use
Vias at One Location Only to Avoid Introducing Switching
Currents into the Ground Plane
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APPLICATIO S I FOR ATIO
Low-Battery Detector
The LT1949-1’s low-battery detector is a simple PNP input
gain stage with an open collector NPN output. The negative input of the gain stage is tied internally to a 200mV
±5% reference. The positive input is the LBI pin. Arrangement as a low-battery detector is straightforward.
Figure␣ 5 details hookup. R1 and R2 need only be low
enough in value so that the bias current of the LBI pin
doesn’t cause large errors. For R2, 49.9k is adequate. The
200mV reference can also be accessed as shown in
Figure␣ 6. The low-battery detector remains active in
shutdown.
3.3V
R1
VIN
LBI
200k
LT1949-1
+
LBO
R2
49.9k
2N3906
1M
TO PROCESSOR
LT1949-1
VREF
200mV
LBI
+
10k
–
VIN
LBO
10µF
GND
1949-1 F06
200mV
INTERNAL
REFERENCE
GND
R1 =
VLB – 200mV
4µA
1949-1 F05
Figure 5. Setting Low-Battery Detector Trip Point
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Figure 6. Accessing 200mV Reference
LT1949-1
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TYPICAL APPLICATIO
4 Cell to 5V SEPIC Converter
C2
4.7µF
16V
L1
10µH
VIN
4V TO 9V
1M
VIN
SW
D1
L2
10µH
VOUT
5V
250mA
100k
1%
LT1949-1
C1
4.7µF
16V
GND
VC
1M
C3
10µF
6.3V
FB
SHDN
33.2k
1%
40.2k
330pF
C1, C2: TAIYO YUDEN EMK316BJ475ML
C3: TAIYO YUDEN JMK316BJ106ML
D1: MOTOROLA MBRM120LT3
L1, L2: SUMIDA CR32-100KC
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PACKAGE DESCRIPTIO
1949-1 TA02
Dimensions in inches (millimeters) unless otherwise noted.
MS8 Package
8-Lead Plastic MSOP
(LTC DWG # 05-08-1660)
0.118 ± 0.004*
(3.00 ± 0.102)
8
7 6
5
0.118 ± 0.004**
(3.00 ± 0.102)
0.193 ± 0.006
(4.90 ± 0.15)
1
0.040 ± 0.006
(1.02 ± 0.15)
0.007
(0.18)
2 3
4
0.034 ± 0.004
(0.86 ± 0.102)
0° – 6° TYP
0.021 ± 0.006
(0.53 ± 0.015)
SEATING
PLANE 0.012
(0.30)
0.0256
REF
(0.65)
BSC
0.006 ± 0.004
(0.15 ± 0.102)
MSOP (MS8) 1098
* DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
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LT1949-1
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TYPICAL APPLICATIO
Low Profile Triple Output LCD Bias Generator
D1
D3
D2
D4
23V
5mA
C7
0.1µF
C8
1µF
C9
0.1µF
C4
1µF
L1
4.7µH
VIN
3.3V
SW
VIN
SHUTDOWN
SHDN
R2
40.2k
LT1949-1
C1
4.7µF
C6
1µF
8V
200mA
FB
GND
VC
R1
30.1k
C3
330pF
C2
4.7µF
R3
7.5k
C1, C2, C5: TAIYO YUDEN LMK325BJ475MF
C4, C6, C8: TAIYO YUDEN EMK316BJ105MF
D1 TO D6: BAT-54S, DUAL DIODE
D7: MBRM120LT3
L1: SUMIDA CLQ4D10-4R7
D5
C5
4.7µF
D6
1949-1 TA02
–8V
10mA
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Linear Technology Corporation
19491i LT/TP 0600 4K • PRINTED IN THE USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com
 LINEAR TECHNOLOGY CORPORATION 2000