INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT253 Dual 4-input multiplexer; 3-state Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification Dual 4-input multiplexer; 3-state 74HC/HCT253 The 74HC/HCT253 have two identical 4-input multiplexers with 3-state outputs which select two bits from four sources selected by common data select inputs (S0, S1). When the individual output enable (1OE, 2OE) inputs of the 4-input multiplexers are HIGH, the outputs are forced to the high impedance OFF-state. The “253” is the logic implementation of a 2-pole, 4-position switch, where the position of the switch is determined by the logic levels applied to S0 and S1. FEATURES • Non-inverting data path • 3-state outputs for bus interface • and multiplex expansion • Common select inputs • Separate output enable inputs • Output capability: bus driver • ICC category: MSI The logic equations for the outputs are: 1Y = 1OE(1l0.S1.S0+1I1.S1.S0+1I2.S1.S0+1I3.S1.S0) 2Y = 2OE(2l0.S1.S0+2I1.S1.S0+2I2.S1.S0+2I3.S1.S0) GENERAL DESCRIPTION The 74HC/HCT253 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. APPLICATIONS • Data selectors • Data multiplexers QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC tPHL/ tPLH propagation delay CL = 15 pF; VCC = 5 V 1In, 2In to nY; 17 17 ns Sn to nY 18 19 ns 3.5 3.5 pF 55 55 pF CI input capacitance CPD power dissipation capacitance per multiplexer notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. December 1990 HCT 2 Philips Semiconductors Product specification Dual 4-input multiplexer; 3-state 74HC/HCT253 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1, 15 1OE, 2OE output enable inputs (active LOW) 14, 2 S 0, S1 common data select inputs 7, 9 1Y, 2Y 3-state multiplexer outputs 8 GND ground (0 V) 6, 5, 4, 3 1I0 to 1I3 data inputs from source 1 10, 11, 12, 13 2I0 to 2I3 data inputs from source 2 16 VCC positive supply voltage Fig.1 Pin configuration. December 1990 Fig.2 Logic symbol. 3 Fig.3 IEC logic symbol. Philips Semiconductors Product specification Dual 4-input multiplexer; 3-state 74HC/HCT253 Fig.4 Functional diagram. Fig.5 Logic diagram. FUNCTION TABLE SELECT INPUTS DATA INPUTS OUTPUT ENABLE OUTPUT nOE nY S0 S1 nI0 nI1 nI2 nI3 X X X X X X H Z L L H H L L L L L H X X X X L H X X X X X X X X L L L L L H L H L L H H H H H H X X X X X X X X L H X X X X L H L L L L L H L H NOTES 1. H = HIGH voltage level L = LOW voltage level X = don’t care Z = high impedance OFF-state December 1990 4 Philips Semiconductors Product specification Dual 4-input multiplexer; 3-state 74HC/HCT253 DC CHARACTERISTICS FOR 74HC For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: bus driver ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HC SYMBOL PARAMETER +25 −40 to +85 −40 to +125 UNIT VCC (V) WAVEFORMS min. typ. max. min. max. min. max. tPHL/ tPLH propagation delay 1In to nY; 2In to nY 55 20 16 175 35 30 220 44 37 265 53 45 ns 2.0 4.5 6.0 Fig.6 tPHL/ tPLH propagation delay Sn to nY 58 21 17 175 35 30 220 44 37 265 53 45 ns 2.0 4.5 6.0 Fig.6 tPZH/ tPZL 3-state output enable time nOE to nY 30 11 9 100 20 17 125 25 21 150 30 26 ns 2.0 4.5 6.0 Fig.7 tPHZ/ tPLZ 3-state output disable time nOE to nY 41 15 12 150 30 26 190 38 33 225 45 38 ns 2.0 4.5 6.0 Fig.7 tTHL/ tTLH output transition time 14 5 4 60 12 10 75 15 13 90 18 15 ns 2.0 4.5 6.0 Fig.6 December 1990 5 Philips Semiconductors Product specification Dual 4-input multiplexer; 3-state 74HC/HCT253 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: bus driver ICC category: MSI Note to HCT types The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT UNIT LOAD COEFFICIENT 1In 2In nOE S0 S1 0.40 0.40 1.10 1.10 1.10 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HCT SYMBOL PARAMETER +25 min. −40 to +85 −40 to +125 typ. max. min. max. min. max. UNIT V WAVEFORMS CC (V) tPHL/ tPLH propagation delay 1In to nY; 2In to nY 20 38 48 57 ns 4.5 Fig.6 tPHL/ tPLH propagation delay Sn to nY 22 40 50 60 ns 4.5 Fig.6 tPZH/ tPZL 3-state output enable time nOE to nY 14 30 38 45 ns 4.5 Fig.7 tPHZ/ tPLZ 3-state output disable time nOE to nY 13 30 38 45 ns 4.5 Fig.7 tTHL/ tTLH output transition time 5 12 15 18 ns 4.5 Fig.6 December 1990 6 Philips Semiconductors Product specification Dual 4-input multiplexer; 3-state 74HC/HCT253 AC WAVEFORMS (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.6 Waveforms showing the input (1In, 2In) to output (1Y, 2Y) propagation delays and the output transition times. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.7 Waveforms showing the 3-state enable and disable times. PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. December 1990 7