PHILIPS SA5224D

INTEGRATED CIRCUITS
SA5224
FDDI fiber optic postamplifier
Product specification
Replaces datasheet NE/SA5224 of 1995 Apr 26
IC19 Data Handbook
1998 Oct 07
Philips Semiconductors
Product specification
FDDI fiber optic postamplifier
SA5224
DESCRIPTION
PIN DESCRIPTION
The SA5224 is a high-gain limiting amplifier that is designed to
process signals from fiber optic preamplifiers. Capable of operating
at 125Mb/s, the chip is FDDI compatible and has input signal
level-detection with a user-adjustable threshold. The DATA and
LEVEL-DETECT outputs are differential for optimum noise margin
and ease of use. Also available is the SA5225 which is an ECL 10K
version of the SA5224.
D Package
FEATURES
CAZN
1
16
VSET
CAZP
2
15
VREF
GNDA
3
14
VCCE
DIN 4
13
DOUT
DIN 5
12
DOUT
6
11
GNDE
CF 7
10
ST
8
9
ST
VCCA
• Wideband operation: 1.0kHz to 120MHz typical
• Applicable in 155Mb/s OC3/SONET receivers
• Operation with single +5V or –5.2V supply
• Differential 100k ECL outputs
• Programmable input signal level-detection
• Fully differential for excellent PSRR to 1GHz
JAM
SD00374
Figure 1. Pin Configuration
APPLICATIONS
• FDDI
• Data communication in noisy industrial environments
• LANs
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
ORDER CODE
DWG #
–40 to +85°C
SA5224D
SOT109-1
16-Pin Plastic Small Outline (SO) package
BLOCK DIAGRAM
VCCA
(6)
DIN (4)
CAZP CAZN
(2)
(1)
VCCE
(16)
DIN (5)
(13) DOUT
ECL
BUFFER
LIMITING
AMPLIFIER
(12) DOUT
JAM
BUFFER
VREF(15)
(8) JAM
REFERENCE
(9) ST
LEVEL
DETECTOR
SD
BUFFER
(10) ST
VSET (16)
(3)
GNDA
(7)
CF
(11)
GNDE
SD00375
Figure 2. Block Diagram
1998 Oct 07
2
853-1594 20141
Philips Semiconductors
Product specification
FDDI fiber optic postamplifier
SA5224
PIN DESCRIPTIONS
PIN NO.
NAME
1
CAZN
Auto-zero capacitor pin. Connecting a capacitor between this pin and CAZP will cancel the offset voltage of the
limiting amplifier.
2
CAZP
Auto-zero capacitor pin. Connecting a capacitor between this pin and CAZN will cancel the offset voltage of the
limiting amplifier.
3
GNDA
Analog GND pin. Connect to ground for +5V upshifted ECL operation. Connect to –5.2V for standard ECL
operation. Must be at same potential as GNDE (Pin 11).
4
DIN
Differential input. DC bias level is set internally at approximately 2.9V. Complimentary to DIN (Pin 5).
5
DIN
Differential input. DC bias level is set internally at approximately 2.9V. Complimentary to DIN (Pin 4).
6
VCCA
7
CF
8
JAM
9
FUNCTION
Analog power supply pin. Connect to a +5V supply for upshifted ECL operation. Connect to ground for standard
ECL operation. Must be at same potential as VCCE (Pin 14).
Filter capacitor for level detector. Capacitor should be connected between this pin and VCCA.
This ECL-compatible input controls the output buffers DOUT and DOUT (Pins 12 and 13). When an ECL LOW signal
is applied, the outputs will follow the input signal. When an ECL HIGH signal is applied, the DOUT and DOUT pins
will latch into LOW and HIGH states, respectively. When left unconnected, this pin is actively pulled-low (JAM OFF).
ST
Input signal level-detect STATUS. This ECL output is high when the input signal is below the user programmable
threshold level.
10
ST
ECL compliment of ST (Pin 9).
11
GNDE
12
DOUT
Digital GND pin. Connect to ground for +5V upshifted ECL operation. Connect to a negative supply for normal ECL
operation. Must be at the same potential as GNDA (Pin 3).
ECL-compatible output. Nominal level is VCCE–1.3V. When JAM is HIGH, this pin will be forced into an ECL HIGH
condition. Complimentary to DOUT (Pin 13).
13
DOUT
ECL-compatible output. Nominal level is VCCE–1.3V. When JAM is HIGH, this pin will be forced into an ECL LOW
condition. Complimentary to DOUT (Pin 12).
14
VCCE
Digital power supply pin. Connect to a +5V supply for upshifted ECL operation. Connect to ground during normal
ECL operation. Must be at the same potential as VCCA (Pin 6).
15
VREF
Reference voltage for threshold level voltage divider. Nominal value is approximately 2.64V.
16
VSET
Input threshold level setting circuit. This input can come from a voltage divider between VREF and GNDA.
ABSOLUTE MAXIMUM RATINGS
SYMBOL
VCC
PARAMETER
RATING
UNITS
6
V
Power supply (VCC - GND)
TA
Operating ambient
–45 to +85
°C
TJ
Operating junction
–55 to +150
°C
Storage
–65 to +150
°C
1100
mW
TSTG
PD
Power dissipation, TA = 25°C (still air)1
16-pin Plastic SO
NOTE:
1. Maximum dissipation is determined by the ambient temperature and the thermal resistance,
θJA: 16-pin SO: θJA = 110°C/W
RECOMMENDED OPERATING CONDITIONS
SYMBOL
VCC
PARAMETER
RATING
Supply voltage
4.5 to 5.5
TA
Ambient temperature ranges
–40 to +85
TJ
Junction temperature ranges
–40 to +110
1998 Oct 07
3
UNITS
V
°C
°C
Philips Semiconductors
Product specification
FDDI fiber optic postamplifier
SA5224
DC ELECTRICAL CHARACTERISTICS
Min and Max limits apply over operating temperature at VCC = 5V ±10%, unless otherwise specified. Typical data apply at TA = 25°C and VCC =
+5V.
SYMBOL
PARAMETER
VIN
Input signal voltage
single-ended
differential
VOS
VN
VTH
VHYS
SA5224
Min
Typ
UNIT
VP-P
Input offset voltage2
50
µV
Input RMS noise2
60
µV
12
mVP-P
Input level-detect programmability
single-ended
Level-detect hysteresis
VCCA + VCCE supply current
IINL
JAM input current
VIN = 200kHz square
wave
2
4
No ECL loading
Pin 8 = 0V
5
6
dB
27
35
mA
10
µA
–0.880
VDC
–10
high1
VOHMAX
Maximum logic
VOHMIN
Minimum logic high1
VOLMAX
Maximum logic low1
VOLMIN
low1
Minimum logic
.002
.004
Max
1.5
3.0
ICC
VIH
TEST CONDITIONS
–1.055
VDC
–1.620
–1.870
Minimum input for JAM = high1
VDC
VDC
–1.165
VDC
VIL
Maximum input for JAM = low1
NOTES:
1. These ECL specifications are referenced to the VCCE rail and apply for TA = 0°C to 85°C.
2. Guaranteed by design.
–1.490
VDC
UNIT
AC ELECTRICAL CHARACTERISTICS
Typical data apply at TA = 25°C and VCC = +5V. Min and Max limits apply for 4.5 ≤ VCC ≤ 5.5V.
SYMBOL
PARAMETER
BW1
Lower –3dB bandwidth
BW2
Upper –3dB bandwidth
RIN
Input resistance
CIN
Input capacitance
tr, tf
ECL output3
TEST CONDITIONS
Min
Typ
Max
CAZ = 0.1µF
0.5
1.0
1.5
kHz
90
120
150
MHz
2.9
4.5
7.6
kΩ
2.5
pF
2.2
ns
Pin 4 or 5
risetime,
falltime
tPWD
Pulsewidth distortion
RAZ
Auto zero output resistance
RF
Level-detect filter resistance
tLD
Level-detect time constant
Pin 4 or 5
RL = 50Ω
To VCCE - 2V
20-80%
1.2
Pin 1 or 2
155
250
0.3
nsP-P
423
kΩ
Pin 7
14
24
41
kΩ
CF = 0
0.5
1.0
2.0
µs
NOTES:
1. Both outputs should be terminated identically to minimize differential feedback to the device inputs on a PC board or substrate.
1998 Oct 07
4
Philips Semiconductors
Product specification
FDDI fiber optic postamplifier
NE5212
SA5224
ECL data outputs if the input is below a set threshold. This prevents
the outputs from reacting to noise in the absence of a valid input
signal, and insures that data will only be transmitted when the input
signal-to-noise ratio is sufficient for low bit-error-rate system
operation. Complimentary ECL flags (ST and STB) indicate whether
the input signal is above or below the desired threshold level.
CLOCK
RECOVERY
&
RETIMING
NE5224
SD00376
Figure 6 shows a simplified block diagram of the SA5224
level-detect system. The input signal is amplified and rectified
before being compared to a programmable reference. A filter is
included to prevent noise spikes from triggering the level-detector.
This filter has a nominal 1µs time constant, and additional filtering
can be achieved by using an external capacitor (CF) from Pin 7 to
VCCA (the internal driving impedance is nominally 24k). The
resultant signal is then compared to a programmable level, VSET,
which is set by an internal voltage reference (2.64V) and an external
resistor divider (R1 and R2). The value of R1 + R2 should be
maintained at approximately 5k.
Figure 3. Typical Fiber Optic Receiving System
INPUT BIASING
The DATA INPUT pins (4 and 5) are DC biased at approximately
2.9V by an internal reference generator. The SA5224 can be DC
coupled, but the driving source must operate within the allowable
1.4V to 4.4V input signal range (for VCC = 5V). If AC coupling is
used to remove any DC compatibility requirement, the coupling
capacitors C1 and C2 must be large enough to pass the lowest input
frequency of interest. For example, .001µF coupling capacitors
react with the internal 4.5k input bias resistors to yield a lower –3dB
frequency of 35kHz. This then sets a limit on the maximum number
of consecutive “1”s or “0”s that can be sensed accurately at the
system data rate. Capacitor tolerance and resistor variation (2.9k to
7.6k) must be included for an accurate calculation.
HYST
VTL
(OFF)
VTH
(ON)
SD00377
Figure 4.
The circuit is designed to operate accurately over a differential
2-12mVP-P square-wave input level detect range. This level,
VSET/100, is the average of VTH and VTL.
AUTO-ZERO CIRCUIT
Figure 5 also shows the essential details of the auto-zero circuit. A
feedback amplifier (A4) is used to cancel the offset voltage of the
forward signal path, so the input to the internal ECL comparator (A6)
is at its toggle point in the absence of any input signal. The time
constant of the cancelling circuitry is set by an external capacitor
(CAZ) connected between Pins 1 and 2. The formula for the lower
–3dB frequency is:
150
f 3dB 2 R AZ C AZ
Nominal hysteresis of 5dB is provided by the complimentary ECL
V SET
V SET
V
V
139 and TH
78 . For
output comparator yielding TL
example, with VSET = 1.2V, a 15.4mVP-P square-wave differential
input will drive the ST pin high, and an input level below 8.6mVP-P
will drive the ST pin low.
Since a “JAM” function is provided (Pin 8) and can force the data
outputs to a predetermined state (DOUT = LOW, DOUT = HIGH), the
ST and JAM pins can be connected together to automatically
disable signal transmission when the chip senses that the input
signal is below the desired threshold. JAM (Pin 8) low enables the
Data Outputs. ST will be in a high ECL state for input signals below
threshold.
where RAZ is the internal driving impedance which can vary from
155k to 423k over temperature and device fabrication limits. The
input coupling time constant must also be considered in determining
the lower frequency response of the SA5224.
INPUT SIGNAL LEVEL-DETECTION
The SA5224 allows for user programmable input signal
level-detection and can automatically disable the switching of its
CAZ
RAZ
250kΩ
RAZ
250kΩ
VBIAS
A4
RIN
RIN
4.5kΩ
4.5kΩ
C1
DOUT
–
DIN
DATA IN
C2
A1
+
A3
DINB
A6
ECL 100k
DATA OUT
DOUTB
SD00378
Figure 5. SA5224 Forward Gain Path Including Auto-Zero
1998 Oct 07
5
Philips Semiconductors
Product specification
FDDI fiber optic postamplifier
SA5224
VCCA
CF
LOW-PASS
FILTER
50X
DATA IN
2.64V
+
ST
–
ST
VREF
R1
ECL 100k
LEVELDETECT
FLAGS
.25X
R2
SD00379
Figure 6. SA5224 Input Signal Level-Detect System
1
CAZN
VSET
16
2
CAZP
VREF
15
3
GNDA
VCCE
14
4
DIN
DOUT
13
CAZ
0.1µF
R1
R2
5V
0.1µF
CIN1
0.1µF
DATA IN
DATA OUT
CIN2
0.1µF
5V
0.1µF
R3
50Ω
R4
5
DIN
DOUT
12
6
VCCA
GNDE
11
7
CF
ST
10
3V
50Ω
0.1µF
R5
50Ω
8
JAM
ST
LEVEL-DETECT
STATUS
9
SD00380
Figure 7. Application with VCC = 5.0V
All die are 100% functional with various parametrics tested at the
wafer level, at room temperature only (25°C), and are guaranteed to
be 100% functional as a result of electrical testing to the point of
wafer sawing only. Although the most modern processes are
utilized for wafer sawing and die pick and place into waffle pack
carriers, it is impossible to guarantee 100% functionality through this
process. There is no post waffle pack testing performed on
individual die.
NOTE: A 50Ω resistor is required from Pin 9 to 3V only if the ST pin
is required to meet 100k ECL specifications.
Die Sales Disclaimer
Due to the limitations in testing high frequency and other parameters
at the die level, and the fact that die electrical characteristics may
shift after packaging, die electrical parameters are not specified and
die are not guaranteed to meet electrical characteristics (including
temperature range) as noted in this data sheet which is intended
only to specify electrical characteristics for a packaged device.
1998 Oct 07
6
Philips Semiconductors
Product specification
FDDI fiber optic postamplifier
SA5224
Although Philips Semiconductors typically realizes a yield of 85%
after assembling die into their respective packages, with care
customers should achieve a similar yield. However, for the reasons
stated above, Philips Semiconductors cannot guarantee this or any
other yield on any die sales.
Since Philips Semiconductors has no control of third party
procedures in the handling or packaging of die, Philips
Semiconductors assumes no liability for device functionality or
performance of the die or systems on any die sales.
CAZN
VSET
CAZP
VREF
1
2
GNDA
DIN
DIN
VCCA
16
15
3
ÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈ
ÈÈÈÈÈÈÈ
4
5
6
14
VCCE
13
DOUT
12
DOUT
11
7
8
9
GNDE
10
ST
CF
JAM
ST
ECN No.: 01673
1991 Feb 8
SD00492
Figure 8. SA5224 Bonding Diagram
1998 Oct 07
7
Philips Semiconductors
Product specification
FDDI fiber optic postamplifier
SA5224
SO16: plastic small outline package; 16 leads; body width 3.9 mm
1998 Oct 07
8
SOT109-1
Philips Semiconductors
Product specification
FDDI fiber optic postamplifier
SA5224
NOTES
1998 Oct 07
9
Philips Semiconductors
Product specification
FDDI fiber optic postamplifier
SA5224
Data sheet status
Data sheet
status
Product
status
Definition [1]
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
 Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Date of release: 10-98
Document order number:
1998 Oct 07
10
9397 750 04628