PHILIPS SC26C562C1A

INTEGRATED CIRCUITS
SC26C562
CMOS dual universal serial
communications controller (CDUSCC)
Product specification
Supersedes data of 1995 May 01
IC19 Data Handbook
1998 Sep 04
Philips Semiconductors
Product specification
CMOS dual universal serial communications controller
(CDUSCC)
SC26C562
• Watchdog timer
• 0 to 10 Mbit/sec data rate
• Programmable bit rate for each receiver and transmitter selectable
DESCRIPTION
The Philips Semiconductors SC26C562 Dual Universal Serial
Communications Controller (CDUSCC) is a single-chip CMOS-LSI
communications device that provides two independent,
multi-protocol, full-duplex receiver/transmitter channels in a single
package. It supports bit-oriented and character-oriented (byte count
and byte control) synchronous data link controls as well as
asynchronous protocols. The SC26C562 interfaces to synchronous
bus MPUs and is capable of program-polled, interrupt driven,
block-move or DMA data transfers.
from:
– 19 fixed rates: 50 to 64K baud
– One user-defined rate derived from programmable
counter/timer
– External 1X or 16X clock
– Digital phase-locked loop
The SC26C562 (CDUSCC) is (PIN) hardware and (REGISTER)
software compatible with the existing SCN26562 (DUSCC).
CDUSCC will automatically configure to the NMOS DUSCC register
map (default mode) on power up.
• Parity and FCS (frame check sequence LRC or CRC) generation
and checking
• Programmable data encoding/decoding: NRZ, NRZI, FM0, FM1,
The operating mode and data format of each channel can be
programmed independently. Each channel consists of a receiver, a
transmitter, a 16-bit multifunction counter/timer, a digital
phase-locked loop (DPLL), a parity/CRC generator and checker, and
associated control circuits. The two channels share a common bit
rate generator (BRG), operating directly from a crystal or an external
clock, which provides sixteen common bit rates simultaneously. The
operating rate for the receiver and transmitter of each channel can
be independently selected from the BRG, the DPLL, the
counter/timer, or from an external 1X or 16X clock, making the
CDUSCC well-suited for dual-speed channel applications. Data
rates up to 10Mbits per second are supported.
Manchester
• Programmable channel mode: full- or half-duplex, auto-echo, or
local loopback
• Programmable data transfer mode: polled, interrupt, DMA, wait
• DMA interface
– Compatible with Synchronous and Asynchronous bus DMA
controllers
– Half- or full-duplex operation
– Single or dual address data transfers
– Automatic frame termination on counter/ timer terminal count or
DMA DONE (EOPN)
The transmitter and receiver each contain a sixteen-deep FIFO with
appended transmitter command and receiver status bits and a shift
register. This permits reading and writing of up to sixteen characters
at a time, minimizing the potential of receiver overrun or transmitter
underrun, and reducing interrupt or DMA overhead. In addition, a
flow control capability is provided to disable a remote transmitter
when the FIFO of the local receiving device is full.
• Transmit path clear status
• High speed data bus interface: 160ns bus cycle
• DPLL operation up to 312.5kHz with internal clock
• Interrupt capabilities
Two modem control inputs (DCD and CTS) and three modem
control outputs (RTS and two general purpose) are provided.
Because the modem control inputs and outputs are general purpose
in nature, they can be optionally programmed for other functions.
– Vector output (fixed or modified by status)
– Individual interrupt enable bits
– Programmable internal priorities
– Maskable interrupt conditions
The SC26C562 CDUSCC is optimized to interface with processors
using a synchronous bus interface, such as the 8086, and iAPX86
family. For systems using an asynchronous bus, such as the 68000
and 68010, refer to the SC68C562 documentation.
– 80XX/X compatible
• Multi-function programmable 16-bit counter/timer
– Bit rate generator
– Event counter
Refer to the CMOS Dual Universal Serial Communication Controller
(CDUSCC) User’s Manual for a complete operational description.
– Count received or transmitted characters
– Delay generator
– Automatic bit length measurement
FEATURES
General Features
• Modem controls
– RTS, CTS, DCD, and up to four general purpose I/O pins per
channel
• Dual full-duplex synchronous/ asynchronous receiver and
transmitter
– CTS and DCD programmable auto-enables for Tx and Rx
• Multi-protocol operation
– Programmable interrupt on change of CTS or DCD
• On-chip oscillator for crystal
• TTL compatible
• Single +5V power supply
– BOP: HDLC/ADCCP, SDLC, SDLC loop, X.25 or X.75 link level,
etc.
– COP: Single SYNC, dual SYNC, BiSYNC, DDCMP
– ASYNC: 5-8 bits plus optional parity
• Sixteen character receive and transmit FIFOs with interrupt
Asynchronous Mode Features
threshold control
• Character length:
• FIFO’ed status bits
1998 Sep 04
2
5 to 8 bits
853-1663 19973
Philips Semiconductors
Product specification
CMOS dual universal serial communications controller
(CDUSCC)
• Odd or even parity, no parity, or force parity
• Up to two stop bits programmable in 1/16-bit increments
• 1X or 16X Rx and Tx clock factors
• Parity, overrun and framing error detection
• False start bit detection
• Break generation with handshake for counting break characters
• Detection of start and end of received break
• Character compare with optional interrupt on match
• Transmit and receive up to 10Mbps at 1x or 1Mbps at 16x data
SC26C562
• Short frame rejection for receiver
• Detection and notification of received end of message
• CRC generation and checking
• SDLC loop mode capability
Character-Oriented Protocols
• Character length: 5 to 8 bits
• Odd or even parity, no parity, or force parity
• LRC or CRC generation and checking
• Optional opening PAD transmission
• One or two SYN characters
• External sync capability
• SYN detection and optional stripping
• SYN or MARK line-fill or underrun
• Idle in MARK or SYNs
• Parity, FCS, overrun and underrun error detection
• Optional SYNC exclusion from FCS
• BISYNC features
rates
Bit-Oriented Protocol
• Character length: 5 to 8 bits
• Detection and transmission of residual character: 0–7 bits
• Automatic switch to programmed character length for I field
• Zero insertion and deletion
• Optional opening PAD transmission
• Detection and generation of FLAG, ABORT, and IDLE bit patterns
• Transmit 7 or 8 bit ABORT
• Detection and generation of shared (single) FLAG between
– EBCDIC or ASCII header, text and control messages
– SYN, DLE stripping
– EOM (end of message) detection and transmission
frames
• Detection of overlapping (shared zero) FLAGs
• Idle in MARK or FLAGs
• Secondary address recognition including group and global
– Auto transparency mode switching
– Auto hunt after receipt of EOM sequence (with closing PAD
check after EOT or NAK)
– Control character sequence detection for both transparent and
normal text
address
– Parity generation for data and LRC characters
• Single- or dual-octet secondary address
• Extended address and control fields
ORDERING INFORMATION
COMMERCIAL
INDUSTRIAL
Serial Data Rate =
10Mbps Maximum
Serial Data Rate =
8Mbps Maximum
DWG #
48-Pin Plastic Dual In-Line Package (DIP)
SC26C562C1N
Not available
SOT240-1
52-Pin Plastic Leaded Chip Carrier (PLCC) Package
SC26C562C1A
SC26C562A8A
SOT238-3
DESCRIPTION
ABSOLUTE MAXIMUM RATINGS1
SYMBOL
PARAMETER
RATING
UNIT
COMMERCIAL
INDUSTRIAL
0 to +70
-40 to +85
°C
TA
Operating ambient temperature2
TSTG
Storage temperature
-65 to +150
-65 to +150
°C
VCC
Voltage from VCC to GND3
–0.5 to +7.0
–0.5 to +7.0
V
VS
Voltage from any pin to ground3
–0.5 to VCC +0.5
–0.5 to VCC +0.5
V
1998 Sep 04
3
Philips Semiconductors
Product specification
CMOS dual universal serial communications controller
(CDUSCC)
SC26C562
PIN CONFIGURATIONS
N PACKAGE
IACKN
1
48 VCC
A3
2
47
A4
A2
3
46
A5
A1
4
45
A6
RTxDAKBN/
GPI1BN
5
44
RTxDAKAN/
GPI1AN
IRQN
6
43
X1/CLK
42
X2
8
41
RTSAN/
SYNOUTAN
TRxCB
9
40
TRxCA
RTxCB 10
39
RTxCA
38
46
34
20
33
DCDAN/
SYNIAN
TOP VIEW
PIN FUNCTION
1
2
3
4
5
37
RxDA
36
TxDA
14
35
15
34
16
33
TxDAKAN/
GPI2AN
RTxDRQAN/
GPO1AN
TxDRQAN/
GPO2AN/RTSAN
17
32
CTSAN/LCAN
D7 18
31
D0
D6 19
30
D1
D5 20
29
D2
D4 21
28
D3
18
RDN 22
27
EOPN
RESETN 23
26
WRN
GND 24
25
CEN
19
20
21
22
23
24
25
26
TxDAKBN/
GPI2BN
RTxDRQBN/
GPO1BN
TxDRQBN/
GPO2BN/RTSBN
CTSBN/LCBN
47
21
7
TxDB 13
1
PLCC
RDYN
DIP
7
8
RTSBN/
SYNOUTBN
DCDBN/ 11
SYNIBN
RxDB 12
A PACKAGE
INDEX
CORNER
6
7
8
9
10
11
12
13
14
15
16
17
IACKN
A3
A2
A1
RTxDAKBN/
GPI1BN
IRQN
NC
RDYN
RTSBN/
SYNOUTBN
TRxCB
RTxCB
DCDBN/
SYNIBN
NC
RxDB
TxDB
TxDAKBN/
GPI2BN
RTxDRQBN/
GPO1BN
TxDRQBN/
GPO2BN/RTSBN
CTSBN/LCBN
D7
D6
D5
D4
RDN
RESETN
GND
PIN FUNCTION
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
CEN
WRN
EOPN
D3
D2
D1
D0
NC
CTSAN/LCAN
TxDRQAN/
GPO2AN/RTSAN
RTxDRQAN/
GPO1AN
TxDAKAN/
GPI2AN
TxDA
RxDA
NC
DCDAN/
SYNIAN
RTxCA
TRxCA
RTSAN/
SYNOUTAN
X2
X1/CLK
RTxDAKAN/
GPI1AN
A6
A5
A4
VCC
SD00203
Figure 1. Pin Configurations
1998 Sep 04
4
Philips Semiconductors
Product specification
CMOS dual universal serial communications controller
(CDUSCC)
SC26C562
BLOCK DIAGRAM
CHANNEL
MODE AND
TIMING A/B
DPLL CLK
MUX A/B
D0–D7
BUS
BUFFER
DPLLA/B
BRG
A7 CONTROL
LOGIC
A7
INTERFACE/
OPERATION
CONTROL
COUNTER
TIMER A/B
ADDRESS
DECODE
C/T CLK
MUX A/B
CTCRA/B
R/W
DECODE
RDYN
CTPRLA/B
WRN
RDN
A1–A6
CTPRHA/B
CTHA/B
DMA
CONTROL
MPU
INTERFACE
CEN
CCRA/B
RESETN
PCRA/B
CTLA/B
TRANSMIT
A/B
INTERNAL BUS
RSRA/B
TRSRA/B
ICTSRA/B
GSR
RTxDRQAN/GPO1AN
CMR1A/B
RTxDRQBN/GPO1BN
CMR2A/B
TxDRQAN/GPO2AN
TxDRQBN/GPO2BN
RTxDAKAN/GPI1AN
OMRA/B
DMA
INTERFACE
TRCR A/B
TRMR A/B
TxDAKAN/GPI2AN
CONTROL
RTxCA/B
DCDBN/SYNIBN
TxD A/B
CRC
GENERATOR
SPEC CHAR
GEN LOGIC
RECEIVER
A/B
CTSAN/LCAN
CTSBN/LCBN
TX SHIFT
REG
TELR
A/B
CID
TxDAKBN/GPI2BN
EOPN
TRxCA/B
TPRA/B
TTRA/B
TRANSMIT
16 DEEP
FIFO
FTLR A/B
RTxDAKBN/GPI1BN
TRANS CLK
MUX
SPECIAL
FUNCTION
PINS
RCVR CLK
MUX
DCDAN/SYNIAN
RPRA/B
RTSBN/SYNOUTBN
RTRA/B
RTSAN/SYNOUTAN
S1RA/B
S2RA/B
INTERRUPT
CONTROL
RCVR
SHIFT REG
ICRA/B
IRQN
IACKN
IVRM
IER1 A/B
RFLR
A/B
IER2 A/B
IER3 A/B
CDUSCC
LOGIC
CRC
ACCUM
BISYNC
COMPARE
LOGIC
X1/CLK
X2
RxD A/B
RECEIVER
16 DEEP
FIFO
IERA/B
OSCILLATOR
SD00239
Figure 2. Block Diagram
1998 Sep 04
5
Philips Semiconductors
Product specification
CMOS dual universal serial communications controller
(CDUSCC)
SC26C562
PIN DESCRIPTION
MNEMONIC
PIN NO.
TYPE
NAME AND FUNCTION
4-2,
51-49
I
Address Lines: Active-high. Address inputs which specify which of the internal registers
is accessed for read/write operation.
31-28,
21-18
33-30,
23-20
I/O
Bidirectional Data Bus: Active-high, 3-State. Bit 0 is the LSB and bit 7 is the MSB. All
data, command and status transfers between the CPU and the CDUSCC take place over
this bus. The data bus is enabled when CSN and RDN, or CSN and WRRN are low during
interrupt acknowledge cycles and single address DMA acknowledge cycles.
RDN
22
24
I
Read Strobe: Active-low input. When active and CSN is also active, causes the content
of the addressed register to be present on the data bus. RDN is ignored unless CSN is
active.
WRN
26
28
I
Write Strobe: Active-low input. When active and CSN is also active, the content of the
data bus is loaded into the addressed register. The transfer occurs on the rising edge of
WRN. WRN is ignored unless CEN is active.
CSN
25
27
I
Chip Select: Active-low input. When active, data transfers between the CPU and the
CDUSCC are enabled on D0–D7 as controlled by RDN or WRN and A1–A6 inputs. When
CSN is high, the data lines are placed in the 3-State condition (except during interrupt
acknowledge cycles and single address DMA transfers).
RDYN
7
8
O
Ready: Active-low, open drain. Used to synchronize data transfers between the CPU and
the CDUSCC. It is valid only during read and write cycles where the CDUSCC is
configured in ‘wait on Rx’, ‘wait on Tx’ or ‘wait on Tx or Rx’ modes, otherwise it is always
inactive. RDYN becomes active on the leading edge of RDN and WRN if the requested
operation cannot be performed (viz, no data in RxFIFO in the case of a read or no room in
the TxFIFO in the case of a write).
IRQN
6
6
O
Interrupt Request: Active-low, open-drain. This output is asserted upon occurrence of
any enabled interrupting condition. The CPU can read the general status register to
determine the interrupting condition(s), or can respond with an interrupt acknowledge cycle
to cause the CDUSCC to output an interrupt vector on the data bus.
IACKN
1
1
I
Interrupt Acknowledge: Active-low. When IACKN is asserted, the CDUSCC responds
by either forcing the bus into high-impedance, placing a vector number, call instruction or
zero on the data bus. The vector number can be modified or unmodified by the status. If
no interrupt is pending, IACKN is ignored and the data bus placed in high-impedance.
X1/CLK
43
47
I
Crystal or External Clock: When using the crystal oscillator, the crystal is connected
between pins X1 and X2. If a crystal is not used, an external clock is supplied at this input.
This clock is used to drive the internal bit rate generator, as an optional input to the
counter/timer or DPLL, and to provide other required clocking signals. When a crystal is
used, a capacitor must be connected from this pin to ground.
X2
42
46
O
Crystal 2: Connection for other side of crystal. When a crystal is used, a capacitor must
be connected from this pin to ground. If an external clock is used on X1, this pin should be
left floating.
RESETN
23
25
I
Master Reset: Active-low. A low on this pin resets the transmitters and receivers and
resets the registers shown in Table 1 of the CDUSCC Users’ Guide. Reset is
asynchronous, i.e., no clock is required.
RxDA, RxDB
37, 12
40, 14
I
Channel A (B) Receiver Serial Data Input: The least significant bit is received first. If
external receiver clock is specified for the channel, the input is sampled on the rising edge
of the clock.
TxDA, TxDB
36, 13
39, 15
O
Channel A (B) Transmitter Serial Data Output: The least significant bit is transmitted
first. This output is in the marking (high) condition when the transmitter is disabled or when
the channel is operating in local loopback mode. If external transmitter clock is specified
for the channel, the data is shifted on the falling edge of the clock.
RTxCA, RTxCB
39, 10
43, 11
I/O
Channel A (B) Receiver/Transmitter Clock: As an input, it can be programmed to
supply the receiver, transmitter, counter/timer, or DPLL clock. As an output, it can supply
the counter/timer output, the transmitter shift clock (1X), or the receiver sampling clock
(1X).
TRxCA, TRxCB
40, 9
44, 10
I/O
Channel A (B) Transmitter/Receiver Clock: As an input, it can supply the receiver,
transmitter, counter/timer, or DPLL clock. As an output, it can supply the counter/timer
output, the DPLL output, the transmitter shift clock (1X), the receiver sampling clock (1X),
the transmitter BRG clock (16X), The receiver BRG clock (16X), or the internal system
clock (X1 ÷ 2).
DIP
PLCC
A1–A6
4-2,
47-45
D0–D7
1998 Sep 04
6
Philips Semiconductors
Product specification
CMOS dual universal serial communications controller
(CDUSCC)
SC26C562
PIN DESCRIPTION (Continued)
MNEMONIC
CTSA/BN,
LCA/BN
DCDA/BN,
SYNIA/BN
RTxDRQA/BN,
GPO1A/BN
TxDRQA/BN,
GPO2A/BN,
RTSA/BN
RTxDAKA/BN,
GPI1A/BN
TxDAKA/BN,
GPI2A/BN
PIN NO.
DIP
32, 17
38, 11
34, 15
33, 16
44, 5
35, 14
PLCC
35, 19
42, 12
37, 17
36, 18
48, 5
38, 16
TYPE
NAME AND FUNCTION
I/O
Channel A (B) Clear-to-Send Input or Loop Control Output: Active-low. The signal
can be programmed to act as an enable for the transmitter when not in loop mode. The
CDUSCC detects logic level transitions on this input and can be programmed to generate
an interrupt when a transition occurs. When operating in the BOP loop mode, this pin becomes a loop control output which is asserted and negated by CDUSCC commands. This
output provides the means of controlling external loop interface hardware to go on-line and
off-line without disturbing operation of the loop.
I
Channel A (B) Data Carrier Detected or External Sync Input: The function of this pin is
programmable. As a DCD active-low input, it acts as an enable for the receiver or can be
used as a general purpose input. For the DCD function, the CDUSCC detects logic level
transitions on this pin and can be programmed to generate an interrupt when a transition
occurs. As an active-low external sync input, it is used in COP mode to obtain character
synchronization for the receiver without receipt of a SYN character. This mode can be
used in disc or tape controller applications or for the optional byte timing lead in X.21.
O
Channel A (B) Receiver/Transmitter DMA Service Request or General Purpose
Output: Active-low. For half-duplex DMA operation, this output indicates to the DMA
controller that one or more characters are available in the receiver FIFO (when the
receiver is enabled) or that the transmit FIFO is not full (when the transmitter is enabled).
For full-duplex DMA operation, this output indicates to the DMA controller that data is
available in the receiver FIFO. In non-DMA mode, this pin is a general purpose output that
can be asserted and negated under program control.
O
Channel A (B) Transmitter DMA Service Request, General Purpose Output, or
Request-to-Send: Active-low. For full-duplex DMA operation, this output indicates to the
DMA controller that the transmit FIFO is not full and can accept more data. When not in
full-duplex DMA mode, this pin can be programmed as a general purpose or a
Request-to-Send output, which can be asserted and negated under program control.
I
Channel A (B) Receiver/Transmitter DMA Acknowledge or General Purpose Input:
Active-low. For half-duplex single address operation, this input indicates to the CDUSCC
that the DMA controller has acquired the bus and that the requested bus cycle (read
receiver FIFO when the receiver is enabled or load transmitter FIFO when the transmitter
is enabled) is beginning. For full-duplex single address DMA operation, this input indicates
to the CDUSCC that the DMA controller has acquired the bus and that the requested read
receiver FIFO bus cycle is beginning. Because the state of this input can be read under
program control, it can be used as a general purpose input when not in single address
DMA mode.
I
Channel A (B) Transmitter DMA Acknowledge or General Purpose Input: Active-low.
When the channel is programmed for full-duplex single address DMA operation, this input
is asserted to indicate to the CDUSCC that the DMA controller has acquired the bus and
that the requested load transmitter FIFO bus cycle is beginning. Because the state of this
input can be read under program control, it can be used as a general purpose input when
not in full-duplex single address DMA mode.
27
29
I/O
Done (EOP): Active-low, open-drain. EOPN can be used and is active in both DMA and
non-DMA modes. As an input, EOPN indicates the last DMA transfer cycle to the TxFIFO.
As an output, EOPN indicates either the last DMA transfer from the RxFIFO or that the
transmitted character count has reached terminal count.
41, 8
45, 9
O
Channel A (B) Sync Detect or Request-to-Send: Active-low. If programmed as a sync
output, it is asserted one bit time after the specified sync character (COP or BISYNC
modes) or a FLAG (BOP modes) is detected by the receiver. As a Request-to-Send
modem control signal, it functions as described previously for the TxDRQN/RTSN pin.
VCC
48
34, 52
I
+5V Power Input
GND
24
26, 13,
41, 7
I
Signal and Power Ground Input
EOPN
RTSA/BN,
SYNOUTA/BN
1998 Sep 04
7
Philips Semiconductors
Product specification
CMOS dual universal serial communications controller
(CDUSCC)
SC26C562
DC ELECTRICAL CHARACTERISTICS4,5 TA = 0°C to +70°C, VCC = 5.0V +10%4,5
SYMBOL
VIL
VIH
PARAMETER
Input low voltage:
All except X1/CLK
X1/CLK
Input high voltage except X1/CLK
TEST CONDITIONS
VOH
Output low voltage:
All except IRQN7
IRQN
Output high voltage:
(Except open drain outputs)
Min
0 to 70C
–40 to +85C
2.0
2.3
0.8 x VCC
IOH = –400µA
0.5
0.5
VCC–0.5
X1/CLK input low current10
X1/CLK input high current10
ISCX2
X2 short circuit current
IIL
Input low current
RESETN, TxDAKN, RxDAKN
II
Input leakage current
IOZH
Output off current high, 3-State data bus
VIN = VCC, 0 to 70C
–40 to +85C
IOZL
Output off current low, 3-State data bus
VIN = 0, 0 to 70C
–40 to +85C
–1
–10
IODL
Open drain output low current in off
state:
EOPN, RDYN
IRQN
Open drain output high current in off
state:
EOPN, IRQN, RDYN
VIN = 0
–15
–1
VIN = VCC
–1
ICC13
CIN
COUT
CI/O
Power supply current
(see Figure 19 for graphs)
capacitance9
Input
Output capacitance9
Input/output capacitance9
Max
VCC
IOL=5.3mA(Comm), 4.8mA(Ind)
IOL=8.8mA(Comm), 7.8mA(Ind)
IILX1
IIHX1
IODH
Typ
0.8
0.8
X1/CLK
VOL
LIMITS
VIN = 0, X2 = open
VIN = VCC, X2 = GND
VIN = 0 to VCC, 0 to 70C
–40 to +85C
0 to 70C
–40 to +85C
VCC = GND = 0
VCC = GND = 0
VCC = GND = 0
V
V
V
V
V
V
V
V
–150
X1 = open, VIN = 0
VIN = VCC
VIN = 0
UNIT
–15
–1
–10
0.0
150
µA
µA
–15
+15
mA
mA
–0.5
µA
+1
+10
µA
+1
+10
µA
µA
25
–0.5
µA
µA
1
µA
80
95
mA
10
15
20
pF
pF
pF
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not
implied.
2. Clock may be stopped (DC) for testing purposes, or when CDUSCC is in non-operational modes.
3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.
4. Parameters are valid over specified temperature range.
5. All voltage measurements are referenced to ground (GND). For testing, all inputs except X1/CLK swing between 0.2V and 3.0V with a transition time of 20ns maximum. For X1/CLK, this swing is between 0.2V and 4.4V. All time measurements are referenced at input voltages of
0.2V and 3.0V and output voltages of 0.8V and 2.0V, as appropriate.
6. See Figure 20 for test conditions for outputs.
7. Tests for open drain outputs are intended to guarantee switching of the output transistor. Measurement of this response is referenced from
midpoint of the switching signal to a point 0.2V above the actual output signal level. This point represents noise margin that assures true
switching has occurred.
8. Execution of the valid command (after it is latched) requires 3 rising edges of X1 (see Figure 15).
9. These values were not explicitly tested; they are guaranteed by design and characterization data.
10. X1/CLK and X2 are not tested with a crystal installed.
11. X1/CLK frequency must be at least the faster of the receiver or transmitter serial data rate.
12. Timing is illustrated and referenced to the WRN and RDN inputs. The device may also be operated with CSN as the ‘strobing’ input. CSN
and RDN (also CSN and WRN) are ANDed internally. As a consequence, the signal asserted last initiates the cycle and the signal negated
first terminates the cycle.
13. VO = 0 to VCC, Rx and Tx clocks at 10MHz, X1 clock at 10MHz.
1998 Sep 04
8
Philips Semiconductors
Product specification
CMOS dual universal serial communications controller
(CDUSCC)
SC26C562
AC ELECTRICAL CHARACTERISTICS4,5,6,7 TA = 0°C to +70°C, –40 to +85C, VCC = 5V ±10%
RESETN
tRELREH
SD00205
Figure 3. Reset Timing
LIMITS
SYMBOL
PARAMETER
INDUSTRIAL SC26C562
Min
tRELREH
RESETN low to RESETN high
COMMERCIAL SC26C562
Max
Min
200
UNIT
Max
200
ns
A6–A1
tADVRDL
tCEHCEL
tRDHCEH
CSN (CEN)
tCELRDL
tRDLADI
tRDLRDH
tRDHRDL
RDN
tRDLDDV
tRDLDLZ
tRDHDDF
D0–D7
tRDLRYL
tRDHDDI
tRYZDDV
RDYN
A
NOTE:
A Wait on Rx. Receiver FIFO empty.
SD00240
Figure 4. Read Cycle12
LIMITS
SYMBOL
PARAMETER
INDUSTRIAL SC26C562
Min
tADVRDL
tCELRDL
tRDLADI
tRDLRYL
tRDLDDV
tRDLRDH
tRYZDDV
tRDHCEH
tCEHCEL
tRDHDDI
tRDHRDL
tRDHDDF
tRDLDLZ
1998 Sep 04
Address valid to RDN low
CEN low to RDN low
RDN low to address invalid
RDN low to RDYN low
RDN low to read data valid
RDN low to RDN high
RDYN high impedance to read data valid9
RDN high to CEN high
CEN high to CEN low
RDN high to read data invalid
RDN high to RDN low
RDN high to data bus floating
RDN low to data bus low impedance9
Max
10
10
60
COMMERCIAL SC26C562
Min
5
0
50
160
150
150
150
130
130
90
10
50
5
50
90
0
30
5
30
50
5
9
40
10
UNIT
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Philips Semiconductors
Product specification
CMOS dual universal serial communications controller
(CDUSCC)
SC26C562
AC ELECTRICAL CHARACTERISTICS (Continued)
A6–A1
tADVWRL
tCEHCEL
tWRHCEH
CSN (CEN)
tCELWRL
tWRLADI
tWRLWRH
tWRHWRL
WRN
tWDVWRH
tWRHWDI
D0–D7
tWRLRYL
RDYN
A
tRYHZWRH
NOTE:
A Wait on Tx. Transmitter FIFO full.
SD00241
Figure 5. Write
Cycle12
LIMITS
SYMBOL
PARAMETER
INDUSTRIAL SC26C562
Min
tADVWRL
tCELWRL
tWRLRYL
tWRHCEH
tWRLWRH
tWDVWRH
tCEHCEL
tWRLADI
tWRHWRL
tWRHWDI
tRYHZWRH
1998 Sep 04
Address valid to WRN low
CSN low to WRN low
WRN low to RDYN low
WRN high to CSN high
WRN low to WRN high
Write data valid to WRN high
CEN high to CEN low
WRN low to address invalid
WRN high to WRN low
WRN high to write data invalid
RDYN hi impedance to WRN high9
10
Max
COMMERCIAL SC26C562
Min
10
10
5
0
10
110
65
50
60
50
10
10
0
100
60
30
50
30
5
0
160
UNIT
Max
150
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Philips Semiconductors
Product specification
CMOS dual universal serial communications controller
(CDUSCC)
SC26C562
AC ELECTRICAL CHARACTERISTICS (Continued)
SERVICE
ROUTINE
A
INTERRUPT REQUEST LOCKED
IRQN
Cleared
through
software
VECTOR SETTLING
IACKN
A
VECTOR
LOCKED
tIALDDV
A
C
D7–D0
C
B
tIAHDDI
tIAHDDF
NOTES:
A ICR[5:4] = 01 or 10 (mode 1 or mode 2)
B Call instruction (mode 2)
C ICR[5:4] = 11 (mode 3)
SD00208
Figure 6. Interrupt Acknowledge Cycle
LIMITS
SYMBOL
PARAMETER
INDUSTRIAL SC26C562
Min
tIALDDV
tIAHDDF
tIAHDDI
tIALDLZ
tIAHIAL
IACKN low to data bus valid
IACKN high to data bus floating
IACKN high to data bus invalid
IACKN low to data bus low impedance9
IACKN high to low
5
5
40
COMMERCIAL SC26C562
Max
Min
140
60
UNIT
Max
130
60
5
10
30
ns
ns
ns
ns
ns
CEN
WRN
tWRHGOV
GPO1_N
AND/OR
GPO2_N
OLD DATA
NEW DATA
SD00209
Figure 7. Output Port Timing
LIMITS
SYMBOL
PARAMETER
INDUSTRIAL SC26C562
Min
tWRHGOV
1998 Sep 04
WRN high to GPO output data valid
Max
100
11
COMMERCIAL SC26C562
Min
UNIT
Max
100
ns
Philips Semiconductors
Product specification
CMOS dual universal serial communications controller
(CDUSCC)
SC26C562
AC ELECTRICAL CHARACTERISTICS (Continued)
CSN (CEN)
RDN
tGIVRDL
tRDLGII
GPI1N
AND/OR
GPI2N
SD00242
Figure 8. Input Port Timing
LIMITS
SYMBOL
PARAMETER
INDUSTRIAL SC26C562
Min
tGIVRDL
tRDLGII
GPI input valid to RDN low
RDN low to GPI input invalid
Min
20
40
*Pull-up resistor is not required when using CMOS levels
TTL
UNIT
COMMERCIAL SC26C562
Max
Max
20
40
ns
ns
DRIVING
FROM EXTERNAL
SOURCE
VCC
470Ω
*
X1
X2 OPEN WHEN
X1 IS DRIVEN
X2
÷2
X1
CL1
tCLHCLL
tCCHCCL
tRCHRCL
tTCHTCL
CP1
TO
CDUSCC
CIRCUITS
50-150kΩ
CL2
X2
CP2
X1/CLK
CTCLK
RxC
TxC
CP1 = 7-12pF
SC26C562
CP2 = 12-17pF
tCLLCLH
tCCLCCH
tRCLRCH
tTCLTCH
NOTE: CL1 AND CL2 VALUES DEPEND ON
CRYSTAL
MANUFACTURER’S REQUIREMENTS, AND SHOULD
INCLUDE CP1 AND CP2
SD00243
Figure 9. Clock Timing
LIMITS
SYMBOL
PARAMETER
INDUSTRIAL SC26C562
Min
tCLHCLL
tCLLCLH
tCCHCCL
tCCLCCH
tRCHRCL
tRCLRCH
tTCHTCL
tTCLTCH
fCL
fCC
fRC
fTC
fRTC
1998 Sep 04
X1/CLK high to low time
X1/CLK low to high time
C/T CLK high to low time
C/T CLK low to high time
RxC high to low time
RxC low to high time
TxC high to low time
TxC low to high time
X1/CLK frequency11
C/T CLK frequency
RxC frequency (16X or 1X @ 50% duty cycle)
TxC frequency (16X or 1X @ 50% duty cycle)
Tx/Rx frequency for FM/Manchester encoding
25
25
50
50
55
55
55
55
0
0
0
0
12
Typ
14.7456
Max
16.0
8
8
8
4
COMMERCIAL SC26C562
Min
25
25
45
45
50
50
50
50
0
0
0
0
Typ
14.7456
UNIT
Max
16.0
10
10
10
5
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
MHz
MHz
Philips Semiconductors
Product specification
CMOS dual universal serial communications controller
(CDUSCC)
SC26C562
AC ELECTRICAL CHARACTERISTICS (Continued)
1 BIT TIME
(1 OR 16 CLOCKS)
TxC
(INPUT)
TxC
(INPUT)
tCILTXV
tCILTXV
tCILTXV
TxD
TxD
tCOLTXV
tCOLTXV
TxC
(1X OUTPUT)
TxC
(1X OUTPUT)
a. Transmit Timing NRZ
tCOLTXV
b. Transmit Timing FM0/1, Manchester Encoding
SD00244
Figure 10.
LIMITS
SYMBOL
PARAMETER
INDUSTRIAL SC26C562
Min
tCILTXV
tCOLTXV*
Max
TxC input low (1X) to TxD output
TxC input low (16X) to TxD output
TxC output low to TxD output9
(NRZ, NRZI)
FM, MAN
COMMERCIAL SC26C562
Min
120
120
25
35
UNIT
Max
120
120
20
30
ns
ns
ns
ns
*Characterized with no loads on TxD and TxC outputs. Tester load is approximately 50pF.
tRCHSOL
RXC
(INPUT)
SYNOUTN
tSILRCH
tRCHRXI
tRXVRCH
tRXVRCH
tRCHSIH
SYNIN
RxD
RXC (1X)
INPUT
tRXVRCH
tRCHRXI
tRCHRXI
RxD
a. Receive Timing NRZ
b. Receive Timing FM0/1, Manchester Encoding
SD00245
Figure 11.
SYMBOL
tRXVRCH
tRCHRXI
tSILRCH
tRCHSIH
tRCHSOL
1998 Sep 04
PARAMETER
LIMITS
INDUSTRIAL SC26C562
COMMERCIAL SC26C562
Min
Max
Min
Max
RxD data valid to RxC high:
For NRZ data
For NRZI, Manchester, FM0, FM1 data
RxC high to RxD data invalid:
For NRZ data
For NRZI, Manchester, FM0, FM1 data
SYNIN low to RxC high
RxC high to SYNIN high
RxC high to SYNOUT low
25
30
20
30
ns
ns
25
30
50
20
20
30
50
20
ns
ns
ns
ns
ns
110
13
UNIT
100
Philips Semiconductors
Product specification
CMOS dual universal serial communications controller
(CDUSCC)
SC26C562
AC ELECTRICAL CHARACTERISTICS (Continued)
tWRHEOZ
EOPN
(OUTPUT)
tWRLEOL
RTxDRQN OR
TxDRQN
CSN (CEN)
tWRLTRH
A
WRN
D7–D0
tEILWRH
tWRHEIH
EOPN
(INPUT)
A
The TxFIFO is addressed during this write cycle.
SD00246
Figure 12. Transmit Dual Address DMA Timing
LIMITS
SYMBOL
PARAMETER
INDUSTRIAL SC26C562
Min
tWRLTRH
tWRLEOL
tWRHEOZ
tEILWRH
tWRHEIH
1998 Sep 04
WRN low to Tx DMA REQN high
WRN low to EOPN output low
WRN high to EOPN output high impedance
EOPN input low to WRN high
WRN high to EOPN input high
35
30
14
Max
110
110
70
COMMERCIAL SC26C562
Min
30
25
UNIT
Max
100
100
60
ns
ns
ns
ns
ns
Philips Semiconductors
Product specification
CMOS dual universal serial communications controller
(CDUSCC)
SC26C562
AC ELECTRICAL CHARACTERISTICS (Continued)
RTxDRQN
tRDLRRH
CEN
A
RDN
D7–D0
tRDLEOL
tRDHEOZ
EOPN
(OUTPUT)
A
The RxFIFO is addressed during this read cycle.
SD00247
Figure 13. Receive Dual Address DMA Timing
LIMITS
SYMBOL
PARAMETER
INDUSTRIAL SC26C562
Min
tRDLRRH
tRDLEOL
tRDHEOZ
1998 Sep 04
RDN low to Rx DMA REQN high
RDN low to EOPN output low
RDN high to EOPN output high impedance
Max
110
110
70
15
COMMERCIAL SC26C562
Min
UNIT
Max
100
100
60
ns
ns
ns
Philips Semiconductors
Product specification
CMOS dual universal serial communications controller
(CDUSCC)
SC26C562
AC ELECTRICAL CHARACTERISTICS (Continued)
TxRQN
tTAHTAL
tTALTRH
TxDAKN
tTALTAH
WRN
A
A
B
B
MEMRN
tTAHEIH
tEILTAH
EOPN
(INPUT)
tWDVTAH
tTAHWDI
D7–D0
tTAHEOF
tTALEOL
EOPN
(OUTPUT)
NOTES:
A Ignored by the CDUSCC since CEN is not asserted, but it can be used externally to qualify TxDAKN.
B Memory read signal; not seen by CDUSCC.
SD00248
Figure 14. DMA-Transmit Single Address Mode
LIMITS
SYMBOL
PARAMETER
INDUSTRIAL SC26C562
Min
tTAHTAL
tTALTAH
tTALTRH
tWDVTAH
tTAHWDI
tTALEOL
tTAHEOF
tEILTAH
tTAHEIH
1998 Sep 04
Transmit DMA ACKN high to low time
Transmit DMA ACKN low to high time
Tx DMA ACKN low to Tx DMA REQN high
Write data valid to Tx DMA ACKN high
Tx DMA ACKN high to write data invalid
Tx DMA ACKN low to EOPN output low
Tx DMA ACKN high to EOPN output float
EOPN input low to Tx DMA ACKN high
Tx DMA ACKN high to EOPN input high
Max
40
110
60
15
40
30
16
COMMERCIAL SC26C562
Min
30
100
110
100
70
40
10
30
25
UNIT
Max
100
80
60
ns
ns
ns
ns
ns
ns
ns
ns
ns
Philips Semiconductors
Product specification
CMOS dual universal serial communications controller
(CDUSCC)
SC26C562
AC ELECTRICAL CHARACTERISTICS (Continued)
RxDRQN
tRAHRAL
tRALRRH
RxDAKN
tRALRAH
RDN
A
A
MEMWN
B
B
tRAHEOF
tRALEOL
EOPN
(OUTPUT)
tRALDDV
tRAHDDI
D7–D0
tRAHDDF
NOTES:
A Ignored by the CDUSCC bit; it can be used to qualify RxDAKN.
B Memory read signal; not seen by CDUSCC.
SD00249
Figure 15. DMA-Receive Single Address Mode
LIMITS
SYMBOL
PARAMETER
INDUSTRIAL SC26C562
Min
tRAHRAL
tRALRAH
tRALRRH
tRALEOL
tRAHEOF
tRALDDV
tRAHDDI
tRAHDDF
1998 Sep 04
Receive DMA ACKN high to low time
Receive DMA ACKN low to high time
Rx DMA ACKN low to Rx DMA REQN high
Rx DMA ACKN low to EOPN output low
Rx DMA ACKN high to EOPN output float
Rx DMA ACKN low to read data valid
Rx DMA ACKN high to read data invalid
Rx DMA ACKN high to data bus float
Max
50
140
COMMERCIAL SC26C562
Min
30
130
100
100
70
140
5
17
100
100
60
130
5
60
UNIT
Max
60
ns
ns
ns
ns
ns
ns
ns
ns
Philips Semiconductors
Product specification
CMOS dual universal serial communications controller
(CDUSCC)
SC26C562
AC ELECTRICAL CHARACTERISTICS (Continued)
VM
RDN/WRN
tRWHIRH
VOL +0.2V
IRQN
VOL
SD00218
Figure 16. Interrupt Timing
SYMBOL
PARAMETER
SYMBOL
PARAMETER
tRWHIRH
LIMITS
INDUSTRIAL SC26C562
Min
COMMERCIAL SC26C562
Max
RDN/WRN high to IRQN high for:
Read RxFIFO (RxRDY interrupt)
Write TxFIFO (TxRDY interrupt)
Write RSR (Rx condition interrupt)
Write TRSR (Rx/Tx interrupt)
Write ICTSR (counter/timer interrupt)
Write TRMSR (Tx Path, Patt. Det.)
Min
100
100
100
100
100
100
UNIT
Max
UNIT
90
90
90
90
90
90
ns
ns
ns
ns
ns
ns
X1/CLK
WRN
COMMAND
VALID
SD00219
Figure 17. Command Timing
RxC
1
2
3
4
5
6
7
8
2
3
4
5
6
7
8
RxD
LCN
a. Loop Control Output Assertion
RxC
1
9
RxD
LCN
b. Loop Control Output Negation
SD00220
Figure 18. Relationship Between Received Data and the Loop Control Output
1998 Sep 04
18
Philips Semiconductors
Product specification
CMOS dual universal serial communications controller
(CDUSCC)
50
SC26C562
50
0°C
40
40
25°C
30
30
ICC
ICC
70°C
20
20
10
10
0
0
4
4.5
5
5.5
6
4
6
8
10
Tx/Rx Clk and X1 Frequency
VCC
Test Condition: Tx/Rx and X1 Frequency @ 10MHz
Test Condition: VCC = 5V @ 25°C
SD00250
Figure 19.
2.7K
TRxC
VDD
IRQN
RTxC
50pF
50pF
820Ω
RDYN
+5.0V
150pF
1K
VDD
EOPN
50pF
710
ALL OTHER
OUTPUTS
+5.0V
150pF
NOTE:
All CL includes 50pF stray capacitance,
i.e., CL = 150pF = 100pF discrete +50pF stray.
SD00251
Figure 20. Test Conditions for Outputs
1998 Sep 04
19
Philips Semiconductors
Product specification
CMOS dual universal serial communications controller
(CSUSCC)
DIP48: plastic dual in-line package; 48 leads (600 mil)
1998 Sep 04
20
SC26C562
SOT240-1
Philips Semiconductors
Product specification
CMOS dual universal serial communications controller
(CSUSCC)
PLCC52: plastic leaded chip carrier; 52 leads; pedestal
1998 Sep 04
21
SC26C562
SOT238-3
Philips Semiconductors
Product specification
CMOS dual universal serial communications controller
(CSUSCC)
SC26C562
Data sheet status
Data sheet
status
Product
status
Definition [1]
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
 Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Date of release: 08-98
Document order number:
1998 Sep 04
22
9397 750 04355