INTEGRATED CIRCUITS DATA SHEET TZA3005H SDH/SONET STM1/OC3 and STM4/OC12 transceiver Product specification Supersedes data of 1997 Aug 05 File under Integrated Circuits, IC19 2000 Feb 17 Philips Semiconductors Product specification SDH/SONET STM1/OC3 and STM4/OC12 transceiver TZA3005H FEATURES GENERAL DESCRIPTION • Supports STM1/OC3 (155.52 Mbits/s) and STM4/OC12 (622.08 Mbits/s) The TZA3005H SDH/SONET transceiver chip is a fully integrated serialization/deserialization STM1/OC3 (155.52 Mbits/s) and STM4/OC12 (622.08 Mbits/s) interface device. It performs all necessary serial-to-parallel and parallel-to-serial functions in accordance with SDH/SONET transmission standards. It is suitable for SONET-based applications and can be used in conjunction with the data and clock recovery unit (TZA3004), optical front-end (TZA3023 with TZA3034/44) and a laser driver (TZA3001). A typical network application is shown in Fig.10. • Supports reference clock frequencies of 19.44, 38.88, 51.84 and 77.76 MHz • Meets Bellcore, ANSI and ITU-T specifications • Meets ITU jitter specification typically to a factor of 2.5 • Integral high-frequency PLL for clock generation • Interface to TTL logic • Low jitter PECL (Positive Emitter Coupled Logic) interface A high-frequency phase-locked loop is used for on-chip clock synthesis, which allows a slower external transmit reference clock to be used. A reference clock of 19.44, 38.88, 51.84 or 77.76 MHz can be used to support existing system clocking schemes. The TZA3005H also performs SDH/SONET frame detection. • 4 or 8-bit STM1/OC3 TTL data path • 4 or 8-bit STM4/OC12 TTL data path • No external filter components required • QFP64 package • Diagnostic and line loopback modes The low jitter PECL interface ensures that Bellcore, ANSI, and ITU-T bit-error rate requirements are satisfied. The TZA3005H is supplied in a compact QFP64 package. • Lock detect • LOS (Loss of Signal) input • Low power (0.9 W typical) • Selectable frame detection and byte realignment • Loop timing • Forward and reverse clocking • Squelched clock operation • Self-biased PECL inputs to support AC coupling. APPLICATIONS • SDH/SONET modules • SDH/SONET-based transmission systems • SDH/SONET test equipment • ATM (Asynchronous Transfer Mode) over SDH/SONET • Add drop multiplexers • Broadband cross-connects • Section repeaters • Fibre optic test equipment • Fibre optic terminators. ORDERING INFORMATION TYPE NUMBER TZA3005H 2000 Feb 17 PACKAGE NAME QFP64 DESCRIPTION plastic quad flat package; 64 leads (lead length 1.6 mm); body 14 × 14 × 2.7 mm 2 VERSION SOT393-1 Philips Semiconductors Product specification SDH/SONET STM1/OC3 and STM4/OC12 transceiver TZA3005H BLOCK DIAGRAM handbook, full pagewidth LLEN TXPD0 to TXPD7 TXPCLK MRST TEST1 TEST2 TEST3 BUSWIDTH REFSEL0 and REFSEL1 MODE REFCLK and REFCLKQ SDTTL SDPECL OOF DLEN RXSD and RXSDQ RXSCLK and RXSCLKQ TRANSMITTER 31 53 to 60 8 61 D 8:1 OR 4:1 PARALLEL TO SERIAL 48 10 11 13 RF SWITCH BOX 2 17, 18 TXSD and TXSDQ 2 21, 20 TXSCLK and TXSCLKQ (1) 30 TZA3005H 3, 4 2 62 49 CLOCK DIVIDER BY 4 OR BY 8 CLOCK SYNTHESIZER 15, 14 2 63 64 22 8 23 36, 37, 39, 40, 41, 43 to 45 on-chip capacitor 2 33 47 1:8 OR 1:4 SERIAL TO PARALLEL 32 24, 25 2 27, 28 2 35 FRAME HEADER DETECT 52 RECEIVER 2 5 VCC(SYNOUT) 8, 9 6 7 VCCD(SYN) GNDSYNOUT VCCA(SYN) 12 GND 16 19 26 29 VCC(TXOUT) VCC(RXOUT) GNDRXCORE VCC(RXCORE) AGNDSYN (1) Dashed lines represent normal operation mode. Fig.1 Block diagram. 3 38, 46 34, 42 GNDRXOUT GNDTXOUT DGNDSYN 2000 Feb 17 LOCKDET 19MHZO RXPD0 to RXPD7 RXPCLK FP D 51 1 SYNCLKDIV VCC(TXCORE) GNDTXCORE MGS975 Philips Semiconductors Product specification SDH/SONET STM1/OC3 and STM4/OC12 transceiver TZA3005H PINNING SYMBOL PIN TYPE(1) DESCRIPTION VCC(SYNOUT) 1 S supply voltage (synthesizer output) GNDSYNOUT 2 G ground (synthesizer output) REFSEL0 3 I reference clock select input 0 REFSEL1 4 I reference clock select input 1 DGNDSYN 5 G digital ground (synthesizer) VCCD(SYN) 6 S digital supply voltage (synthesizer) VCCA(SYN) 7 S analog supply voltage (synthesizer) AGNDSYN 8 G analog ground (synthesizer) AGNDSYN 9 G analog ground (synthesizer) TEST1 10 I test and control input TEST2 11 I test and control input GND 12 G ground TEST3 13 I test and control input REFCLKQ 14 I inverted reference clock input REFCLK 15 I reference clock input VCC(TXOUT) 16 S supply voltage (transmitter output) TXSD 17 O serial data output TXSDQ 18 O inverted serial data output GNDTXOUT 19 G ground (transmitter output) TXSCLKQ 20 O inverted serial clock output TXSCLK 21 O serial clock output SDTTL 22 I TTL signal detect input SDPECL 23 I PECL signal detect input RXSD 24 I serial data input RXSDQ 25 I inverted serial data input VCC(RXCORE) 26 S supply voltage (receiver core) RXSCLK 27 I serial clock input RXSCLKQ 28 I inverted serial clock input GNDRXCORE 29 G ground (receiver core) BUSWIDTH 30 I 4/8 bus width select input LLEN 31 I line loopback enable input (active LOW) DLEN 32 I diagnostic loopback enable input (active LOW) OOF 33 I out-of-frame enable input GNDRXOUT 34 G ground (receiver output) FP 35 O frame pulse output RXPD0 36 O parallel data output 0 RXPD1 37 O parallel data output 1 VCC(RXOUT) 38 S supply voltage (receiver output) RXPD2 39 O parallel data output 2 RXPD3 40 O parallel data output 3 2000 Feb 17 4 Philips Semiconductors Product specification SDH/SONET STM1/OC3 and STM4/OC12 transceiver PIN TYPE(1) RXPD4 41 O parallel data output 4 SYMBOL TZA3005H DESCRIPTION GNDRXOUT 42 G ground (receiver output) RXPD5 43 O parallel data output 5 RXPD6 44 O parallel data output 6 RXPD7 45 O parallel data output 7 VCC(RXOUT) 46 S supply voltage (receiver output) RXPCLK 47 O receive parallel clock output MRST 48 I master reset (active LOW) MODE 49 I serial data rate select STM1/STM4 ALTPIN 50 I test and control input GNDTXCORE 51 G ground (transmitter core) VCC(TXCORE) 52 S supply voltage (transmitter core) TXPD0 53 I parallel data input 0 TXPD1 54 I parallel data input 1 TXPD2 55 I parallel data input 2 TXPD3 56 I parallel data input 3 TXPD4 57 I parallel data input 4 TXPD5 58 I parallel data input 5 TXPD6 59 I parallel data input 6 TXPD7 60 I parallel data input 7 TXPCLK 61 I transmit parallel clock input SYNCLKDIV 62 O transmit byte/nibble clock output (synchronous) LOCKDET 63 O lock detect output 19MHZO 64 O 19 MHz reference clock output Note 1. Pin type abbreviations: O = Output, I = Input, S = Supply, G = Ground. 2000 Feb 17 5 Philips Semiconductors Product specification SDH/SONET STM1/OC3 and STM4/OC12 transceiver 49 MODE 50 ALTPIN 51 GNDTXCORE 53 TXPD0 54 TXPD1 55 TXPD2 56 TXPD3 57 TXPD4 58 TXPD5 59 TXPD6 60 TXPD7 61 TXPCLK 62 SYNCLKDIV 63 LOCKDET 64 19MHZO handbook, full pagewidth 52 VCC(TXCORE) TZA3005H VCC(SYNOUT) 1 48 MRST GNDSYNOUT 2 47 RXPCLK REFSEL0 3 46 VCC(RXOUT) REFSEL1 4 45 RXPD7 DGNDSYN 5 44 RXPD6 VCCD(SYN) 6 43 RXPD5 VCCA(SYN) 7 42 GNDRXOUT AGNDSYN 8 AGNDSYN 9 40 RXPD3 TEST1 10 39 RXPD2 TEST2 11 38 VCC(RXOUT) 41 RXPD4 TZA3005H GND 12 37 RXPD1 TEST3 13 36 RXPD0 REFCLKQ 14 35 FP 34 GNDRXOUT REFCLK 15 VCC(TXOUT) 16 Fig.2 Pin configuration. 2000 Feb 17 6 DLEN 32 LLEN 31 BUSWIDTH 30 GNDRXCORE 29 RXSCLKQ 28 RXSCLK 27 VCC(RXCORE) 26 RXSDQ 25 RXSD 24 SDPECL 23 SDTTL 22 TXSCLK 21 TXSCLKQ 20 GNDTXOUT 19 TXSDQ 18 TXSD 17 33 OOF MGK483 Philips Semiconductors Product specification SDH/SONET STM1/OC3 and STM4/OC12 transceiver TZA3005H FUNCTIONAL DESCRIPTION CLOCK SYNTHESIZER Introduction The clock synthesizer generates a serial output clock (TXSCLK) which is phase synchronised with the input reference clock (REFCLK). The serial output clock is synthesized from one of four SDH/SONET input reference clock frequencies and can have a frequency of either 155.52 MHz for STM1/OC3 or 622.08 MHz for STM4/OC12 selected by the MODE input (see Table 1). The TZA3005H transceiver implements SDH/SONET serialization/deserialization, transmission and frame detection/recovery functions. The TZA3005H can be used as the front-end for SONET equipment. It handles the serial receive and transmit interface functions including parallel-to-serial and serial-to-parallel conversion and clock generation. A block diagram showing the basic operation of the chip is shown in Fig.1. Table 1 The TZA3005H has a transmitter section, a receiver section, and an RF switch box. The sequence of operations is as follows: • Transmitter operations: – 4 or 8-bit parallel input Transmitter output clock (TXSCLK) frequency options MODE INPUT TXSCLK FREQUENCY OPERATING MODE 0 155.52 MHz STM1/OC3 1 622.08 MHz STM4/OC12 – parallel-to-serial conversion – frame detection The frequency of the input reference clock is divided to obtain a frequency of about 19 MHz which is fed to the phase detector in the PLL. The appropriate divisor is selected by control inputs REFSEL0 and REFSEL1 as shown in Table 2. – serial-to-parallel conversion Table 2 – serial output. • Receiver operations: – serial input Reference frequency (REFCLK) options – 4 or 8-bit parallel output. The RF switch box receives serial clock and data signals from the transmitter section, the receiver input buffers and from the clock synthesizer. These signals are routed by multiplexers to the transmitter section, the transmitter output, the receiver and to the clock divider, depending on the status of the control inputs. The switch box also supports a number of test and loop modes. REFSEL0 REFCLK FREQUENCY 0 0 19.44 MHz 0 1 38.88 MHz 1 0 51.84 MHz 1 1 77.76 MHz To ensure the TXSCLK frequency is accurate enough to operate in a SONET system, REFCLK must be generated from a differential PECL crystal oscillator having a frequency accuracy better than 4.6 ppm for compliance with “ITU G.813 (option 1)”, or 20 ppm for “ITU G.813 (option 2)”. Transmitter operation The transmitter section of the TZA3005H converts STM1/OC3 or STM4/OC12 byte-serial input data to a bit-serial output data format. Input data rates of 19.44, 38.88, 77.76 or 155.52 Mbytes/s are converted to an output data rate of either 155.52 or 622.08 Mbits/s. It also provides diagnostic loopback (transmitter to receiver), line loopback (receiver to transmitter) and also loop timing (transmitter clocked by the receiver clock). To comply with SONET jitter requirements, the maximum value specified for reference clock signal jitter must be guaranteed over the 12 kHz to 1 MHz bandwidth (see Table 3). An integral frequency synthesizer, comprising a phase-locked loop and a divider, can be used to generate a high-frequency bit clock from an input reference clock frequency of 19.44, 38.88, 51.84 or 77.76 MHz. 2000 Feb 17 REFSEL1 7 Philips Semiconductors Product specification SDH/SONET STM1/OC3 and STM4/OC12 transceiver Table 3 mode, a 4-bit parallel data stream is generated having a clock frequency of either 38.88 or 155.52 MHz. It also provides diagnostic loopback (transmitter to receiver), line loopback (receiver to transmitter) and squelched clock operation (transmitter clock to receiver). ITU reference clock signal (REFCLK) jitter limits MAXIMUM JITTER OF REFCLK 12 kHz TO 1 MHz OPERATING MODE 56 ps (RMS) STM1/OC3 14 ps (RMS) STM4/OC12 TZA3005H FRAME AND BYTE BOUNDARY DETECTION The frame and byte boundary detection circuit searches the incoming data for the correct 48-bit frame pattern which is a sequence of three consecutive A1 bytes of F0 H followed immediately by three consecutive A2 bytes of 28 H. Frame pattern detection is enabled and disabled by the out-of-frame enable input (OOF). Detection is enabled by a rising edge on pin OOF, and remains enabled while the level on pin OOF is HIGH. It is disabled when at least one frame pattern is detected and the level on pin OOF is no longer HIGH. When frame pattern detection is enabled, the frame pattern is used to locate byte and frame boundaries in the incoming data stream (Received Serial Data (RXSD) or looped transmitter data). The serial to parallel converter block uses the located byte boundary to divide the incoming data stream into bytes for output on the parallel output data bus (RXPD0 to RXPD7). When the correct 48-bit frame pattern is detected, the occurrence of the frame boundary is indicated by the Frame Pulse (FP) signal. When frame pattern detection is disabled, the byte boundary is fixed, and only frame patterns which align with the fixed byte boundary produce an output on pin FP. The on-chip PLL contains a phase detector, a loop filter and a VCO. The phase detector compares the phases of the VCO and the divided REFCLK signals. The loop filter converts the phase detector output to a smooth DC voltage which controls the VCO frequency and ensures that it is always 622.08 MHz. In STM1/OC3 mode, the correct output frequency at TXSCLK is obtained by dividing the VCO frequency by 4. The loop filter parameters are optimized for minimal output jitter. CLOCK DIVIDER The clock divider generates either a byte rate or a nibble rate version of the serial output clock (TXSCLK) which is output on pin SYNCLKDIV (see Table 4). Table 4 MODE INPUT SYNCLKDIV frequency BUSWIDTH SYNCLKDIV FREQUENCY OPERATING MODE 0 0 (nibble) 38.88 MHz STM1/OC3 0 1 (byte) 19.44 MHz STM1/OC3 1 0 (nibble) 155.52 MHz STM4/OC12 1 1 (byte) 77.76 MHz STM4/OC12 It is extremely unlikely that random data in an STM1/OC3 or STM4/OC12 data stream will replicate the 48-bit frame pattern. Therefore, the time taken to detect the beginning of the frame should be less than 250 µs (as specified in “ITU G.783”) even at extremely high bit error rates. SYNCLKDIV is intended for use as a byte speed clock for upstream multiplexing and overhead processing circuits. Using SYNCLKDIV for upstream circuits ensures a stable frequency and phase relationship is maintained between the data in to and out of the TZA3005H. Once down-stream overhead circuits verify that frame and byte synchronization are correct, OOF can be set LOW to prevent the frame search process synchronizing to a mimic frame pattern. For parallel-to-serial data conversion, the parallel input data is transferred from the TXPCLK byte clock timing domain to the internally generated bit clock timing domain. The internally generated bit clock does not have to be phase aligned to the TXPCLK signal but must be synchronized by the master reset (MRST) signal. SERIAL-TO-PARALLEL CONVERTER The serial-to-parallel converter causes a delay between the first bit of an incoming serial data byte to the start of the parallel output of that byte. The delay depends on the time taken for the internal parallel load timing circuit to synchronize the data byte boundaries to the falling edge of RXPCLK. The timing of RXPCLK is independent of the byte boundaries. RXPCLK is neither truncated nor extended during reframe sequences. Receiver operation The receiver section of the TZA3005H converts STM1/OC3 or STM4/OC12 bit-serial input data to a parallel data output format. In byte mode, input data rates of 155.52 or 622.08 Mbits/s are converted to an output data rate of either 19.44 or 77.76 Mbytes/s. In nibble 2000 Feb 17 8 Philips Semiconductors Product specification SDH/SONET STM1/OC3 and STM4/OC12 transceiver TZA3005H Transceiver pin descriptions Signal detect PECL (SDPECL) TRANSMITTER INPUT SIGNALS This is a single-ended PECL input with an internal pull-down resistor. This input is driven by an external optical receiver module to indicate a loss of received optical power (LOS). SDPECL is active HIGH when SDTTL is at logic 0 and active LOW when SDTTL is at logic 1or unconnected. When there is a loss of signal, SDPECL is inactive and the bit-serial data on pins RXSD and RXSDQ is internally forced to a constant zero. When SDPECL is active, the bit-serial data on pins RXSD and RXSDQ is processed normally (see Table 5). Parallel data inputs (TXPD0 to TXPD7) These are TTL data word inputs. The input data is aligned with the TXPCLK parallel input clock. TXPD7 is the most significant bit (corresponding to bit 1 of each PCM word, the first bit transmitted). TXPD0 is the least significant bit (corresponding to bit 8 of each PCM word, the last bit transmitted). Bits TXPD0 to TXPD7 are sampled on the rising edge of TXPCLK. If a 4-bit bus width is selected, TXPD7 is the most significant bit and TXPD4 is the least significant bit. Inputs TXPD0 to TXPD3 are unused. Signal detect TTL (SDTTL) This is a single-ended TTL input with an internal pull-up resistor. This input is driven by an external optical receiver module to indicate a loss of received optical power (LOS). SDTTL is active HIGH when pin SDPECL is logic 0 or unconnected, and active LOW when pin SDPECL is at logic 1. When there is a loss of signal, SDTTL is inactive and the bit-serial data on pins RXSD and RXSDQ is internally forced to a constant zero. When SDTTL is active, the bit-serial data on pins RXSD and RXSDQ is processed normally (see Table 5). Parallel clock input (TXPCLK) This is a TTL input clock signal having a frequency of either 19.44, 38.88, 77.76 or 155.52 MHz and a duty factor of nominally 50%, to which input data bits TXPD0 to TXPD7 are aligned. TXPCLK transfers the input data to a holding register in the parallel-to-serial converter. The rising edge of TXPCLK samples bits TXPD0 to TXPD7. After a master reset, one rising edge of TXPCLK is required to fully initialize the internal data path. If pin SDTTL instead of pin SDPECL is to be connected to the optical receiver module, connect pin SDPECL to a logic HIGH-level to implement an active-LOW signal detect, or leave pin SDPECL unconnected to implement an active-HIGH signal detect. RECEIVER INPUT SIGNALS Receive serial data (RXSD and RXSDQ) These are differential PECL serial data inputs, normally connected to an optical receiver module or to the TZA3004 data and clock recovery unit, and clocked by RXSCLK and RXSCLKQ. These inputs can be AC coupled without external biasing. Table 5 Receive serial clock (RXSCLK and RXSCLKQ) These are differential PECL recovered clock signals synchronized to the input data RXSD and RXSDQ. It is used by the receiver as the master clock for framing and deserialization functions. These inputs can be AC coupled without external biasing. SDPECL SDTTL RXPD OUTPUT DATA 0 or floating 0 0 0 or floating 1 or floating RXSD input data 1 0 RXSD input data 1 1 or floating 0 COMMON INPUT SIGNALS Bus width selection (BUSWIDTH) Out-of-frame (OOF) This is a TTL signal which selects 4-bit or 8-bit operation for the transmit and receive parallel interfaces. BUSWIDTH LOW selects a 4-bit bus width. BUSWIDTH HIGH selects an 8-bit bus width. This is a TTL signal which enables frame pattern detection logic in the TZA3005H. The frame pattern detection logic is enabled by a rising edge on pin OOF, and remains enabled until a frame boundary is detected and OOF goes LOW. OOF is an asynchronous signal with a minimum pulse width of one RXPCLK period (see Fig.3). 2000 Feb 17 SDPECL/SDTTL truth table 9 Philips Semiconductors Product specification SDH/SONET STM1/OC3 and STM4/OC12 transceiver TZA3005H Reference clock (REFCLK and REFCLKQ) Parallel clock (SYNCLKDIV) These are differential PECL reference clock inputs for the internal bit clock synthesizer. This is a TTL reference clock generated by dividing the internal bit clock by eight, or by four when BUSWIDTH is LOW. It is normally used to coordinate byte-wide transfers between upstream logic and the TZA3005H. Diagnostic loopback enable (DLEN) This is an active-LOW TTL signal which selects diagnostic loopback. When DLEN is HIGH, the TZA3005H receiver uses the primary data (RXSD) and clock (RXSCLK) inputs. When DLEN is LOW, the receiver uses the diagnostic loopback clock and the transmitter input data. Lock detect (LOCKDET) This is an active HIGH CMOS signal. When active, it indicates that the transmit PLL is locked to the reference clock input. Master reset (MRST) 19 MHz clock output (19MHZO) This is an active LOW TTL signal which initializes the transmitter. SYNCLKDIV is LOW during reset. This is a 19 MHz CMOS clock from the clock synthesizer. It can be connected to the reference clock input of an external clock recovery unit, such as the TZA3004. Line loopback enable (LLEN) RECEIVER OUTPUT SIGNALS This is an active LOW TTL signal which selects line loopback. When LLEN is LOW, the TZA3005H routes the data and clock from the receiver inputs RXSD and RXSCLK to the transmitter outputs TXSD and TXSCLK. Parallel data outputs (RXPD0 to RXPD7) These outputs comprise a parallel TTL data bus. The parallel output data is aligned with the parallel output clock (RXPCLK). RXPD7 is the most significant bit (corresponding to bit 1 of each PCM word, the first bit received). RXPD0 is the least significant bit (corresponding to bit 8 of each PCM word, the last bit received). RXPD0 to RXPD7 are updated on the falling edge of RXPCLK. When a 4-bit bus width is selected, RXPD7 is the most significant bit and bit 4 is the least significant bit. Outputs RXPD0 to RXPD3 are forced LOW. Reference select (REFSEL0 and REFSEL1) These are TTL signals which select the reference clock frequency (see Table 2). Mode select (MODE) This TTL signal selects the transmitter serial data rate. MODE LOW selects 155.52 Mbits/s. MODE HIGH selects 622.08 Mbits/s. Frame pulse (FP) Test inputs (ALTPIN, TEST1, TEST2, TEST3) This is a TTL signal which indicates frame boundaries detected in the incoming data stream on pin RXSD. When frame pattern detection is enabled (see Section “Out-of-frame (OOF)”), FP goes HIGH for one cycle of RXPCLK when a 48-bit sequence matching the frame pattern is detected on inputs RXSD and RXSDQ. When frame pattern detection is disabled, FP goes HIGH only when the incoming data matches the frame pattern and fits exactly within the fixed byte boundary. FP is updated on the falling edge of RXPCLK. These are active HIGH TTL signals which control the operating mode and test internal circuits during production testing. For normal operation, these inputs are left unconnected and internal pull-down resistors hold each pin LOW. See Table 7 for more details. TRANSMITTER OUTPUT SIGNALS Transmit clock outputs (TXSCLK and TXSCLKQ) These are differential PECL serial clock signals which can be used to retime TXSD. The clock frequency is either 155.52 MHz or 622.08 MHz depending on the operating mode. Parallel output clock (RXPCLK) This is a TTL byte-rate output clock having a frequency of either 19.44, 38.88, 77.76 or 155.52 MHz and a duty factor of nominally 50%, to which the byte-serial output data bits RXPD0 to RXPD7 are aligned. The falling edge of RXPCLK updates the data on pins RXPD0 to RXPD7 and the FP signal. Transmit serial data (TXSD and TXSDQ) These are differential PECL serial data stream outputs which are normally connected to an optical transmitter module or to the TZA3001 laser driver. 2000 Feb 17 10 Philips Semiconductors Product specification SDH/SONET STM1/OC3 and STM4/OC12 transceiver TZA3005H Other operating modes SQUELCHED CLOCK OPERATION DIAGNOSTIC LOOPBACK Some clock recovery devices force their recovered output clock to zero if a loss of input signal is detected. If this happens, the SDTTL or SDPECL signals are inactive and no clock signal is present at pins RXSCLK and RXSCLKQ. A transmitter-to-receiver loopback mode is available for diagnostic purposes. When DLEN is LOW, the differential serial clock and data from the transmitter parallel-to-serial block continue to be routed to transmitter outputs, but are also routed to the receiver serial-to-parallel block instead of the receiver input signals from pins RXSD/RXSDQ and RXSCLK/RXSCLKQ. If no clock signal is present at pins RXSCLK/RXSCLKQ, there is no RXPCLK signal. This may not be suitable for some applications, in which case, the TZA3005H can be set to squelched clock operation by setting pins ALTPIN, TEST1, TEST2 and TEST3 as shown in Table 6. LINE LOOPBACK In squelched clock operation, receiver timing is performed by a part of the internal clock synthesizer which normally only provides transmitter timing. This produces a RXPCLK clock signal when either SDTTL or SDPECL is inactive. If either SDTTL or SDPECL is inactive in squelched clock operation, it is equivalent to normal operation. During a transition from normal operation to squelched clock operation, the RXPCLK clock cycle exhibits a once-only random shortening. A receiver-to-transmitter loopback mode is available for line testing purposes. When LLEN is LOW, the receiver input signals (RXSD/RXSDQ and RXSCLK/RXSCLKQ) are routed, after retiming, to the transmitter output buffers. The receiver clock and data are also routed to the serial-to-parallel block. LOOP TIMING In loop timing mode, the transmitter section is clocked by the receiver input clock (RXSCLK) instead of by the internal clock synthesizer. SYNCLKDIV is now derived from RXSCLK so that it can be used to clock upstream transmitter logic. Loop timing is enabled by setting pins ALTPIN, TEST1, TEST2 and TEST3 (see Table 6). After activating the loop timing mode, the receiver clock must be synchronized to the transmitter input data (TXPD0 to TXPD7) by activating master reset (MRST). In loop timing mode, the internal clock synthesizer is still used to generate the 19MHz output clock signal on pin 19MHZO. 2000 Feb 17 Table 6 shows that the same operating mode can be selected at different settings of the control inputs. If ALTPIN = 0, the STM4 nibble mode is not available, but is used for squelched clock operation. If ALTPIN = 1, all operating modes are available, including STM4 nibble mode. 11 Philips Semiconductors Product specification SDH/SONET STM1/OC3 and STM4/OC12 transceiver Table 6 TZA3005H Truth table operating modes ALTPIN TEST1 TEST2 TEST3 (pin 50) (pin 10) (pin 11) (pin 13) BUSWIDTH (pin 30) MODE (pin 49) SD(1) LLEN DLEN (pin 31) (pin 32) FUNCTIONAL OPERATING MODE 0 X X 0 X 0 X 1 1 normal operation (STM1 byte/nibble) 0 X X 0 0 1 0 1 1 squelched clock operation (STM4 byte) 0 X X 0 0 1 1 1 1 normal operation (STM4 byte) 0 X X 0 1 1 X 1 1 normal operation (STM4 byte) 0 X X 1 X X X 1 1 loop timing 1 0 0 0 X X X 1 1 normal operation 1 0 0 1 X X X 1 1 loop timing 1 0 1 0 X X 0 1 1 squelched clock operation 1 0 1 0 X X 1 1 1 normal operation X X X X X X X X 0 diagnostic loopback X X X X X X X 0 X line loopback Note 1. SD denotes either pin 22 (SDTTL) or pin 23 (SDPECL) (signal present = active = 1; loss of signal = inactive = 0). During a loss of signal, the outputs RXPD0 to RXPD7 are forced to zero (see Table 5). Receiver frame alignment The frame and byte boundary detection block is activated on the rising edge of OOF, and remains active until a frame pulse (FP) occurs and OOF goes LOW, whichever occurs last. Figure 4 shows a typical OOF timing pattern when the TZA3005H is connected to a down stream section terminating device. OOF stays HIGH for one full frame after the first frame pulse (FP). The frame and byte boundary detection block is active until OOF goes LOW. Figure 3 shows a typical frame and boundary alignment sequence. Frame and byte boundary detection is enabled on the rising edge of OOF and remains enabled while OOF is HIGH. Byte boundaries are recognized after the third A2 byte is received. FP goes HIGH for one RXPCLK cycle to indicate that this is the first data byte with the correct byte alignment on the output parallel data bus (RXPD0 to RXPD7). Figure 5 shows frame and byte boundary detection activated on the rising edge of OOF, and deactivated by the first frame pulse (FP) after OOF goes LOW. When interfaced with a section terminating device, OOF must remain HIGH for a full frame period after the initial frame pulse (FP). This is to allow the section terminating device to internally verify that frame and byte alignment are correct (see Fig.4). Because at least one frame pattern will have been detected since the rising edge of OOF, boundary detection is disabled when OOF goes LOW. 2000 Feb 17 12 Philips Semiconductors Product specification SDH/SONET STM1/OC3 and STM4/OC12 transceiver TZA3005H handbook, full pagewidth RXSCLK OOF RXSD A1 A1 A1 A2 A2 RXPD0 to RXPD7 A2 A2 (28H) valid data invalid data RXPCLK FP MGK485 Fig.3 Frame and byte detection. handbook, halfpage boundary detection enabled handbook, halfpage boundary detection enabled OOF OOF FP FP MGK486 MGK487 Fig.4 OOF operating time with PM5312 STTX or PM5355 SUNI-622 (see Table 7). 2000 Feb 17 Fig.5 Alternate OOF timing. 13 Philips Semiconductors Product specification SDH/SONET STM1/OC3 and STM4/OC12 transceiver TZA3005H LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL PARAMETER VCC supply voltage Vn voltage II(n) MIN. −0.5 MAX. +6 UNIT V on any input pin −0.5 VCC + 0.5 V between two differential PECL input pins −2 +2 V on SDPECL input pin VCC − 3 VCC + 0.5 V into any TTL output pin −8 +8 mA into any PECL output pin −50 +1.5 mA current Ptot total power dissipation − 1.5 W Tstg storage temperature −65 +150 °C Tj(bias) junction temperature under bias −55 +125 °C Tcase(bias) case temperature under bias −55 +100 °C HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However it is good practice to take normal precautions appropriate to handling MOS devices (see “Handling MOS devices” ). THERMAL CHARACTERISTICS SYMBOL PARAMETER VALUE UNIT Tamb ambient temperature; note 1 −40 +85 Tj junction temperature −40 +125 Rth(j-a) thermal resistance from junction to ambient; note 2 55 K/W Notes 1. For applications with Tamb >75 °C, it is advised that the board layout is designed to allow optimum heat transer. 2. Rth(j-a) is determined with the IC soldered on a standard single-sided 57 × 57 × 1.6 mm FR4 epoxy PCB with 35 µm thick copper tracks. The measurements are performed in still air. This value will vary depending on the number of board layers, copper sheet thickness and area, and the proximity of surrounding components. 2000 Feb 17 14 Philips Semiconductors Product specification SDH/SONET STM1/OC3 and STM4/OC12 transceiver TZA3005H DC CHARACTERISTICS For typical values, Tamb = 25 °C and VCC = 3.3 V; minimum and maximum values are valid over entire Tj and VCC ranges. SYMBOL PARAMETER CONDITION MIN. TYP. MAX. UNIT General VCC supply voltage Ptot total power dissipation ICC(tot) total supply current 3.0 3.3 5.5 V VCC = 3.47 V − 0.9 1.4 W VCC = 5.5 V − − 2.3 W VCC = 3.47 V − 272 394 mA VCC = 5.5 V − − 420 mA outputs open; outputs open; TTL inputs VIH HIGH-level input voltage 2 − VCC V VIL LOW-level input voltage 0 − 0.8 V IIH HIGH-level input current VIH = VCC; note 1 −10 − +10 µA IIL LOW-level input current VIL = 0; note 1 −10 − +10 µA Rpu pull-up resistor note 2 8 10 12 kΩ Rpd pull-down resistor at pin SDTTL 8 10 12 kΩ TTL outputs VOH HIGH-level output voltage IOH = −1 mA; note 3 2.4 − − V VOL LOW-level output voltage IOL = 4 mA − − +0.5 V note 4 PECL I/O VIH HIGH-level input voltage VIL LOW-level input voltage VOH HIGH-level output voltage VOL LOW-level output voltage ∆Vo(dif) differential output voltage ∆Vi(dif)(sens) differential input sensitivity terminated with 50 Ω to VCC − 2.0 V PECL inputs are AC coupled VCC − 1.2 − − V − − VCC − 1.6 V VCC − 1.1 − VCC − 0.9 V VCC − 1.9 − VCC − 1.6 V ±600 − ±900 mV ±100 − − mV Notes 1. For input pins REFSEL0, REFSEL1, BUSWIDTH, LLEN, DLEN, OOF, MRST, MODE, TXPDn, TXPCLK. 2. For input pins SDPECL, ALTPIN, TEST1, TEST2, TEST3. 3. Only applies to pin 19MHZO; guaranteed by simulation. 4. The PECL inputs are high impedance. The transmission lines should be terminated externally using an appropriate termination. 2000 Feb 17 15 Philips Semiconductors Product specification SDH/SONET STM1/OC3 and STM4/OC12 transceiver TZA3005H AC CHARACTERISTICS For typical values, Tamb = 25 °C and VCC = 3.3 V; minimum and maximum values are valid over entire Tj and VCC ranges. SYMBOL PARAMETER CONDITION MIN. TYP. MAX. UNIT General fTXSCLK(nom) nominal TXSCLK frequency fREFCLK as Table 2; MODE = 0 155.517 155.52 155.523 MHz MODE = 1 622.068 622.08 622.092 MHz − 0.004 0.006 UI (RMS) −20 − +20 ppm − 220 450 ps − − 15 pF 40 50 60 % Jo data output jitter fREFCLK(tol) frequency tolerance of REFCLK meets SONET output frequency specification; note 1 tr, tf rise/fall time PECL outputs in lock; note 1 20% to 80%; 50 Ω load to VCC − 2.0 V Receiver timing (see Figs 6 and 7) CL TTL output load capacitance δRXPCLK duty factor of RXPCLK tPD propagation delay; RXPCLK LOW to RXPDn, FP −0.5 +1.5 +2.5 ns tsu set-up time; RXSD/RXSDQ to RXSCLK/RXSCLKQ 400 − − ps th hold time; RXSD/RXSDQ to RXSCLK/RXSCLKQ 400 − − ps note 2 Transmitter timing (see Figs 8 and 9) δTXSCLK duty factor of TXSCLK 40 50 60 % tsu set-up time; TXPDn to TXPCLK −0.5 − − ns th hold time; TXPDn to TXPCLK 1.5 − − ns tPD propagation delay time; TXSCLK LOW to TXSD − − 440 ps Notes 1. Jitter on pins REFCLK/REFCLKQ complies with Table 3. 2. Minimum value is 35% in STM4 nibble mode. 2000 Feb 17 16 Philips Semiconductors Product specification SDH/SONET STM1/OC3 and STM4/OC12 transceiver TZA3005H handbook, halfpage handbook, halfpage RXPCLK RXSCLK tsu t PD RXPD0 to RXPD7, FP th RXSD/RXSDQ MGK489 MGK488 For TTL outputs, tPD is the time (ns) from the 50% point of the reference signal to the 50% point of the output signal. Timing is measured from the cross-over point of the reference signal to the cross-over point of the input signal. Fig.6 Receiver output timing. Fig.7 Receiver input timing. handbook, halfpage TXPCLK handbook, halfpage TXSCLK tsu th t PD TXPD0 to TXPD7 TXSD MGK490 MGK491 For TTL signals, tsu between input data and clock signals is the time (ps) from the 50% point of the data to the 50% point of the clock. For TTL signals, th between input data and clock signals is the time (ps) from the 50% point of the clock to the 50% point of the data. Timing is measured from the cross-over point of the reference signal to the cross-over point of the output signal. Fig.8 Transmitter input timing. 2000 Feb 17 Fig.9 Transmitter output timing. 17 Philips Semiconductors Product specification SDH/SONET STM1/OC3 and STM4/OC12 transceiver TZA3005H INTERNAL CIRCUITRY PIN SYMBOL AND DESCRIPTION CHARACTERISTIC 24 RXSD; serial data input PECL inputs 27 RXSCLK; serial clock input 25 RXSDQ; inverted serial data input 28 RXSCLKQ; inverted serial clock input EQUIVALENT CIRCUIT VCC −1.35 V handbook, halfpage 10 kΩ 10 kΩ 25, 28 24, 27 100 µA GND 14 15 REFCLKQ; inverted reference clock input PECL inputs VCC −1.35 V handbook, halfpage REFCLK; reference clock input MGS979 10 kΩ VCC 10 kΩ VCC 600 fF 600 fF 2 kΩ 2 kΩ 14 15 100 µA GND 23 SDPECL; PECL signal detect input PECL input MGS980 VCC handbook, halfpage 600 fF 25 kΩ VCC −1.35 V 23 100 µA GND 2000 Feb 17 18 MGS981 Philips Semiconductors Product specification SDH/SONET STM1/OC3 and STM4/OC12 transceiver PIN SYMBOL AND DESCRIPTION CHARACTERISTIC 3 REFSEL0; reference clock select input 0 TTL inputs 4 REFSEL1; reference clock select input 1 10 TEST1; test and control input 11 TEST2; test and control input 13 TEST3; test and control input 30 BUSWIDTH; 4/8 bus width select input 31 LLEN; line loopback enable input (active LOW) 32 DLEN; diagnostic loopback enable input (active LOW) 33 OOF; out-of-frame enable input 48 MRST; master reset (active LOW) 49 MODE; serial data rate select STM1/STM4 50 ALTPIN; test and control input 22 SDTTL; TTL signal detect input 53 TXPD0; parallel data input 0 54 TXPD1; parallel data input 1 55 TXPD2; parallel data input 2 56 TXPD3; parallel data input 3 57 TXPD4; parallel data input 4 58 TXPD5; parallel data input 5 59 TXPD6; parallel data input 6 60 TXPD7; parallel data input 7 61 TXPCLK; transmit parallel clock input 36 RXPD0; parallel data output 0 37 RXPD1; parallel data output 1 39 RXPD2; parallel data output 2 40 RXPD3; parallel data output 3 41 RXPD4; parallel data output 4 43 RXPD5; parallel data output 5 44 RXPD6; parallel data output 6 45 RXPD7; parallel data output 7 47 RXPCLK; receive parallel clock output 62 EQUIVALENT CIRCUIT handbook, halfpage 50 kΩ 3, 4, 10, 11, 13, 30 to 33, 48 to 50 1 pF GND MGS982 TTL inputs handbook, halfpage 100 Ω 22, 53 to 61 ≈ 50 µA GND MGS983 TTL outputs handbook, halfpage VCC 15 Ω 36, 37, 39 to 41, 43 to 45, 47, 62 15 Ω GND MGS984 SYNCLKDIV; transmit byte/nibble clock output (synchronous) 2000 Feb 17 TZA3005H 19 Philips Semiconductors Product specification SDH/SONET STM1/OC3 and STM4/OC12 transceiver PIN SYMBOL AND DESCRIPTION CHARACTERISTIC 63 LOCKDET; lock detect output; R = 50 Ω CMOS outputs 64 19MHZO; 19 MHz reference clock output; R = 20 Ω TZA3005H EQUIVALENT CIRCUIT VCC handbook, halfpage 50 Ω 63, 64 R GND MGS985 17 TXSD; serial data output 18 TXSDQ; inverted serial data output 20 TXSCLKQ; inverted serial clock output 21 TXSCLK; serial clock output PECL outputs handbook, halfpage VCC 17, 21 18, 20 500 µA 500 µA GND MGS986 2000 Feb 17 20 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... PHOTO DIODE TZA3005 AND TZA3044 LASER DRIVER 8 TZA3023 OPTICAL RECEIVER TZA3004 data DCR(1) 8 clock clock TZA3005 21 CONTROLLER CONTROLLER 8 TRANSCEIVER TRANSCEIVER TZA3023 TZA3004 data DCR(1) AND PHOTO DIODE LASER DIODE TZA3044 8 TZA3001 LASER DRIVER OPTICAL RECEIVER Philips Semiconductors optical fibre SDH/SONET STM1/OC3 and STM4/OC12 transceiver APPLICATION INFORMATION handbook, full pagewidth 2000 Feb 17 LASER DIODE TZA3001 MGK494 Product specification Fig.10 Application diagram. TZA3005H (1) DCR = Data and Clock Recovery unit. Philips Semiconductors Product specification SDH/SONET STM1/OC3 and STM4/OC12 transceiver TZA3005H Forward clocking Reverse clocking It is sometimes necessary to ‘forward clock’ data in an SDH/SONET system. When this is the case, the input parallel data clock (TXPCLK) and the reference clock (REFCLK/REFCLKQ) from which the high speed serial clock is synthesized will both originate from the same clock source. This section explains how to configure the TZA3005H to operate in this mode. In many cases, a reverse clocking scheme is used where the upstream logic is clocked by the TZA3005H using SYNCLKDIV (see Fig.14). There is no requirement specification for the propagation delay from SYNCLKDIV to TXPCLK because the TZA3005H can handle any phase relationship between these two signals. The TZA3005H internal transmitter logic must be synchronized by asserting a master reset (MRST). The connections required for forward clocking are shown in Fig.13. There are no timing specifications for the phase relationship between REFCLK and TXPCLK. The TZA3005H can handle any phase relationship between these two input clocks if they are derived from the same clock source. The TZA3005H internal transmitter logic must be synchronized by asserting a master reset (MRST). handbook, halfpage PECL output termination The PECL outputs have to be terminated with 50 Ω connected to VCC − 2.0 V. If this voltage is not available, a Thevenin termination can be used as shown in Figs 11 and 12. VCC = 5.0 V R1 83.3 Ω R3 125 Ω GND handbook, halfpage R2 83.3 Ω R1 127 Ω R2 127 Ω TXSD/TXSCLK TXSD/TXSCLK TXSDQ/TXSCLKQ TXSDQ/TXSCLKQ R4 125 Ω R3 82.5 Ω GND MGK654 Fig.11 PECL output termination scheme (VCC = 5.0 V). 2000 Feb 17 VCC = 3.3 V R4 82.5 Ω MGS978 Fig.12 PECL output termination scheme (VCC = 3.3 V). 22 Philips Semiconductors Product specification SDH/SONET STM1/OC3 and STM4/OC12 transceiver TZA3005H handbook, full pagewidth CLOCK SOURCE PECL REFCLK TXPCLK ASIC 8 TZA3005 parallel data serial data TXPD0 to TXPD7 MGS976 Fig.13 TZA3005H in forward clocking scheme. handbook, full pagewidth CLOCK SOURCE PECL REFCLK TXPCLK ASIC 8 TZA3005 parallel data TXPD0 to TXPD7 SYNCLKDIV MGS977 Fig.14 TZA3005H in reverse clocking scheme. 2000 Feb 17 23 serial data Philips Semiconductors Product specification SDH/SONET STM1/OC3 and STM4/OC12 transceiver Table 7 TZA3005H Suggested interface devices MANUFACTURER Philips PMC-Sierra 2000 Feb 17 DATA RATE (Mbits/s) TYPE FUNCTION TZA3004 622 or 155 clock recovery TZA3031/3001 155/622 laser driver TZA3034/3044 155/622 post amplifier TZA3033/3023 155/622 transimpedance amplifier PM5312 155 or 622 transport terminal transceiver PM5355 622 Saturn user network interface 24 Philips Semiconductors Product specification SDH/SONET STM1/OC3 and STM4/OC12 transceiver TZA3005H PACKAGE OUTLINE QFP64: plastic quad flat package; 64 leads (lead length 1.6 mm); body 14 x 14 x 2.7 mm SOT393-1 c y X A 48 33 49 32 ZE e E HE A A2 (A 3) A1 θ wM Lp bp pin 1 index L 17 64 detail X 16 1 w M bp e v M A ZD D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 3.00 0.25 0.10 2.75 2.55 0.25 0.45 0.30 0.23 0.13 14.1 13.9 14.1 13.9 0.8 HD HE L 17.45 17.45 1.60 16.95 16.95 Lp v w y 1.03 0.73 0.16 0.16 0.10 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 θ o 7 0o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT393-1 134E07 MS-022 2000 Feb 17 EIAJ EUROPEAN PROJECTION ISSUE DATE 99-12-27 00-01-19 25 Philips Semiconductors Product specification SDH/SONET STM1/OC3 and STM4/OC12 transceiver • For packages with leads on two sides and a pitch (e): SOLDERING – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Reflow soldering During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C. Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. 2000 Feb 17 TZA3005H 26 Philips Semiconductors Product specification SDH/SONET STM1/OC3 and STM4/OC12 transceiver TZA3005H Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE REFLOW(1) WAVE BGA, LFBGA, SQFP, TFBGA not suitable suitable(2) HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not PLCC(3), SO, SOJ suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO suitable suitable suitable not recommended(3)(4) suitable not recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. 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Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 403510/150/02/pp28 Date of release: 2000 Feb 17 Document order number: 9397 750 06573