UT54ACS164245S RadHard Schmitt CMOS 16-bit Bidirectional MultiPurpose Transceiver Datasheet April , 2002 LOGIC SYMBOL FEATURES • Voltage translation - 5V bus to 3.3V bus - 3.3V bus to 5V bus • Cold sparing - 1MΩ minimum input impedance power-off • 0.6µm Commercial CMOS - Total dose: 100K rad(Si) - Single Event Latchup immune • High speed, low power consumption • Schmitt trigger inputs to filter noisy signals • Available QML Q or V processes • Standard Microcircuit Drawing 5962-98580 • Package: - 48-lead flatpack, 25 mil pitch (.390 x .640) RadHardTM G1 G2 1A1 1A2 The 16-bit wide UT54ACS164245S MultiPurpose transceiver RadHard TM is built using UTMC’s Commercial epitaxial CMOS technology and is ideal for space applications. This high speed, low power UT54ACS164245S transceiver is designed to perform multiple functions including: asynchronous two-way communication, signal buffering, voltage translation, and cold sparing. With V DD equal to zero volts, the UT54ACS164245S outputs and inputs present a minimum impedance of 1MΩ making it ideal for "cold spare" applications. Balanced outputs and low "on" output impedance make the UT54ACS164245S well suited for driving high capacitance loads and low impedance backplanes. The UT54ACS164245S enables system designers to interface 3.3 volt CMOS compatible components with 5 volt CMOS components. For voltage translation, the A port interfaces with the 3.3 volt bus; the B port interfaces with the 5 volt bus. The direction control (DIRx) controls the direction of data flow. The output enable (OEx) overrides the direction control and disables both ports. These signals can be driven from either port A or B. The direction and output enable controls operate these devices as either two independent 8-bit transceivers or one 16-bit transceiver. 2EN1 (BA) 2EN2 (AB) 1EN1 (BA) 1EN2 (AB) (1) DIR1 (47) (24) DIR2 (2) 11 12 (46) (3) (44) (5) (43) 1A4 (41) 1A5 (40) 1A6 (38) 1A7 (37) 1A8 (36) 2A1 (6) 1A3 2A2 DESCRIPTION 1 O E1 (48) O E2 (25) 2A3 (8) 1B1 1B2 1B3 1B4 1B5 (9) 1B6 (11) 1B7 (12) 1B8 (13) 2B1 21 22 (35) (14) 2B2 (16) 2B3 (17) 2B4 (19) 2B5 (20) 2B6 (22) 2B7 (23) 2B8 (33) (32) 2A4 (30) 2A5 (29) 2A6 (27) 2A7 (26) 2A8 PIN DESCRIPTION Pin Names Description OE x Output Enable Input (Active Low) DIRx Direction Control Inputs xAx Side A Inputs or 3-State Outputs (3.3V Port) xBx Side B Inputs or 3-State Outputs (5V Port) FUNCTION TABLE ENABLE OE x DIRECTION DIRx OPERATION L L B Data To A Bus L H A Data To B Bus H X Isolation PINOUTS POWER TABLE1 48-Lead Flatpack Top View Port B Port A OPERATION 5 Volts 3.3 Volts Voltage Translator 5 Volts 5 Volts Non Translating 3.3 Volts 3.3 Volts Non Translating DIR1 1 48 OE1 V SS V SS Cold Spare 1B1 2 47 1A1 V SS 3.3V or 5V Port B Cold Spare 1B2 3 46 V SS 1B3 4 1A2 V SS NOTE: 5 45 44 1A3 1. V DD2 cannot be tied to V SS while power is applied to VD D 1. 1B4 6 43 1A4 VDD1 7 42 VDD2 41 40 39 1A5 1A6 V SS 8 9 10 1B7 11 38 1A7 1B8 12 37 1A8 2B1 13 36 2A1 2B2 14 35 V SS 15 34 2A2 V SS 2B3 16 33 2A3 2B4 17 32 2A4 VDD1 18 31 VDD2 2B5 2B6 V SS 19 20 21 30 29 28 2A5 2A6 V SS 2B7 22 27 2B8 23 24 26 25 2A7 2A8 O E2 1B5 1B6 DIR2 Control signals DIRx and OEx are 5 volt tolerant inputs. When V DD2 is at 3.3 volts, either 3.3 or 5 volt CMOS logic levels can be applied to all control inputs. For proper operation connect power to all VDD and ground all V SS pins (i.e., no floating V DD or V SS input pins). Tie unused inputs to VSS . If VDD1 and V DD2 are not powered up together, then V DD2 should be powered up first for proper control of OE and DIR. Until V DD2 reaches 2.75V + 5%, control of the outputs by OE and DIR cannot be guaranteed. During operation of the part, after power up, insure VDD1 > V DD2 . Tie unused inputs to V SS . V SS 2 LOGIC DIAGRAM 2A1 3.3V PORT 1A4 (20) 2A7 (22) 2A8 (12) 3 2B7 (26) (23) 1B8 2B6 (27) 1B7 (37) 2B5 (29) 1B6 (38) 2B4 (30) (19) 2A6 (11) 1A8 (17) 2A5 2B3 (32) 1B5 (40) (9) 1A7 1B4 (41) (8) 1A6 (16) 2A4 2B2 (33) 1B3 (43) (6) 1A5 (14) 2A3 2B1 (35) 1B2 (44) OE 2 (36) (13) 2A2 (5) (25) 1B1 (46) (3) 1A3 (24) O E1 (47) (2) 1A2 DIR2 3.3V PORT 1A1 (48) 2B8 5 V PORT (1) 5 V PORT DIR1 RADIATION HARDNESS SPECIFICATIONS 1 PARAMETER LIMIT UNITS Total Dose 1.0E5 rad(Si) SEL Latchup >120 MeV-cm2 /mg Neutron Fluence 2 1.0E14 n/cm 2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Not tested, inherent of CMOS technology. ABSOLUTE MAXIMUM RATINGS 1 SYMBOL PARAMETER LIMIT (Mil only) UNITS V I/O Voltage any pin -.3 to V DD1 +.3 V V DD1 Supply voltage -0.3 to 6.0 V V DD2 Supply voltage -0.3 to 6.0 V TSTG Storage Temperature range -65 to +150 °C TJ Maximum junction temperature +175 °C ΘJ C Thermal resistance junction to case 20 °C/W II DC input current ±10 mA PD Maximum power dissipation 1 W Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability and performance. DUAL SUPPLY OPERATING CONDITIONS SYMBOL PARAMETER LIMIT UNITS V DD1 Supply voltage 3.0 to 3.6 or 4.5 to 5.5 V V DD2 Supply voltage 3.0 to 3.6 or 4.5 to 5.5 V V IN Input voltage any pin 0 to VDD1 V TC Temperature range -55 to + 125 °C 4 DC ELECTRICAL CHARACTERISTICS 1 ( -55°C < TC < +125°C) (T C = -55 ° C to +125°°C for "C" screening and -40°°C to +125 ° C for "W" screening) SYMBOL PARAMETER VT + Schmitt Trigger, positive going threshold2 V T- Schmitt Trigger, negative going threshold2 V DD from 3.00 to 5.5 V H1 Schmitt Trigger range of hysteresis10 V H2 IIN CONDITION MIN V DD from 3.00 to 5.5 MAX UNIT .7VDD V .3VDD V V DD from 4.5 to 5.5 0.6 V Schmitt Trigger range of hysteresis10 V DD from 3.00 to 3.6 0.4 V Input leakage current10 V DD from 3.6 to 5.5 -1 3 µA -1 3 µA -1 5 µA -200 200 mA -100 100 mA I OL= 8mA 0.4 V I OL= 100µA 0.2 V IN = V DD or VSS I OZ Three-state output leakage current10 V DD from 3.6 to 5.5 V IN = V DD or VSS ICS Cold sparing leakage current 3 V IN = 5.5 V DD = V SS IOS1 Short-circuit output current 6, 11 V O = V DD or VSS V DD from 4.5 to 5.5 IOS2 Short-circuit output current 6, 11 V O = V DD or VSS V DD from 3.00 to 3.6 VOL1 Low-level output voltage4, 10 V DD = 4.5 VOL2 Low-level output voltage4, 10 I OL= 8mA 0.5 I OL= 100µA 0.2 V V DD = 3.00 V OH1 High-level output voltage4, 10 I OH= -8mA I OH= -100µA V DD - 0.7 V VDD - 0.2 V DD = 4.5 V OH2 High-level output voltage4, 10 I OH= -8mA V DD - 0.9 I OH= -100µA VDD - 0.2 V DD = 3.00 5 V Ptotal1 Power dissipation 5,7, 8 CL = 50pF 2.0 mW/ MHz 1.5 mW/ MHz µA µA V DD from 4.5 to 5.5 Ptotal2 Power dissipation 5, 7, 8 CL = 50pF V DD from 3.00 to 3.6 I DD Standby Supply Current VDD1 or VDD2 V IN = V DD or VSS V DD = 5.5 CIN Pre-Rad 25oC OE=V DD Pre-Rad -55o C to +125oC OE=V DD 10 100 Post-Rad 25oC OE=V DD 500 µA Input capacitance 9 ƒ = 1MHz @ 0V 15 pF 15 pF V DD from 3.00 to 5.5 COUT Output capacitance9 ƒ = 1MHz @ 0V V DD from 3.00 to 5.5 Notes: 1. All specifications valid for radiation dose ≤ 1E5 rad(Si) per MIL-STD-883, Method 1019. 2. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: V IH = V IH (min) + 20%, - 0%; V IL = V IL(max) + 0%, - 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within th e above specified range, but are guaranteed to V IH (min) and VIL (max). 3. All combinations of OEx and DIRx 4. Per MIL-PRF-38535, for current density ≤ 5.0E5 amps/cm 2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765 pF-MHz. 5. Guaranteed by characterization. 6. Not more than one output may be shorted at a time for maximum duration of one second. 7. Power does not include power contribution of any CMOS output sink current. 8. Power dissipation specified per switching output. 9.Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at frequency of 1MHz and a signal amplitude of 50mV rms maximum. 10 .Guaranteed; tested on a sample of pins per device. 11. Supplied as a design limit, but not guaranteed or tested. . 6 AC ELECTRICAL CHARACTERISTICS 1 (Port B = 5 Volt, Port A = 3.3 Volt) (V DD1 = 5V ±10%; V DD2 = 3.00V to 3.6V, -55°C < TC < +125 °C ) (T C = -55 °C ° to +125 °C ° for "C" screening and -40°°C to +125°°C for "W" screening SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPLH Propagation delay Data to Bus 1 20 ns tPHL Propagation delay Data to Bus 1 20 ns tPZL Output enable time OEx to Bus 1 18 ns tPZH Output enable time OEx to Bus 1 18 ns tPLZ Output disable time OEx to Bus high impedance 1 20 ns tPHZ Output disable time OEx to Bus high impedance 1 20 ns tPZL 2 Output enable time DIRx to Bus 1 18 ns tPZH2 Output enable time DIRx to Bus 1 18 ns tPLZ 2 Output disable time DIRx to Bus high impedance 1 20 ns tPHZ2 Output disable time DIRx to Bus high impedance 1 20 ns Notes: 1. All specifications valid for radiation dose ≤ 1E5 rad(Si) per MIL-STD-883, Method 1019. 2. DIRx to bus times are guaranteed by design, but not tested. OEx to bus times are tested. Propagation Delay Input tPLH V DD V DD /2 0V tPHL V OH V DD /2 V OL Output Enable Disable Times Control Input 5V Output Normally Low 5V Output Normally High tPZL tPLZ V DD/2-0.2 tPHZ tPZH V DD /2+0.2 tPZL 3.3V Output Normally Low 3.3V Output Normally High .2VDD + .2V .8VDD - .2V tPLZ VDD /2-0.2 .2V DD + .2V tPHZ tPZH VDD /2+0.2 7 .7V DD - .2V V DD V DD /2 0V V DD /2 .2V DD .8V DD V DD /2 VDD /2 .2VDD .7VDD VDD /2 8 AC ELECTRICAL CHARACTERISTICS 1 (Port A = Port B, 5 Volt Operation) (VDD1 = 5V ±10%; V DD2 = 5.0V +10%, -55°C < T C < +125°C) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPLH Propagation delay Data to Bus 1 15 ns tPHL Propagation delay Data to Bus 1 15 ns tPZL Output enable time OEx to Bus 1 12 ns tPZH Output enable time OEx to Bus 1 12 ns tPLZ Output disable time OEx to Bus high impedance 1 15 ns tPHZ Output disable time OEx to Bus high impedance 1 15 ns tPZL 2 Output enable time DIRx to Bus 1 12 ns tPZH2 Output enable time DIRx to Bus 1 12 ns tPLZ 2 Output disable time DIRx to Bus high impedance 1 15 ns tPHZ2 Output disable time DIRx to Bus high impedance 1 15 ns Notes: 1. All specifications valid for radiation dose ≤ 1E5 rad(Si) per MIL-STD-883, Method 1019. 2. DIRx to bus times are guaranteed by design, but not tested. OEx to bus times are tested Propagation Delay Input tPLH V DD V DD/2 0V tPHL V OH V DD/2 V OL Output Enable Disable Times Control Input 5V Output Normally Low 5V Output Normally High tPZL tPLZ V DD/2-0.2 .2VDD + .2V tPHZ tPZH V DD/2+0.2 9 .8V DD - .2V V DD V DD/2 0V V DD/2 .2V DD .8V DD V DD/2 AC ELECTRICAL CHARACTERISTICS 1 (Port A = Port B, 3.3 Volt Operation) (VDD1 = 3.00V to 3.6V; V DD2 = 3.00V to 3.6V, -55°C < TC < +125°C) SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPLH Propagation delay Data to Bus 1 20 ns tPHL Propagation delay Data to Bus 1 20 ns tPZL Output enable time OEx to Bus 1 18 ns tPZH Output enable time OEx to Bus 1 18 ns tPLZ Output disable time OEx to Bus high impedance 1 20 ns tPHZ Output disable time OEx to Bus high impedance 1 20 ns tPZL 2 Output enable time DIRx to Bus 1 18 ns tPZH2 Output enable time DIRx to Bus 1 18 ns tPLZ 2 Output disable time DIRx to Bus high impedance 1 20 ns tPHZ2 Output disable time DIRx to Bus high impedance 1 20 ns Notes: 1. All specifications valid for radiation dose ≤ 1E5 rad(Si) per MIL-STD-883, Method 1019 . 2. DIRx to bus times are guaranteed by design, but not tested. OEx to bus times are tested. Propagation Delay Input tPLH V DD V DD /2 0V tPHL V OH V DD /2 V OL Output Enable Disable Times Control Input 3.3V Output Normally Low 3.3V Output Normally High tPZL tPLZ V DD/2-0.2 .2VDD + .2V tPHZ tPZH V DD /2+0.2 10 .7VDD - .2V V DD V DD /2 0V V DD /2 .2V DD .7VDD V DD /2 PACKAGE 5 6 4 6 1. All exposed metalized areas are gold plated over electroplated nickel per MIL-PRF-38535. 2. The lid is electrically connected to VSS. 3. Lead finishes are in accordance with MIL-PRF-38535. 4. Lead position and colanarity are not measured. 5. ID mark symbol is vendor option. 6. With solder, increase maximum by 0.003. Figure 1. 48-Lead Flatpack 11 ORDERING INFORMATION UT54ACS164245S: SMD 5962 R 98580 ** * * * Lead Finish: (C) = Gold Case Outline: (X) = 48 lead BB FP (Gold only) Class Designator: (Q) = Class Q (V) = Class V Device Type (01) = 16-bit MultiPurpose Transceiver (3.13V - 5.5V) (02) = 16-bit MultiPurpose Transceiver (3.0V - 5.5V) (03) = Extended Industrial Temp (-40 oC to +125oC) Drawing Number: 98580 Total Dose: (R) = 1E5 rad(Si) Federal Stock Class Designator: No options Notes: 1. Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening. 12 UT54ACS164245S UT54 *** ****** * * * Lead Finish: (C) = Gold Screening: (C) = Mil Temp (P) = Prototype (W) = Extended Industrial Temp (-40 oC to +125 oC) Package Type: (U) = 48-lead BB FP (Gold only) Part Number: (164245S) = 16-bit MultiPurpose Transceiver I/O Type: (ACS)= CMOS compatible I/O Level UTMC Core Part Number Notes: 1. Military Temperature Range flow per UTMC Manufacturing Flows Document. Devices are tested -55C, room temp, and 125C. Radiation n either tested nor guaranteed. 2. Prototype flow per UTMC Manufacturing Flows Document Tested at 25C only. Lead finish is gold only. 3. Extended Industrial Temperature Range Flow per UTMC Manufacturing Flows Document. Devices are tested at -40oC, room temp, and +125 oC. Radiation is neither tested nor guaranteed 13 14