UT54ACTQ16374 16-bit D Flip Flop

Standard Products
UT54ACTQ16374
RadHard CMOS 16-bit D Flip-Flop TTL Inputs, and
Three-State Outputs
Datasheet
May 16, 2012
www.aeroflex.com/radhard
PIN DESCRIPTION
FEATURES
 16 non-inverting D flip-flops with three-state outputs
 Guaranteed simultaneously switching noise level and dynamic threshold performance
 Buffered positive edge-triggered clock
 Separate control logic for each byte
 Guaranteed pin-to-pin output skew
Pin Names
Description
OEn
Output Enable Input (Active Low)
CPn
Clock Pulse Input
I0-I15
Inputs
O0-O15
Outputs
RadHardTM
CMOS
 0.6m Commercial
- Total dose: 100K rad(Si)
- Single Event Latchup immune
LOGIC SYMBOL
- SEU Onset LET >95 MeV -cm2/mg
 High speed, low power consumption
 Output source/sink 24mA
 Standard Microcircuit Drawing 5962-06245
- QML compliant part
 Package:
- 48-lead flatpack, 25 mil pitch (.390 x .640)
OE1
(1)
EN2
CP1 (48)
OE2 (24)
CP2 (25)
C1
EN4
I0
I1
DESCRIPTION
1
(47)
(46)
(2)
1D
2
(3)
(44)
(5)
(43)
I3
(41)
I4
(40)
I5
(38)
I6
(37)
I7
(36)
I8
(35)
I9
(33)
I10
(32)
I11
(30)
I12
(29)
I13
(27)
I14
(26)
I15
(6)
I2
The 16-bit wide UT54ACTQ16374 D flip-flop is built using
Aeroflex’s Commercial RadHardTM epitaxial CMOS technology and is ideal for space applications. This high-speed, low power UT54ACTQ16374 D flip-flop is designed for bus oriented
applications. A buffered clock (CP) and Output Enable (OE) are
common to each byte and can be shorted together for full 16-bit
operation. The UT54ACTQ16374 are particularly suitable for
implementing buffer registers, I/O ports, bidirectional bus drivers and working registers. Each flip-flop will store the state of
their indivdual D inputs (In) that meet the setup and hold requirements on the low-to-high clock (CPn) transition. With the
Output Enable (OEn) low, the contents of the flip-flops are available at the output. When OEn is high, the outputs go to high
impedance state. Operation of OEn input does not affect the state
of the D flip-flops.
C3
(8)
3D
4
(9)
(11)
(12)
(13)
(14)
(16)
(17)
(19)
O0
O1
O2
O3
O4
O5
O6
O7
O8
O9
O10
O11
O12
(20)
O13
(22)
O14
(23)
O15
PINOUTS
48-Lead Flatpack
Top View
OE1
1
48
CP1
O0
2
47
I0
O1
3
46
VSS
O2
4
5
45
44
I1
VSS
O3
6
43
VDD
7
42
VDD
O4
O5
VSS
8
9
10
41
40
39
I4
I5
VSS
O6
11
38
I6
O7
12
37
I7
O8
13
36
I8
O9
VSS
14
15
35
34
I9
VSS
O10
16
33
I10
O11
VDD
17
32
I11
O12
O13
VSS
18
19
20
21
31
30
29
28
VDD
I12
I13
VSS
O14
O15
OE2
22
23
24
27
26
25
I14
I15
CP2
I2
I3
2
FUNCTION TABLE
INPUTS
OUTPUT
OPERATION
OEn
CPn
In
On
H
H
L
Z
Hold
H
H
H
Z
Hold
H

L
Z
Load
H

H
Z
Load
L

L
L
Data Available
L

H
H
Data Available
L
H
L
Qo
No change in data
L
H
H
Qo
No change in data
3
LOGIC DIAGRAM
BYTE 1 (0:7)
(48)
(1)
(47)
(46)
(44)
(43)
I0
I1
I2
I3
(41)
(40)
(38)
(37)
I4
I5
I6
I7
CP I
CP I
CP I
CP I
CP I
CP I
CP I
CP I
0
0
0
0
0
0
0
0
O0
O1
O2
O3
O4
O5
O6
O7
(2)
(3)
(5)
(6)
(8)
(9)
(11)
(12)
CP1
OE1
BYTE 2 (8:15)
(36)
I8
(35)
I9
(33)
I10
(32)
I11
(30)
I12
(29)
I13
(27)
I14
(26)
I15
I CP
I CP
I CP
I CP
I CP
I CP
I CP
I CP
0
0
0
0
0
0
0
0
O8
O9
(13)
(14)
O10
(16)
O11
(17)
O12
(19)
O13
O14
(20)
(22)
4
O15
(23)
CP2
(25)
OE2
(24)
RADIATION HARDNESS SPECIFICATIONS 1
PARAMETER
LIMIT
UNITS
Total Dose
1.0E5
rad(Si)
SEL Immune
>108
MeV-cm2/mg
SEU Onset LET
>95
MeV-cm2/mg
Neutron Fluence2
1.0E14
n/cm2
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Not tested, inherent of CMOS technology.
ABSOLUTE MAXIMUM RATINGS1
SYMBOL
PARAMETER
LIMIT (Mil only)
UNITS
VI/O
Voltage any pin during operation
-.3 to VDD +.3
V
VDD
Supply voltage
-0.3 to 6.0
V
TSTG
Storage Temperature range
-65 to +150
C
TJ
Maximum junction temperature
+175
C
JC
Thermal resistance junction to case
20
C/W
II
DC input current
10
mA
PD
Maximum power dissipation
310
mW
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at
these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability and performance.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMIT
UNITS
VDD
Supply voltage
4.5 to 5.5
V
VIN
Input voltage any pin
0 to VDD
V
TC
Temperature range
-55 to + 125
C
tINRISE
tINFALL
Maximum input rise or fall time
(VIN transitioning between VIL (max) and VIH (min))
20
ns
5
DC ELECTRICAL CHARACTERISTICS 1
( -55C < TC < +125C)
SYMBOL
PARAMETER
CONDITION
MIN
MAX
UNIT
0.8
V
VIL
Low level input voltage2
VDD from 4.5V to 5.5V
VIH
High level input voltage2
VDD from 4.5V to 5.5V
2.0
IIN
Input leakage current3
VDD from 4.5V to 5.5V
-1
1
A
-10
10
A
-600
600
mA
0.36
0.5
V
V
VIN = VDD or VSS
IOZ
Three-state output leakage current
VDD from 4.5V to 5.5V
VIN = VDD or VSS
IOS
Short-circuit output current 4, 5
VO = VDD or VSS
VDD from 4.5V to 5.5V
VOL1
Low-level output voltage5
IOL= 24mA
-55C, 25C
IOL= 24mA
+125C
IOL= 100A
-55C, 25C,
+125C
0.2
-55C, 25C
0.8
VDD = 5.5V
+125C
1.0
IOH= -24mA
-55C, 25C
VDD - 0.64
IOH= -24mA
+125C
VDD - 0.8
IOH= -100A
-55C, 25C,
+125C
VDD - 0.2
-55C, 25C
VDD -1.1
+125C
VDD -1.3
VIN = 2V or 0.8V
VDD = 4.5V to 5.5V
VOL2
Low-level output voltage5,6
IOL= 50mA
V
VIN = 2.0V or 0.8V
VOH1
High-level output voltage5
V
VIN = 2V or 0.8V
VDD = 4.5V to 5.5V
VOH2
High-level output voltage5,6
IOH= -50mA
V
VIN = 2.0V or 0.8V
VDD = 5.5V
VIC+
Positive input clamp voltage
For input under test, IIN = 18mA
0.4
1.5
V
-1.5
-0.4
V
VDD = 0.0V
VIC-
Negative input clamp voltage
For input under test, IIN = -18mA
VDD = open
6
Ptotal
Power dissipation 7,6,9
CL = 20pF
0.5
VDD from 4.5V to 5.5V
IDDQ
Standby Supply Current VDD
VIN = VDD or VSS
VDD = 5.5V
IDDQ
mW/
MHz
Pre-Rad 25oC
OEn = VDD
10
-55oC to +125oC
OEn = VDD
Post-Rad 25oC
OEn = VDD
160
160
Quiescent Supply Current Delta, TTL input level
For input under test
A
VIN = VDD - 2.1V
For other inputs
1.6
mA
VIN = VDD or VSS
VDD = 5.5V
CIN
Input capacitance 10
 = 1MHz @ 0V
15
pF
15
pF
1100
-1300
mV
mV
VOH
+1200
VOH
-1400
mV
VDD from 4.5V to 5.5V
COUT
Output capacitance10
 = 1MHz @ 0V
VDD from 4.5V to 5.5V
VOLP
Low level VSS bounce noise11
VOLV
VOHP
VOHV
High level VDD bounce noise11
VIN = 3.0V, VIL = 0.0V,
TA=+25oC,
VDD = 5.0V
See figure "Quiet Output Under
Test"
mV
Notes:
1. All specifications valid for radiation dose  1E5 rad(Si) per MIL-STD-883, Method 1019.
2. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are
guaranteed to VIH(min) and VIL(max).
3. Not more than one output may be shorted at a time for maximum duration of one second.
4. Supplied as a design limit, but not guaranteed or tested.
5. Per MIL-PRF-38535, for current density  5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765
pF-MHz.
6. Transmission driving tests are performed at VDD = 5.5V, only one output loaded at a time with a duration not to exceed 2ms. The test is guaranteed, if not tested,
for VIN=VIH minimum or VIL maximum.
7. Guaranteed by characterization.
8. Power does not include power contribution of any CMOS output sink current.
9. Power dissipation specified per switching output.
10.Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS
at frequency of 1MHz and a signal amplitude of 50mV rms maximum.
11. This test is for qualification only. VSS and VDD bounce tests are performed on a non-switching (quiescent) output and are used to measure the magnitude of induced
noise caused by other simultaneously switching outputs. The test is performed on a low noise bench test fixture.
AC ELECTRICAL CHARACTERISTICS1
(VDD = 5V 10%, -55C < TC < +125C)
SYMBOL
PARAMETER
MIN
MAX
UNIT
tPLH
Propagation delay CPn to On
2
10
ns
tPHL
Propagation delay CPn to On
2
10
ns
tPZL
Output enable time OEn to On
2
9.0
ns
tPZH
Output enable time OEn to On
2
9.0
ns
tPLZ
Output disable time OEn to On high impedance
2
9.0
ns
tPHZ
Output disable time OEn to On high impedance
2
9.0
ns
100
MHz
tFMAX2
Maximum clock frequency
tS
Setup time high or low In to CPn
1.5
ns
tH
Hold time high or low In from CPn
0.5
ns
tW
Clock pulse, high or low CPn
5.0
ns
tSKEW3
Output-to-output skew
1.25
ns
tDSKEW3
Differential skew between outputs
1.5
ns
Part-to-part output skew between outputs on multiple devices under
identical system conditions.
500
ps
tDSKEWPP3,5
Notes:
1. All specifications valid for radiation dose  1E5 rad(Si) per MIL-STD-883, Method 1019.
2. Verified by functional testing.
3. Output skew is defined as a comparison of any two output transitions high-to-low vs. high-to-low and low-to-high vs low-to-high.
4. Differential skew is defined as a comparison of any two output transitions high-to-low vs. low-to-high and low-to-high vs high-to low.
5. Guaranteed by characterization, but not tested.
Test Load or Equivalent1
VDD
VDD
100
•
•
40pF
100
Notes
1. Equivalent test circuit means that DUT performance will be correlated and remain guaranteed to the applicable test circuit, above, whenever a test platform
change necessitates a deviation from the applicable test circuit.
8
Propagation Delay
3.0V
1.5V
0V
CPn
tPHL
tPLH
VOH
VDD/2
VOL
Output
Enable Disable Times
OEn
tPZL
5V Output
Normally Low
5V Output
Normally High
3.0V
1.5V
0V
tPLZ
VDD/2-0.2
.2VDD + .2V
tPHZ
tPZH
.8VDD - .2V
VDD/2+0.2
Bounce Noise
VOH
Active Outputs
VOL
Quiet Outputs
Under Test
VOHP
VOLP
VOL
VOLV
VOH
VOHV
VDD/2
.2VDD
.8VDD
VDD/2
Setup and Hold Measurements
3.0V
1.5V
0.0V
Data Input
tS
tH
3.0V
1.5V
0.0V
CPn Input
tW
PACKAGE
NOTE:
1. Seal ring is connected to VSS.
2. Units are in inches.
3. All exposed metalized areas must be gold plated 100 to 225 microinches thick. Dyer electroplated nickel
undercoating 100 to 350 microinches per MIL-PRF-38535.
Figure 1. 48-Lead Flatpack
ORDERING INFORMATION
UT54ACTQ16374: SMD
5962 R 06245 **
*
*
*
Lead Finish: (NOTES 1 & 2)
(C) = Gold
(A) = Hot solder dip
(X) = Factory option (gold or solder)
Case Outline:
(X) = 48 lead BB FP
Class Designator:
(Q) = Class Q
(V) = Class V
Device Type
(01) = 16-bit D Flip-Flop (4.5V - 5.5V)
Drawing Number: 06245
Total Dose: (NOTE 3)
(R) = 1E5 rad(Si)
Federal Stock Class Designator: No options
Notes:
1. Lead finish (A,C, or X) must be specified.
2. If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3.Total dose radiation must be specified when ordering. QML Q not available without radiation hardening.
UT54ACTQ16374
UT54 **** *****
* * *
Lead Finish: (NOTES 1 & 2)
(A) = Hot solder dip
(C)
= Gold
(X) = Factory option (gold or solder)
Screening: (NOTES 3 & 4)
(C) = Mil Temp
(P)
= Prototype
Package Type:
(U) = 48-lead BB FP
Part Number:16374
(16374) = 16-bit D Flip-Flop
I/O Type:
(ACTQ)=
TTL compatible I/O Level
Aeroflex Core Part Number
Notes:
1. Lead finish (A, C, or X) must be specified.
2. If an “X” is specified when ordering, then the part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3. Prototype flow per Aeroflex Manufacturing Flows Document. Tested at 25C only. Lead finish is Gold "C" only. Radiation neither tested nor guaranteed.
4. Military Temperature Range flow per Aeroflex Manufacturing Flows Document. Devices are tested at -55C, room temp, and 125C. Radiation neither
tested nor guaranteed.
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Advanced Datasheet - Product In Development
Preliminary Datasheet - Shipping Prototype
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Aeroflex Colorado Springs, Inc., reserves the right to make
changes to any products and services herein at any time
without notice. Consult Aeroflex or an authorized sales
representative to verify that the information in this data sheet
is current before using this product. Aeroflex does not assume
any responsibility or liability arising out of the application or
use of any product or service described herein, except as
expressly agreed to in writing by Aeroflex; nor does the
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