INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT4515 4-to-16 line decoder/demultiplexer with input latches; inverting Product specification File under Integrated Circuits, IC06 September 1993 Philips Semiconductors Product specification 4-to-16 line decoder/demultiplexer with input latches; inverting 74HC/HCT4515 The 74HC/HCT4515 are 4-to-16 line decoders/demultiplexers having four binary weighted address inputs (A0 to A3) with latches, a latch enable input (LE), and an active LOW enable input (E). The 16 inverting outputs (Q0 to Q15) are mutually exclusive active LOW. When LE is HIGH, the selected output is determined by the data on An. When LE goes LOW, the last data present at An are stored in the latches and the outputs remain stable. When E is LOW, the selected output, determined by the contents of the latch, is LOW. When E is HIGH, all outputs are HIGH. The enable input (E) does not affect the state of the latch. FEATURES • Inverting outputs • Output capability: standard • ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT4515 are high-speed Si-gate CMOS devices and are pin compatible with “4515” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. When the “4515” is used as a demultiplexer, E is the data input and A0 to A3 are the address inputs. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL PARAMETER CONDITIONS tPHL/ tPLH propagation delay An to Qn CL = 15 pF; VCC = 5 V CI input capacitance CPD power dissipation capacitance per package notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi +∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. September 1993 2 UNIT HC HCT 25 26 ns 3.5 3.5 pF 44 46 pF Philips Semiconductors Product specification 4-to-16 line decoder/demultiplexer with input latches; inverting 74HC/HCT4515 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1 LE latch enable input (active HIGH) 2, 3, 21, 22 A0 to A3 address inputs 11, 9, 10, 8, 7, 6, 5, 4,18, 17, 20, 19, 14, 13, 16, 15 Q0 to Q15 multiplexer outputs (active LOW) 12 GND ground (0 V) 23 E enable input (active LOW) 24 VCC positive supply voltage Fig.1 Pin configuration. September 1993 Fig.2 Logic symbol. 3 Fig.3 IEC logic symbol. Philips Semiconductors Product specification 4-to-16 line decoder/demultiplexer with input latches; inverting 74HC/HCT4515 APPLICATIONS • Digital multiplexing • Address decoding • Hexadecimal/BCD decoding Fig.4 Functional diagram. FUNCTION TABLE INPUTS E OUTPUTS A0 A1 A2 A3 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15 H X X X X H H H H H H H H H H H H H H H H L L L L L H L H L L H H L L L L L L L L L H H H H L H H H H L H H H H L H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H L L L L L H L H L L H H H H H H L L L L H H H H H H H H H H H H H H H H L H H H H L H H H H L H H H H L H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H L L L L L H L H L L H H L L L L H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H L H H H H L H H H H L H H H H L H H H H H H H H H H H H H H H H L L L L L H L H L L H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H H L H H H H L H H H H L H H H H L Notes 1. LE = HIGH H = HIGH voltage level L = LOW voltage level X = don’t care September 1993 4 Philips Semiconductors Product specification 4-to-16 line decoder/demultiplexer with input latches; inverting Fig.5 Logic diagram. September 1993 5 74HC/HCT4515 Philips Semiconductors Product specification 4-to-16 line decoder/demultiplexer with input latches; inverting 74HC/HCT4515 DC CHARACTERISTICS FOR 74HC For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HC SYMBOL PARAMETER +25 min. typ. max. −40 to +85 −40 to +125 min. min. max. UNIT V WAVEFORMS CC (V) max. tPHL/ tPLH propagation delay An to Qn 80 29 23 250 50 43 315 63 54 375 75 64 ns 2.0 4.5 6.0 Fig.6 tPHL/ tPLH propagation delay LE to Qn 66 24 19 225 45 38 280 56 48 340 68 58 ns 2.0 4.5 6.0 Fig.6 tPHL/ tPLH propagation delay E to Qn 50 18 14 175 35 30 220 44 37 265 53 45 ns 2.0 4.5 6.0 Fig.6 tTHL/ tTLH output transition time 19 7 6 75 15 13 95 19 16 110 22 19 ns 2.0 4.5 6.0 Fig.6 tW latch enable pulse width 75 HIGH 15 13 14 5 4 95 19 16 110 22 19 ns 2.0 4.5 6.0 Fig.7 tsu set-up time An to LE 90 18 15 28 10 8 115 23 20 135 27 23 ns 2.0 4.5 6.0 Fig.7 th hold time An to LE 0 0 0 −11 −4 −3 0 0 0 0 0 0 ns 2.0 4.5 6.0 Fig.7 September 1993 6 Philips Semiconductors Product specification 4-to-16 line decoder/demultiplexer with input latches; inverting 74HC/HCT4515 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: standard ICC category: MSI Note to HCT types The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT UNIT LOAD COEFFICIENT An LE E 0.65 1.40 1.00 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HCT SYMBOL PARAMETER −40 to+85 +25 min. typ. max. min. max. −40 to +125 min. UNIT V WAVEFORMS CC (V) max. tPHL/ tPLH propagation delay An to Qn 30 55 69 83 ns 4.5 Fig.6 tPHL/ tPLH propagation delay LE to Qn 29 50 63 75 ns 4.5 Fig.6 tPHL/ tPLH propagation delay E to Qn 18 40 50 60 ns 4.5 Fig.6 tTHL/ tTLH output transition time 7 15 19 22 ns 4.5 Fig.6 tW latch enable pulse width HIGH 16 3 20 24 ns 4.5 Fig.7 tsu set-up time An to LE 18 9 23 27 ns 4.5 Fig.7 th hold time An to LE 3 −2 3 3 ns 4.5 Fig.7 September 1993 7 Philips Semiconductors Product specification 4-to-16 line decoder/demultiplexer with input latches; inverting 74HC/HCT4515 AC WAVEFORMS (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.6 Waveforms showing the input (An, LE, E) to output (Qn) propagation delays and the output transition times. The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.7 Waveforms showing the minimum pulse width of the latch enable input (LE) and the set-up and hold times for LE to An. Set-up and hold times are shown as positive values but may be specified as negative values. PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. September 1993 8