PHILIPS 74LV132D

74LV132
Quad 2-input NAND Schmitt trigger
Rev. 04 — 12 November 2007
Product data sheet
1. General description
The 74LV132 is a low-voltage Si-gate CMOS device that is pin and function compatible
with 74HC132 and 74HCT132.
The 74LV132 contains four 2-input NAND gates which accept standard input signals.
They are capable of transforming slowly changing input signals into sharply defined,
jitter-free output signals.
The gate switches at different points for positive and negative-going signals. The
difference between the positive voltage VT+ and the negative voltage VT− is defined as the
input hysteresis voltage VH.
2. Features
■
■
■
■
■
Wide operating voltage: 1.0 V to 5.5 V
Optimized for low voltage applications: 1.0 V to 3.6 V
Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 °C
Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and
Tamb = 25 °C
■ ESD protection:
◆ HBM JESD22-A114E exceeds 2000 V
◆ MM JESD22-A115-A exceeds 200 V
■ Multiple package options
■ Specified from −40 °C to +85 °C and from −40 °C to +125 °C
3. Applications
■ Wave and pulse shapers for highly noisy environments
■ Astable multivibrators
■ Monostable multivibrators
74LV132
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
4. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range
Name
Description
Version
74LV132N
−40 °C to +125 °C
DIP14
plastic dual in-line package; 14 leads (300 mil)
SOT27-1
74LV132D
−40 °C to +125 °C
SO14
plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
74LV132DB
−40 °C to +125 °C
SSOP14
plastic shrink small outline package; 14 leads;
body width 5.3 mm
SOT337-1
74LV132PW
−40 °C to +125 °C
TSSOP14
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
74LV132BQ
−40 °C to +125 °C
DHVQFN14 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 14 terminals;
body 2.5 × 3 × 0.85 mm
SOT762-1
5. Functional diagram
1
1A
1Y
2
3
1B
1
&
3
&
6
&
8
&
11
2
4
2A
2Y
5
9
4
5
9
3A
3Y
10
6
2B
10
8
3B
12
13
12
4A
mna408
4Y
13
11
Y
4B
B
mna407
Fig 1. Logic symbol
mna409
Fig 2. IEC logic symbol
74LV132_4
Product data sheet
A
Fig 3. Logic diagram (one gate)
© NXP B.V. 2007. All rights reserved.
Rev. 04 — 12 November 2007
2 of 17
74LV132
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
6. Pinning information
6.1 Pinning
1
1A
terminal 1
index area
2
13 4B
12 4A
1Y
3
2A
4
2B
5
2Y
6
9
3A
GND
7
8
3Y
132
11 4Y
10 3B
12 4A
2A
4
2B
5
2Y
6
11 4Y
VCC
(1)
10 3B
9
8
1B
13 4B
3
3Y
14 VCC
2
1Y
7
1
1B
GND
1A
14 VCC
74LV132
3A
001aah099
Transparent top view
(1) The die substrate is attached to the exposed die pad
using conductive die attach material. It can not be
used as a supply pin or input.
001aac203
Fig 4. Pin configuration DIP14, SO14 and (T)SSOP14
Fig 5. Pin configuration DHVQFN14
6.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
1A
1
data input
1B
2
data input
1Y
3
data output
2A
4
data input
2B
5
data input
2Y
6
data output
GND
7
ground (0 V)
3Y
8
data output
3A
9
data input
3B
10
data input
4Y
11
data output
4A
12
data input
4B
13
data input
VCC
14
supply voltage
74LV132_4
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 04 — 12 November 2007
3 of 17
74LV132
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
7. Functional description
Table 3.
Function table
H = HIGH voltage level; L = LOW voltage level.
Input
Output
nA
nB
nY
L
L
H
L
H
H
H
L
H
H
H
L
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
Conditions
Min
Max
Unit
−0.5
+7.0
V
-
±20
mA
-
±50
mA
input clamping current
VI < −0.5 V or VI > VCC + 0.5 V
[1]
IOK
output clamping current
VO < −0.5 V or VO > VCC + 0.5 V
[1]
IO
output current
VO = −0.5 V to (VCC + 0.5 V)
-
±25
mA
ICC
supply current
-
50
mA
IGND
ground current
−50
-
mA
Tstg
storage temperature
−65
+150
°C
Ptot
total power dissipation
IIK
Tamb = −40 °C to +125 °C
DIP14 package
[2]
-
750
mW
SO14 package
[3]
-
500
mW
(T)SSOP14 package
[4]
-
500
mW
DHVQFN14 package
[5]
-
500
mW
[1]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2]
Ptot derates linearly with 12 mW/K above 70 °C.
[3]
Ptot derates linearly with 8 mW/K above 70 °C.
[4]
Ptot derates linearly with 5.5 mW/K above 60 °C.
[5]
Ptot derates linearly with 4.5 mW/K above 60 °C.
74LV132_4
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 04 — 12 November 2007
4 of 17
74LV132
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
9. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply
Conditions
voltage[1]
Min
Typ
Max
Unit
1.0
3.3
5.5
V
VI
input voltage
0
-
VCC
V
VO
output voltage
0
-
VCC
V
Tamb
ambient temperature
−40
+25
+125
°C
[1]
The static characteristics are guaranteed from VCC = 1.2 V to VCC = 5.5 V, but LV devices are guaranteed to function down to
VCC = 1.0 V (with input levels GND or VCC).
10. Static characteristics
Table 6.
Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
−40 °C to +85 °C
Min
VOH
HIGH-level output voltage
LOW-level output voltage
VOL
Typ[1]
Max
−40 °C to +125 °C Unit
Min
Max
VI = VIH or VIL
lO = −100 µA; VCC = 1.2 V
-
1.2
-
-
-
V
lO = −100 µA; VCC = 2.0 V
1.8
2.0
-
1.8
-
V
lO = −100 µA; VCC = 2.7 V
2.5
2.7
-
2.5
-
V
lO = −100 µA; VCC = 3.0 V
2.8
3.0
-
2.8
-
V
lO = −100 µA; VCC = 4.5 V
4.3
4.5
-
4.3
-
V
lO = −6 mA; VCC = 3.0 V
2.4
2.82
-
2.2
-
V
lO = −12 mA; VCC = 4.5 V
3.6
4.2
-
3.5
-
V
VI = VIH or VIL
IO = 100 µA; VCC = 1.2 V
-
0
-
-
-
V
IO = 100 µA; VCC = 2.0 V
-
0
0.2
-
0.2
V
IO = 100 µA; VCC = 2.7 V
-
0
0.2
-
0.2
V
IO = 100 µA; VCC = 3.0 V
-
0
0.2
-
0.2
V
IO = 100 µA; VCC = 4.5 V
-
0
0.2
-
0.2
V
IO = 6 mA; VCC = 3.0 V
-
0.25
0.40
-
0.50
V
IO = 12 mA; VCC = 4.5 V
-
0.35
0.55
-
0.65
V
II
input leakage current
VI = VCC or GND;
VCC = 5.5 V
-
-
1.0
-
1.0
µA
ICC
supply current
VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
20.0
-
40
µA
∆ICC
additional supply current
per input; VI = VCC − 0.6 V;
VCC = 2.7 V to 3.6 V
-
-
500
-
850
µA
CI
input capacitance
-
3.5
-
-
-
pF
[1]
Typical values are measured at Tamb = 25 °C.
74LV132_4
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 04 — 12 November 2007
5 of 17
74LV132
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
11. Dynamic characteristics
Table 7.
Dynamic characteristics
GND = 0 V; For test circuit see Figure 7.
Symbol Parameter
propagation delay
tpd
−40 °C to +85 °C
Conditions
power dissipation
capacitance
Unit
Min
Max
Min
Max
VCC = 1.2 V
-
65
-
-
-
ns
VCC = 2.0 V
-
18
34
-
43
ns
24
-
30
ns
[2]
nA, nB to nY; see Figure 6
VCC = 2.7 V
CPD
−40 °C to +125 °C
Typ[1]
-
15
VCC = 3.0 V to 3.6 V; CL = 15 pF
[3]
-
10
-
-
-
ns
VCC = 3.0 V to 3.6 V
[3]
-
12
20
-
25
ns
VCC = 4.5 V to 5.5 V
[3]
-
9.0
14
-
17
ns
CL = 50 pF; fi = 1 MHz;
VI = GND to VCC
[4]
-
24
-
-
-
pF
[1]
All typical values are measured at Tamb = 25 °C.
[2]
tpd is the same as tPLH and tPHL.
[3]
Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V).
[4]
CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz, fo = output frequency in MHz
CL = output load capacitance in pF
VCC = supply voltage in V
N = number of inputs switching
Σ(CL × VCC2 × fo) = sum of the outputs.
12. Waveforms
VI
VM
nA, nB input
GND
t PHL
t PLH
VOH
VM
nY output
VOL
001aaa662
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 6. The input (nA, nB) to output (nY) propagation delays
74LV132_4
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 04 — 12 November 2007
6 of 17
74LV132
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
Table 8.
Measurement points
Supply voltage
Input
Output
VCC
VM
VM
< 2.7 V
0.5VCC
0.5VCC
2.7 V to 3.6 V
1.5 V
1.5 V
≥ 4.5 V
0.5VCC
0.5VCC
VCC
PULSE
GENERATOR
VI
VO
D.U.T.
CL
50 pF
RT
RL
1 kΩ
001aaa663
Test data is given in Table 9.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
Fig 7. Load circuit for switching times
Table 9.
Test data
Supply voltage
Input
VCC
VI
tr, tf
< 2.7 V
VCC
≤ 2.5 ns
2.7 V to 3.6 V
2.7 V
≤ 2.5 ns
≥ 4.5 V
VCC
≤ 2.5 ns
13. Transfer characteristics
Table 10. Transfer characteristics
GND = 0 V; For test circuit see Figure 7.
Symbol Parameter
VT+
positive-going
threshold voltage
Conditions
−40 °C to +85 °C
Unit
Min
Max
Min
Max
VCC = 1.2 V
-
0.70
-
-
-
V
VCC = 2.0 V
0.8
1.10
1.4
0.8
1.4
V
VCC = 2.7 V
1.0
1.45
2.0
1.0
2.0
V
VCC = 3.0 V
1.2
1.60
2.2
1.2
2.2
V
VCC = 3.6 V
1.5
1.95
2.4
1.5
2.4
V
VCC = 4.5 V
1.7
2.50
3.2
1.7
3.2
V
VCC = 5.5 V
2.1
3.00
3.9
2.1
3.9
V
see Figure 6
74LV132_4
Product data sheet
−40 °C to +125 °C
Typ[1]
© NXP B.V. 2007. All rights reserved.
Rev. 04 — 12 November 2007
7 of 17
74LV132
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
Table 10. Transfer characteristics …continued
GND = 0 V; For test circuit see Figure 7.
Symbol Parameter
VT−
negative-going
threshold voltage
hysteresis voltage
VH
[1]
−40 °C to +85 °C
Conditions
Min
Typ[1]
Max
−40 °C to +125 °C
Min
Unit
Max
see Figure 6
VCC = 1.2 V
-
0.34
-
-
-
V
VCC = 2.0 V
0.3
0.65
0.9
0.3
0.9
V
VCC = 2.7 V
0.4
0.90
1.4
0.4
1.4
V
VCC = 3.0 V
0.6
1.05
1.5
0.6
1.5
V
VCC = 3.6 V
0.8
1.30
1.8
0.8
1.8
V
VCC = 4.5 V
0.9
1.60
2.0
0.9
2.0
V
VCC = 5.5 V
1.2
2.00
2.6
1.2
2.6
V
(VT+ − VT−); see Figure 6
VCC = 1.2 V
-
0.3
-
-
-
V
VCC = 2.0 V
0.2
0.55
0.8
0.2
0.8
V
VCC = 2.7 V
0.3
0.60
1.1
0.3
1.1
V
VCC = 3.0 V
0.4
0.65
1.2
0.4
1.2
V
VCC = 3.6 V
0.4
0.70
1.2
0.4
1.2
V
VCC = 4.5 V
0.4
0.80
1.4
0.4
1.4
V
VCC = 5.5 V
0.6
1.00
1.5
0.6
1.5
V
All typical values are measured at Tamb = 25 °C.
14. Waveforms transfer characteristics
VT+
VO
VI
VH
VT−
VO
VI
VH
VT−
VT+
Fig 8. Transfer characteristic
mna207
mna208
VT+ and VT− limits at 70 % and 20 %.
Fig 9. Definition of VT+, VT− and VH
74LV132_4
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 04 — 12 November 2007
8 of 17
74LV132
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
001aaa659
12
001aaa660
100
ICC
(µA)
ICC
(µA)
80
8
60
40
4
20
0
0
0
0.3
0.6
0.9
1.2
0
0.4
VI (V)
0.8
1.2
1.6
2
VI (V)
VCC = 1.2 V.
VCC = 2.0 V.
Fig 10. Typical 74LV132 transfer characteristics
Fig 11. Typical 74LV132 transfer characteristics
001aaa661
300
ICC
(µA)
200
100
0
0
0.6
1.2
1.8
2.4
3
VI (V)
VCC = 3.0 V.
Fig 12. Typical 74LV132 transfer characteristics
74LV132_4
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 04 — 12 November 2007
9 of 17
74LV132
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
15. Package outline
DIP14: plastic dual in-line package; 14 leads (300 mil)
SOT27-1
ME
seating plane
D
A2
A
A1
L
c
e
Z
w M
b1
(e 1)
b
MH
8
14
pin 1 index
E
1
7
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
min.
A2
max.
b
b1
c
D (1)
E (1)
e
e1
L
ME
MH
w
Z (1)
max.
mm
4.2
0.51
3.2
1.73
1.13
0.53
0.38
0.36
0.23
19.50
18.55
6.48
6.20
2.54
7.62
3.60
3.05
8.25
7.80
10.0
8.3
0.254
2.2
inches
0.17
0.02
0.13
0.068
0.044
0.021
0.015
0.014
0.009
0.77
0.73
0.26
0.24
0.1
0.3
0.14
0.12
0.32
0.31
0.39
0.33
0.01
0.087
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT27-1
050G04
MO-001
SC-501-14
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-13
Fig 13. Package outline SOT27-1 (DIP14)
74LV132_4
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 04 — 12 November 2007
10 of 17
74LV132
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
D
E
A
X
c
y
HE
v M A
Z
8
14
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
7
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
0.01
0.019 0.0100 0.35
0.014 0.0075 0.34
0.16
0.15
0.010 0.057
inches 0.069
0.004 0.049
0.05
0.244
0.039
0.041
0.228
0.016
0.028
0.024
0.01
0.01
0.028
0.004
0.012
θ
o
8
o
0
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT108-1
076E06
MS-012
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Fig 14. Package outline SOT108-1 (SO14)
74LV132_4
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 04 — 12 November 2007
11 of 17
74LV132
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm
D
SOT337-1
E
A
X
c
y
HE
v M A
Z
8
14
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
7
1
detail X
w M
bp
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
2
0.21
0.05
1.80
1.65
0.25
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
0.65
7.9
7.6
1.25
1.03
0.63
0.9
0.7
0.2
0.13
0.1
1.4
0.9
8
o
0
o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT337-1
REFERENCES
IEC
JEDEC
JEITA
MO-150
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Fig 15. Package outline SOT337-1 (SSOP14)
74LV132_4
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 04 — 12 November 2007
12 of 17
74LV132
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
E
D
A
X
c
y
HE
v M A
Z
8
14
Q
(A 3)
A2
A
A1
pin 1 index
θ
Lp
L
1
7
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.72
0.38
8
o
0
o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT402-1
REFERENCES
IEC
JEDEC
JEITA
MO-153
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
Fig 16. Package outline SOT402-1 (TSSOP14)
74LV132_4
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 04 — 12 November 2007
13 of 17
74LV132
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
SOT762-1
14 terminals; body 2.5 x 3 x 0.85 mm
A
B
D
A
A1
E
c
detail X
terminal 1
index area
terminal 1
index area
C
e1
e
2
6
y
y1 C
v M C A B
w M C
b
L
1
7
Eh
e
14
8
13
9
Dh
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
mm
A(1)
max.
A1
b
1
0.05
0.00
0.30
0.18
c
D (1)
Dh
E (1)
Eh
0.2
3.1
2.9
1.65
1.35
2.6
2.4
1.15
0.85
e
0.5
e1
L
v
w
y
y1
2
0.5
0.3
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT762-1
---
MO-241
---
EUROPEAN
PROJECTION
ISSUE DATE
02-10-17
03-01-27
Fig 17. Package outline SOT762-1 (DHVQFN14)
74LV132_4
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 04 — 12 November 2007
14 of 17
74LV132
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
16. Abbreviations
Table 11.
Abbreviations
Acronym
Description
CMOS
Complementary Metal Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
TTL
Transistor-Transistor Logic
17. Revision history
Table 12.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74LV132_4
20071112
Product data sheet
-
74LV132_3
Modifications:
•
The format of this data sheet has been redesigned to comply with the new identity guidelines
of NXP Semiconductors.
•
•
•
•
Legal texts have been adapted to the new company name where appropriate.
Section 4: DHVQFN14 package added.
Section 9: derating values added for DHVQFN14 package.
Section 15: outline drawing added for DHVQFN14 package.
74LV132_3
20040415
Product specification
-
74LV132_2
74LV132_2
19980428
Product specification
-
74LV132_1
74LV132_1
19970204
Product specification
-
-
74LV132_4
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 04 — 12 November 2007
15 of 17
74LV132
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
18. Legal information
18.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
18.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
18.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
18.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
19. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: [email protected]
74LV132_4
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 04 — 12 November 2007
16 of 17
74LV132
NXP Semiconductors
Quad 2-input NAND Schmitt trigger
20. Contents
1
2
3
4
5
6
6.1
6.2
7
8
9
10
11
12
13
14
15
16
17
18
18.1
18.2
18.3
18.4
19
20
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Transfer characteristics. . . . . . . . . . . . . . . . . . . 7
Waveforms transfer characteristics . . . . . . . . . 8
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 16
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Contact information. . . . . . . . . . . . . . . . . . . . . 16
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 12 November 2007
Document identifier: 74LV132_4