74ALVC32 Quad 2-input OR gate Rev. 02 — 10 December 2007 Product data sheet 1. General description The 74ALVC32 is a quad 2-input OR gate. Schmitt trigger action on all inputs makes the device tolerant of slow rise and fall times. 2. Features ■ ■ ■ ■ ■ ■ ■ Wide supply voltage range from 1.65 V to 3.6 V 3.6 V tolerant inputs/outputs CMOS low power consumption Direct interface with TTL levels (2.7 V to 3.6 V) Power-down mode Latch-up performance exceeds 250 mA Complies with JEDEC standards: ◆ JESD8-7 (1.65 V to 1.95 V) ◆ JESD8-5 (2.3 V to 2.7 V) ◆ JESD8B/JESD36 (2.7 V to 3.6 V) ■ ESD protection: ◆ HBM JESD22-A114E exceeds 2000 V ◆ MM JESD22-A115-A exceeds 200 V 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74ALVC32D −40 °C to +85 °C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 74ALVC32PW −40 °C to +85 °C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 74ALVC32BQ −40 °C to +85 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 × 3 × 0.85 mm SOT762-1 74ALVC32 NXP Semiconductors Quad 2-input OR gate 4. Functional diagram 1 ≥1 3 ≥1 6 ≥1 8 ≥1 11 2 4 1 1A 2 1B 4 2A 5 2B 9 3A 10 3B 12 4A 13 4B 1Y 3 5 2Y 6 9 10 3Y 8 4Y 11 12 13 mna242 mna243 Fig 1. Logic symbol Fig 2. IEC logic symbol A Y B mna241 Fig 3. Logic diagram (one gate) 5. Pinning information 14 VCC 1B 2 13 4B terminal 1 index area 1A 1 1 1A 2B 5 2Y 6 9 3A GND 7 8 3Y 32 11 4Y 10 3B 1Y 12 4A 2A 4 32 11 4Y 2B 5 GND(1) 10 3B 2Y 6 9 8 4 13 4B 3 3Y 2A 2 7 3 1B GND 12 4A 1Y 14 VCC 5.1 Pinning 3A 001aad102 Transparent top view 001aad101 (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 4. Pin configuration SO14 and TSSOP14 Fig 5. Pin configuration DHVQFN14 74ALVC32_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 10 December 2007 2 of 13 74ALVC32 NXP Semiconductors Quad 2-input OR gate 5.2 Pin description Table 2. Pin description Symbol Pin Description nA 1, 4, 9, 12 data input nB 2, 5, 10, 13 data input nY 3, 6, 8, 11 data output VCC 14 supply voltage GND 7 ground (0 V) 6. Functional description Table 3. Function table[1] Input nA Input nB Output nY L L L L H H H L H H H H [1] H = HIGH voltage level L = LOW voltage level 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current output voltage VO Conditions Min −0.5 +4.6 V VI < 0 V −50 - mA −0.5 +4.6 V - ±50 mA VO > VCC or VO < 0 V output HIGH or LOW state [1] [2] output 3-state power-down mode, VCC = 0 V [2] Unit −0.5 VCC + 0.5 V −0.5 +4.6 V −0.5 +4.6 V - ±50 mA IO output current ICC supply current - 100 mA IGND ground current −100 - mA Tstg storage temperature −65 +150 °C - 500 mW total power dissipation Ptot VO = 0 V to VCC Max Tamb = −40 °C to +85 °C [3] [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] When VCC = 0 V (power-down mode), the output voltage can be 3.6 V in normal operation. [3] For SO14 packages: above 70 °C derate linearly with 8 mW/K. For TSSOP14 packages: above 60 °C derate linearly with 5.5 mW/K. For DHVQFN14 packages: above 60 °C derate linearly with 4.5 mW/K. 74ALVC32_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 10 December 2007 3 of 13 74ALVC32 NXP Semiconductors Quad 2-input OR gate 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VCC Conditions Min Max Unit supply voltage 1.65 3.6 V VI input voltage 0 3.6 V VO output voltage Tamb ambient temperature ∆t/∆V input transition rise and fall rate output HIGH or LOW state 0 VCC V output 3-state 0 3.6 V power-down mode; VCC = 0 V 0 3.6 V in free air −40 +85 °C VCC = 1.65 V to 2.7 V 0 20 ns/V VCC = 2.7 V to 3.6 V 0 10 ns/V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter −40 °C to +85 °C Conditions Min VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage Unit Max 0.65 × VCC - - V VCC = 2.3 V to 2.7 V 1.7 - - V VCC = 2.7 V to 3.6 V 2.0 - - V VCC = 1.65 V to 1.95 V - - VCC = 2.3 V to 2.7 V - - 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 V VCC − 0.2 - - V VCC = 1.65 V to 1.95 V 0.35 × VCC V VI = VIH or VIL IO = −100 µA; VCC = 1.65 V to 3.6 V VOL Typ[1] IO = −6 mA; VCC = 1.65 V 1.25 1.51 - V IO = −12 mA; VCC = 2.3 V 1.8 2.10 - V IO = −18 mA; VCC = 2.3 V 1.7 2.01 - V IO = −12 mA; VCC = 2.7 V 2.2 2.53 - V IO = −18 mA; VCC = 3.0 V 2.4 2.76 - V IO = −24 mA; VCC = 3.0 V 2.2 2.68 - V - - 0.2 V VI = VIH or VIL IO = 100 µA; VCC = 1.65 V to 3.6 V IO = 6 mA; VCC = 1.65 V - 0.11 0.3 V IO = 12 mA; VCC = 2.3 V - 0.17 0.4 V IO = 18 mA; VCC = 2.3 V - 0.25 0.6 V IO = 12 mA; VCC = 2.7 V - 0.16 0.4 V IO = 18 mA; VCC = 3.0 V - 0.23 0.4 V IO = 24 mA; VCC = 3.0 V - 0.30 0.55 V II input leakage current VCC = 3.6 V; VI = 3.6 V or GND - ±0.1 ±5 µA IOFF power-off leakage current VCC = 0 V; VI or VO = 0 V to 3.6 V - ±0.1 ±10 µA 74ALVC32_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 10 December 2007 4 of 13 74ALVC32 NXP Semiconductors Quad 2-input OR gate Table 6. Static characteristics …continued At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter −40 °C to +85 °C Conditions Unit Min Typ[1] Max ICC supply current VCC = 3.6 V; VI = VCC or GND; IO = 0 A - 0.2 10 µA ∆ICC additional supply current per input pin; VCC = 3.0 V to 3.6 V; VI = VCC − 0.6 V; IO = 0 A - 5 750 µA CI input capacitance - 3.5 - pF [1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 °C. 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 7. Symbol Parameter propagation delay tpd −40 °C to +85 °C Conditions CP to Qn; see Figure 6 1.0 2.8 4.7 ns 1.0 2.0 3.1 ns VCC = 2.7 V 1.0 2.2 2.9 ns 1.0 2.0 2.8 ns - 25 - pF per gate; VI = GND to VCC; VCC = 3.3 V [1] Typical values are measured at Tamb = 25 °C [2] tpd is the same as tPHL and tPLH. [3] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in Volts N = number of inputs switching Σ(CL × VCC2 × fo) = sum of the outputs 74ALVC32_2 Product data sheet Max VCC = 2.3 V to 2.7 V VCC = 3.0 V to 3.6 V power dissipation capacitance Typ[1] [2] VCC = 1.65 V to 1.95 V CPD Unit Min [3] © NXP B.V. 2007. All rights reserved. Rev. 02 — 10 December 2007 5 of 13 74ALVC32 NXP Semiconductors Quad 2-input OR gate 11. Waveforms VI VM nA, nB input GND t PHL t PLH VM nY output mna244 Measurement points are given in Table 8. Fig 6. Inputs nA, nB to output nY propagation delay times Table 8. Measurement points Supply voltage VCC Input VI VM 1.65 V to 1.95 V VCC 0.5VCC 2.3 V to 2.7 V VCC 0.5VCC 2.7 V 2.7 V 1.5 V 3.0 V to 3.6 V 2.7 V 1.5 V 74ALVC32_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 10 December 2007 6 of 13 74ALVC32 NXP Semiconductors Quad 2-input OR gate VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VEXT VCC VI RL VO G DUT RT CL RL 001aae331 Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 7. Test circuitry for switching times Table 9. Test data Supply voltage VCC Input Load VEXT VI tr, tf CL RL tPLH, tPHL tPLZ, tPZL tPHZ, tPZH 1.65 V to 1.95 V VCC ≤ 2.0 ns 30 pF 1 kΩ open 2 × VCC GND 2.3 V to 2.7 V VCC ≤ 2.0 ns 30 pF 500 Ω open 2 × VCC GND 2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 6V GND 3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 6V GND 74ALVC32_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 10 December 2007 7 of 13 74ALVC32 NXP Semiconductors Quad 2-input OR gate 12. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.010 0.057 inches 0.069 0.004 0.049 0.05 0.244 0.039 0.041 0.228 0.016 0.028 0.024 0.01 0.01 0.028 0.004 0.012 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 8. Package outline SOT108-1 (SO14) 74ALVC32_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 10 December 2007 8 of 13 74ALVC32 NXP Semiconductors Quad 2-input OR gate TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC JEITA MO-153 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 9. Package outline SOT402-1 (TSSOP14) 74ALVC32_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 10 December 2007 9 of 13 74ALVC32 NXP Semiconductors Quad 2-input OR gate DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT762-1 14 terminals; body 2.5 x 3 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 6 y y1 C v M C A B w M C b L 1 7 Eh e 14 8 13 9 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. A1 b 1 0.05 0.00 0.30 0.18 c D (1) Dh E (1) Eh 0.2 3.1 2.9 1.65 1.35 2.6 2.4 1.15 0.85 e 0.5 e1 L v w y y1 2 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT762-1 --- MO-241 --- EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 10. Package outline SOT762-1 (DHVQFN14) 74ALVC32_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 10 December 2007 10 of 13 74ALVC32 NXP Semiconductors Quad 2-input OR gate 13. Abbreviations Table 10. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74ALVC32_2 20071210 Product data sheet - 74ALVC32_1 Modifications: 74ALVC32_1 • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • • • Legal texts have been adapted to the new company name where appropriate. Section 3: DHVQFN14 package added. Section 7: derating values added for DHVQFN14 package. Section 12: outline drawing added for DHVQFN14 package. 20021115 Product specification - 74ALVC32_2 Product data sheet - © NXP B.V. 2007. All rights reserved. Rev. 02 — 10 December 2007 11 of 13 74ALVC32 NXP Semiconductors Quad 2-input OR gate 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 15.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: [email protected] 74ALVC32_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 10 December 2007 12 of 13 74ALVC32 NXP Semiconductors Quad 2-input OR gate 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 11 Legal information. . . . . . . . . . . . . . . . . . . . . . . 12 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Contact information. . . . . . . . . . . . . . . . . . . . . 12 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 10 December 2007 Document identifier: 74ALVC32_2