PHILIPS BSP152

DISCRETE SEMICONDUCTORS
DATA SHEET
BSP152
N-channel enhancement mode
vertical D-MOS transistor
Product specification
File under Discrete Semiconductors, SC13b
April 1995
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
FEATURES
BSP152
QUICK REFERENCE DATA
• Direct interface to C-MOS, TTL,
etc.
• High-speed switching
• No secondary breakdown.
SYMBOL
CONDITIONS
MIN.
−
200
V
ID
DC drain current
−
550
mA
Ptot
total power
dissipation
up to Tamb = 25 °C −
1.5
W
±VGSO
gate-source
voltage
open drain
−
40
V
RDS(on)
drain-source
on-resistance
ID = 750 mA;
VGS = 10 V
−
2.5
Ω
VGS(off)
gate-source
cut-off voltage
ID = 1 mA;
VDS = VGS
1.5
3.5
V
DESCRIPTION
gate
2
drain
3
source
4
drain
d
4
handbook, halfpage
1
g
1
Top view
2
s
3
MAM054
Fig.1 Simplified outline and symbol.
April 1995
UNIT
drain-source
voltage
PINNING - SOT223
PIN
MAX.
VDS
DESCRIPTION
N-channel enhancement mode
vertical D-MOS transistor in a
SOT223 envelope, intended for use
as a line current interruptor in
telephone sets and for applications in
relay, high-speed and line
transformer drivers.
PARAMETER
2
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
BSP152
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
VDS
drain-source voltage
±VGSO
gate-source voltage
ID
DC drain current
IDM
peak drain current
Ptot
total power dissipation
Tstg
Tj
CONDITIONS
MIN.
open drain
MAX.
UNIT
−
200
V
−
40
V
−
550
mA
−
3
A
−
1.5
W
storage temperature
−65
+150
°C
operating junction temperature
−
150
°C
up to Tamb = 25 °C; note 1
THERMAL RESISTANCE
SYMBOL
Rth j-a
PARAMETER
THERMAL RESISTANCE
from junction to ambient; note 1
83.3 K/W
Note
1. Device mounted on an epoxy printed-circuit board, 40 x 40 x 1.5 mm, mounting pad for the drain tab minimum 6 mm2.
STATIC CHARACTERISTICS
Tj = 25 °C unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
V(BR)DSS
drain-source breakdown voltage
ID = 10 µA; VGS = 0
200
−
−
V
±IGSS
gate-source leakage current
±VGS = 40 V; VDS = 0
−
−
100
nA
VGS(th)
gate-source threshold voltage
ID = 1 mA; VDS = VGS
1.5
−
3.5
V
RDS(on)
drain-source on-resistance
ID = 750 mA; VGS = 10 V
−
−
2.5
Ω
IDSS
drain-source leakage current
VDS = 160 V; VGS = 0
−
−
100
nA
| Yfs|
transfer admittance
ID = 750 mA; VDS = 25 V
400
−
−
mS
Ciss
input capacitance
VDS = 25 V; VGS = 0;
−
100
−
pF
Coss
output capacitance
VDS = 25 V; VGS = 0; f = 1 MHz
−
42
−
pF
Crss
feedback capacitance
VDS = 25 V; VGS = 0; f = 1 MHz
−
8
−
pF
f = 1 MHz
Switching times (see Figs 2 and 3)
ton
turn-on time
ID = 750 mA; VDD = 50 V;
VGS = 0 to 10 V
−
−
15
ns
toff
turn-off time
ID = 750 mA; VDD = 50 V;
VGS = 10 to 0 V
−
−
30
ns
April 1995
3
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
BSP152
handbook, halfpage
VDD = 50 V
handbook, halfpage
90 %
INPUT
10 %
90 %
10 V
0V
OUTPUT
ID
50 Ω
10 %
MSA631
ton
toff
MBB692
Fig.2 Switching times test circuit.
Fig.3 Input and output waveforms.
MRC207
2
MRC203
300
handbook, halfpage
handbook, halfpage
Ptot
(W)
C
(pF)
1.5
200
1
Ciss
100
0.5
Coss
0
0
0
50
100
Tamb (°C)
150
Crss
0
10
20
VDS (V)
30
VGS = 0; f = 1 MHz; Tj = 25 °C.
Fig.5
Fig.4 Power derating curve.
April 1995
4
Capacitance as a function of drain-source
voltage, typical values.
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
MRC204
600
handbook,
halfpage
handbook,
I halfpage
D
(A)
VGS = 10 V
3
BSP152
7V
MRC205
VGS = 10 V 5 V
ID
4V
(mA)
P = 1.5 W
6V
3.5 V
400
2
5V
4.5 V
1
200
4V
3.5 V
0
0
4
8
VDS (V)
0
12
0
Tj = 25 °C.
1
2
VDS (V)
3
Tj = 25 °C.
Fig.6 Typical output characteristics.
Fig.7 Typical output characteristics.
MRC206
3
MRC208
7
RDS(on)
handbook, halfpage
handbook, halfpage
ID
(mA)
(Ω) 6
VGS = 3.5 V 4 V 5 V
6V
5
2
4
3
7V
2
8V
1
1
0
0.01
0
0
2
4
6
8
10
VDS (V)
VDS = 10 V; Tj = 25 °C.
1
ID (A)
5
Tj = 25 °C.
Fig.9
Fig.8 Typical transfer characteristics.
April 1995
0.1
5
Drain-source on-resistance as a function of
drain current, typical values.
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
BSP152
MRC210
100
MRC212
5
handbook, halfpage
handbook, halfpage
ID
(mA)
(1)
tp
10 µs
100 µs
1 ms
10 ms
1
RDS(on)
(Ω)
10-1
10
100 ms
1s
DC
tp
δ= T
P
10-2
t
tp
T
10-3
1
0
2
4
6
8
10
VDS (V)
1
VDS = 100 mV; Tj = 25 °C.
102
10
3
VDS (V) 10
δ = 0.01; Tamb = 25 °C.
(1) RDSon limitation.
Fig.10 Drain-source on-resistance as a function of
gate-source voltage, typical values.
Fig.11 SOAR curve.
MRC211
102
handbook, full pagewidth
δ=
0.75
Rth j-a
(K/W)
0.5
0.2
10
0.1
0.05
0.02
1
0.01
tp
δ= T
P
0
t
tp
T
10-1
10-5
10-4
10-3
10-2
10-1
1
10
102
tp (s)
Fig.12 Transient thermal resistance from junction to ambient as a function of pulse time.
April 1995
6
103
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
MRC209
2.2
MRC213
1.2
handbook, halfpage
handbook, halfpage
k
BSP152
k
2
1.8
1
1.6
1.4
1.2
0.8
1
0.8
0.6
0.4
–50
0
50
100
Tj (°C)
0.6
–50
150
50
100
Tj (°C)
150
V GS(th) at T j
k = ------------------------------------------o
V GS(th) at 25 C
R DS(on) at T j
k = ------------------------------------------o
R DS(on) at 25 C
Typical VGS(th) at ID = 1 mA.
Typical RDSon at ID = 750 mA; VGS = 10 V.
Fig.13 Temperature coefficient of
drain-source on-resistance.
April 1995
0
Fig.14 Temperature coefficient of gate-source
threshold voltage.
7
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
BSP152
PACKAGE OUTLINE
Plastic surface mounted package; collector pad for good heat transfer; 4 leads
D
SOT223
E
B
A
X
c
y
HE
v M A
b1
4
Q
A
A1
1
2
3
Lp
bp
e1
w M B
detail X
e
0
2
4 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
bp
b1
c
D
E
e
e1
HE
Lp
Q
v
w
y
mm
1.8
1.5
0.10
0.01
0.80
0.60
3.1
2.9
0.32
0.22
6.7
6.3
3.7
3.3
4.6
2.3
7.3
6.7
1.1
0.7
0.95
0.85
0.2
0.1
0.1
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
96-11-11
97-02-28
SOT223
April 1995
EUROPEAN
PROJECTION
8
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
BSP152
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
April 1995
9
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
NOTES
April 1995
10
BSP152
Philips Semiconductors
Product specification
N-channel enhancement mode vertical
D-MOS transistor
NOTES
April 1995
11
BSP152
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© Philips Electronics N.V. 1997
SCA54
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Printed in The Netherlands
137107/00/01/pp12
Date of release: April 1995
Document order number:
9397 750 02541