DISCRETE SEMICONDUCTORS DATA SHEET BST86 N-channel enhancement mode vertical D-MOS transistor Product specification File under Discrete Semiconductors, SC13b April 1995 Philips Semiconductors Product specification N-channel enhancement mode vertical D-MOS transistor DESCRIPTION BST86 QUICK REFERENCE DATA N-channel enhancement mode vertical D-MOS transistor in SOT89 envelope and designed for use as Surface Mounted Device (SMD) in thin and thick-film circuits for application with relay, high-speed and line-transformer drivers. Drain-source voltage VDS max. 180 V Drain-source voltage (non-repetitive peak; tp ≤ 2 ms) VDS(SM) max. 200 V Gate-source voltage (open drain) ±VGSO max. 20 V Drain current (DC) ID max. 300 mA Total power dissipation up to Tamb = 25 °C Ptot max. 1 W RDS(on) typ. max. 7 Ω 10 Ω Yfs typ. 250 mS Drain-source ON-resistance FEATURES ID = 15 mA; VGS = 3 V • Direct interface to C-MOS, TTL, etc. Transfer admittance • High-speed switching ID = 300 mA; VDS = 15 V • No second breakdown PINNING - SOT89 1 = source 2 = drain 3 = gate PIN CONFIGURATION d handbook, halfpage g 1 2 3 s Bottom view MAM355 Marking: K0 Fig.1 Simplified outline and symbol. April 1995 2 Philips Semiconductors Product specification N-channel enhancement mode vertical D-MOS transistor BST86 RATINGS Limiting values in accordance with the Absolute Maximum System (IEC 134) Drain-source voltage VDS max. 180 V Drain-source voltage (non-repetitive peak; tp ≤ 2 ms) VDS(SM) max. 200 V Gate-source voltage (open drain) ±VGSO max. 20 V Drain current (DC) ID max. 300 mA Drain current (peak) IDM max. 800 mA Total power dissipation up to Tamb = 25 °C (note 1) Ptot max. 1 W Storage temperature range Tstg Junction temperature Tj max. 150 °C Rth j-a = 125 K/W −65 to + 150 °C THERMAL RESISTANCE From junction to ambient (note 1) Note 1. Transistor mounted on a ceramic substrate of 2.5 cm2 and thickness of 0.7 mm. April 1995 3 Philips Semiconductors Product specification N-channel enhancement mode vertical D-MOS transistor BST86 CHARACTERISTICS Tj = 25 °C unless otherwise specified Drain-source breakdown voltage ID = 100 µA; VGS = 0 V(BR)DSS min. 180 V IDSS max. 10 µA IGSS max. 100 nA VGS(th) min. max. 0.7 V 2.7 V ID = 15 mA; VGS = 3 V RDS(on) typ. max. 7 Ω 10 Ω ID = 300 mA; VGS = 10 V RDS(on) typ. 6 Ω Yfs typ. 250 mS Ciss typ. max. 50 pF 65 pF Coss typ. max. 20 pF 30 pF Crss typ. max. 6 pF 10 pF ton toff max. max. 10 ns 15 ns Drain-source leakage current VDS = 120 V; VGS = 0 Gate-source leakage current VGS = 20 V; VDS = 0 Gate threshold voltage ID = 100 µA; VDS = VGS Drain-source ON-resistance Transfer admittance ID = 300 mA; VDS = 15 V Input capacitance at f = 1 MHz VDS = 10 V; VGS = 0 Output capacitance at f = 1 MHz VDS = 10 V; VGS = 0 Feedback capacitance at f = 1 MHz VDS = 10 V; VGS = 0 Switching times (see as 2 and 3) ID = 300 mA; VDD = 50 V; VGS = 0 to 10 V April 1995 4 Philips Semiconductors Product specification N-channel enhancement mode vertical D-MOS transistor handbook, halfpage VDD = 50 V handbook, halfpage BST86 90 % INPUT 10 % 90 % 10 V OUTPUT ID 0V 10 % 50 Ω ton MBB691 toff MBB692 Fig.2 Switching times test circuit. Fig.3 Input and output waveforms. MDA169 103 handbook, halfpage (1) MDA170 1 (2) handbook, halfpage ID (A) 0.8 (3) ID (mA) 0.6 102 0.4 0.2 10 4 6 8 10 0 12 14 RDSon (Ω) 0 2 4 6 8 10 VGS (V) (1) VGS = 10 V. (2) VGS = 5 V. (3) VGS = 4 V. Fig.4 Tj = 25 °C; typical values. April 1995 Fig.5 Tj = 25 °C; VDS = 10 V; typ. values. 5 Philips Semiconductors Product specification N-channel enhancement mode vertical D-MOS transistor MDA164 1 BST86 MRC238 1.2 handbook, halfpage handbook, halfpage ID (A) 0.8 (1) (2) Ptot (W) 0.8 (3) 0.6 0.4 0.4 (4) 0.2 0 0 2 0 4 6 8 0 10 VDS (V) 50 100 150 200 Tamb (°C) (1) VGS = 10 V. (2) VGS = 5 V. (3) VGS = 4 V. (4) VGS = 3 V. Fig.6 Tj = 25 °C; typical values. Fig.7 Power derating curve. MDA166 3 MDA167 1.2 handbook, halfpage handbook, halfpage k k 2.5 1 (1) 2 (2) 1.5 0.8 1 0.5 −50 0 50 100 Tj (oC) 0.6 −50 150 0 50 100 150 Tj (oC) (1) ID = 300 mA; VGS = 10 V. (2) ID = 15 mA; VGS = 3 V. Fig.8 April 1995 Fig.9 R DS on at T j k = ------------------------------------------- ; R DS on at 25 °C V GS ( th ) at T j k = -------------------------------------------- ; V GS(th) at 25 °C typcial values. VGS(th) at 01. mA; typical values. 6 Philips Semiconductors Product specification N-channel enhancement mode vertical D-MOS transistor MDA168 120 handbook, halfpage C (pF) 80 (1) 40 (2) (3) 0 0 10 20 VDS (V) 30 (1) Ciss. (2) Coss. (3) Crss. Fig.10 Tj = 25 °C; VGS = 0; f = 1 MHz; typical values. April 1995 7 BST86 Philips Semiconductors Product specification N-channel enhancement mode vertical D-MOS transistor BST86 PACKAGE OUTLINE Plastic surface mounted package; collector pad for good heat transfer; 3 leads SOT89 B D A b3 E HE L 1 2 3 c b2 w M b1 e1 e 0 2 4 mm scale DIMENSIONS (mm are the original dimensions) UNIT A b1 b2 b3 c D E e e1 HE L min. w mm 1.6 1.4 0.48 0.35 0.53 0.40 1.8 1.4 0.44 0.37 4.6 4.4 2.6 2.4 3.0 1.5 4.25 3.75 0.8 0.13 OUTLINE VERSION REFERENCES IEC JEDEC EIAJ SOT89 April 1995 EUROPEAN PROJECTION ISSUE DATE 97-02-28 8 Philips Semiconductors Product specification N-channel enhancement mode vertical D-MOS transistor BST86 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 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