PHILIPS 74AHCT2G08DC

74AHC2G08; 74AHCT2G08
Dual 2-input AND gate
Rev. 03 — 12 January 2009
Product data sheet
1. General description
The 74AHC2G08; 74AHCT2G08 is a high-speed Si-gate CMOS device.
The 74AHC2G08; 74AHCT2G08 provides two 2-input AND gates.
2. Features
n Symmetrical output impedance
n High noise immunity
n ESD protection:
u HBM JESD22-A114E exceeds 2000 V
u MM JESD22-A115-A exceeds 200 V
u CDM JESD22-C101C exceeds 1000 V
n Low power dissipation
n Balanced propagation delays
n Multiple package options
n Specified from −40 °C to +85 °C and from −40 °C to +125 °C
3. Ordering information
Table 1.
Ordering information
Type number
74AHC2G08DP
Package
Temperature range Name
Description
−40 °C to +125 °C
TSSOP8
plastic thin shrink small outline package; 8 leads; body SOT505-2
width 3 mm; lead length 0.5 mm
−40 °C to +125 °C
VSSOP8
plastic very thin shrink small outline package; 8 leads; SOT765-1
body width 2.3 mm
−40 °C to +125 °C
XSON8U
plastic extremely thin small outline package; no leads; SOT996-2
8 terminals; UTLP based; body 3 × 2 × 0.5 mm
74AHCT2G08DP
74AHC2G08DC
74AHCT2G08DC
74AHC2G08GD
74AHCT2G08GD
Version
74AHC2G08; 74AHCT2G08
NXP Semiconductors
Dual 2-input AND gate
4. Marking
Table 2.
Marking
Type number
Marking code
74AHC2G08DP
A08
74AHCT2G08DP
C08
74AHC2G08DC
A08
74AHCT2G08DC
C08
74AHC2G08GD
A08
74AHCT2G08GD
C08
5. Functional diagram
1
1
1A
2
1B
5
2A
6
2B
1Y
7
2Y
3
7
5
&
3
6
mna725
mna724
Fig 1.
&
2
Logic symbol.
Fig 2.
IEC logic symbol.
A
Y
B
mna221
Fig 3.
Logic diagram (one gate).
74AHC_AHCT2G08_3
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 03 — 12 January 2009
2 of 14
74AHC2G08; 74AHCT2G08
NXP Semiconductors
Dual 2-input AND gate
6. Pinning information
6.1 Pinning
74AHC2G08
74AHCT2G08
1A
1
8
VCC
1B
2
7
1Y
2Y
3
6
2B
GND
4
5
2A
74AHC2G08
74AHCT2G08
1A
1
8
VCC
1B
2
7
1Y
2Y
3
6
2B
GND
4
5
2A
001aaj390
Transparent top view
001aaj389
Fig 4.
Pin configuration SOT505-2 (TSSOP8) and
SOT765-1 (VSSOP8)
Fig 5.
Pin configuration SOT996-2 (XSON8U)
6.2 Pin description
Table 3.
Pin description
Symbol
Pin
Description
1A, 2A
1, 5
data input
1B, 2B
2, 6
data input
GND
4
ground (0 V)
1Y, 2Y
7, 3
data output
VCC
8
supply voltage
7. Functional description
Table 4.
Function table[1]
Input
Output
nA
nB
nY
L
L
L
L
H
L
H
L
L
H
H
H
[1]
H = HIGH voltage level; L = LOW voltage level.
74AHC_AHCT2G08_3
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 03 — 12 January 2009
3 of 14
74AHC2G08; 74AHCT2G08
NXP Semiconductors
Dual 2-input AND gate
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
VCC
supply voltage
VI
input voltage
IIK
input clamping current
VI < −0.5 V
[1]
IOK
output clamping current
VO < −0.5 V or VO > VCC + 0.5 V
[1]
IO
output current
−0.5 V < VO < VCC + 0.5 V
Min
Max
Unit
−0.5
+7.0
V
−0.5
+7.0
V
−20
-
mA
-
±20
mA
-
±25
mA
ICC
supply current
-
75
mA
IGND
ground current
−75
-
mA
Tstg
storage temperature
−65
+150
°C
-
250
mW
total power dissipation
Ptot
Tamb = −40 °C to +125 °C
[2]
[1]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2]
For TSSOP8 package: above 55 °C the value of Ptot derates linearly with 2.5 mW/K.
For VSSOP8 package: above 110 °C the value of Ptot derates linearly with 8 mW/K.
For XSON8U package: above 45 °C the value of Ptot derates linearly with 2.4 mW/K.
9. Recommended operating conditions
Table 6.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
74AHC2G08
Min
Typ
74AHCT2G08
Max
Min
Typ
Unit
Max
VCC
supply voltage
2.0
5.0
5.5
4.5
5.0
5.5
V
VI
input voltage
0
-
5.5
0
-
5.5
V
VO
output voltage
0
-
VCC
0
-
VCC
V
Tamb
ambient temperature
−40
+25
+125
−40
+25
+125
°C
∆t/∆V
input transition rise
and fall rate
VCC = 3.3 V ± 0.3 V
-
-
100
-
-
-
ns/V
VCC = 5.0 V ± 0.5 V
-
-
20
-
-
20
ns/V
74AHC_AHCT2G08_3
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 03 — 12 January 2009
4 of 14
74AHC2G08; 74AHCT2G08
NXP Semiconductors
Dual 2-input AND gate
10. Static characteristics
Table 7.
Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
25 °C
Conditions
−40 °C to +85 °C −40 °C to +125 °C Unit
Min
Typ
Max
Min
Max
Min
Max
VCC = 2.0 V
1.5
-
-
1.5
-
1.5
-
V
VCC = 3.0 V
2.1
-
-
2.1
-
2.1
-
V
VCC = 5.5 V
3.85
-
-
3.85
-
3.85
-
V
74AHC2G08
VIH
VIL
VOH
VOL
HIGH-level
input voltage
LOW-level
input voltage
VCC = 2.0 V
-
-
0.5
-
0.5
-
0.5
V
VCC = 3.0 V
-
-
0.9
-
0.9
-
0.9
V
VCC = 5.5 V
-
-
1.65
-
1.65
-
1.65
V
HIGH-level
VI = VIH or VIL
output voltage
IO = −50 µA; VCC = 2.0 V
1.9
2.0
-
1.9
-
1.9
-
V
IO = −50 µA; VCC = 3.0 V
2.9
3.0
-
2.9
-
2.9
-
V
IO = −50 µA; VCC = 4.5 V
4.4
4.5
-
4.4
-
4.4
-
V
IO = −4.0 mA; VCC = 3.0 V
2.58
-
-
2.48
-
2.40
-
V
IO = −8.0 mA; VCC = 4.5 V
3.94
-
-
3.8
-
3.70
-
V
LOW-level
VI = VIH or VIL
output voltage
IO = 50 µA; VCC = 2.0 V
-
0
0.1
-
0.1
-
0.1
V
IO = 50 µA; VCC = 3.0 V
-
0
0.1
-
0.1
-
0.1
V
IO = 50 µA; VCC = 4.5 V
-
0
0.1
-
0.1
-
0.1
V
IO = 4.0 mA; VCC = 3.0 V
-
-
0.36
-
0.44
-
0.55
V
IO = 8.0 mA; VCC = 4.5 V
-
-
0.36
-
0.44
-
0.55
V
-
-
0.1
-
1.0
-
2.0
µA
II
input leakage
current
VI = 5.5 V or GND;
VCC = 0 V to 5.5 V
ICC
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
1.0
-
10
-
40
µA
CI
input
capacitance
-
1.5
10
-
10
-
10
pF
74AHCT2G08
VIH
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
2.0
-
-
2.0
-
2.0
-
V
VIL
LOW-level
input voltage
VCC = 4.5 V to 5.5 V
-
-
0.8
-
0.8
-
0.8
V
VOH
HIGH-level
VI = VIH or VIL; VCC = 4.5 V
output voltage
IO = −50 µA
4.4
4.5
-
4.4
-
4.4
-
V
3.94
-
-
3.8
-
3.70
-
V
-
0
0.1
-
0.1
-
0.1
V
-
-
0.36
-
0.44
-
0.55
V
-
-
0.1
-
1.0
-
2.0
µA
IO = −8.0 mA
VOL
LOW-level
VI = VIH or VIL; VCC = 4.5 V
output voltage
IO = 50 µA
IO = 8.0 mA
II
input leakage
current
VI = 5.5 V or GND;
VCC = 0 V to 5.5 V
74AHC_AHCT2G08_3
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 03 — 12 January 2009
5 of 14
74AHC2G08; 74AHCT2G08
NXP Semiconductors
Dual 2-input AND gate
Table 7.
Static characteristics …continued
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
25 °C
Conditions
−40 °C to +85 °C −40 °C to +125 °C Unit
Min
Typ
Max
Min
Max
Min
Max
ICC
supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
1.0
-
10
-
40
µA
∆ICC
additional
per input pin; VI = 3.4 V;
supply current other inputs at VCC or GND;
IO = 0 A; VCC = 5.5 V
-
-
1.35
-
1.5
-
1.5
mA
CI
input
capacitance
-
1.5
10
-
10
-
10
pF
11. Dynamic characteristics
Table 8.
Dynamic characteristics
GND = 0 V; for test circuit see Figure 7.
Symbol Parameter
25 °C
Conditions
−40 °C to +85 °C −40 °C to +125 °C Unit
Min
Typ
Max
Min
Max
Min
Max
-
4.6
8.8
1.0
10.5
1.0
12.0
ns
-
6.5
12.3
1.0
14.0
1.0
16.0
ns
-
3.2
5.9
1.0
7.0
1.0
8.0
ns
-
4.6
7.9
1.0
9.0
1.0
10.5
ns
-
17
-
-
-
-
-
pF
74AHC2G08
tpd
propagation
delay
nA, nB to nY; see Figure 6
VCC = 3.0 V to 3.6 V
[1]
[2]
CL = 15 pF
CL = 50 pF
VCC = 4.5 V to 5.5 V
[3]
CL = 15 pF
CL = 50 pF
CPD
power
per buffer;
dissipation
CL = 50 pF; fi = 1 MHz;
capacitance VI = GND to VCC
[4]
74AHC_AHCT2G08_3
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 03 — 12 January 2009
6 of 14
74AHC2G08; 74AHCT2G08
NXP Semiconductors
Dual 2-input AND gate
Table 8.
Dynamic characteristics …continued
GND = 0 V; for test circuit see Figure 7.
Symbol Parameter
25 °C
Conditions
−40 °C to +85 °C −40 °C to +125 °C Unit
Min
Typ
Max
Min
Max
Min
Max
-
3.6
6.2
1.0
7.1
1.0
8.0
ns
-
5.1
7.9
1.0
9.0
1.0
10.5
ns
-
19
-
-
-
-
-
pF
74AHCT2G08
propagation
delay
tpd
nA, nB to nY; see Figure 6
[1]
[3]
VCC = 4.5 V to 5.5 V
CL = 15 pF
CL = 50 pF
[4]
power
per buffer;
dissipation
CL = 50 pF; fi = 1 MHz;
capacitance VI = GND to VCC
CPD
[1]
tpd is the same as tPLH and tPHL.
[2]
Typical values are measured at VCC = 3.3 V.
[3]
Typical values are measured at VCC = 5.0 V.
[4]
CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of the outputs.
12. Waveforms
VI
VM
nA, nB input
GND
t PLH
t PHL
VOH
VM
nY output
VOL
Fig 6.
Table 9.
mna224
The input (nA and nB) to output (nY) propagation delays.
Measurement points
Type
Input
Output
VM
VM
74AHC2G08
0.5VCC
0.5VCC
74AHCT2G08
1.5 V
0.5VCC
74AHC_AHCT2G08_3
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 03 — 12 January 2009
7 of 14
74AHC2G08; 74AHCT2G08
NXP Semiconductors
Dual 2-input AND gate
VI
tW
90 %
negative
pulse
VM
0V
tf
tr
tr
tf
VI
90 %
positive
pulse
0V
VM
10 %
VM
VM
10 %
tW
VCC
VCC
G
VI
VO
RL
S1
open
DUT
RT
CL
001aad983
Test data is given in Table 10.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch.
Fig 7.
Table 10.
Test circuit for measuring switching times
Test data
Type
Input
Load
S1 position
VI
tr, tf
CL
RL
tPHL, tPLH
tPZH, tPHZ
tPZL, tPLZ
74AHC2G08
VCC
≤ 3 ns
15 pF, 50 pF
1 kΩ
open
GND
VCC
74AHCT2G08
3V
≤ 3 ns
15 pF, 50 pF
1 kΩ
open
GND
VCC
74AHC_AHCT2G08_3
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 03 — 12 January 2009
8 of 14
74AHC2G08; 74AHCT2G08
NXP Semiconductors
Dual 2-input AND gate
13. Package outline
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm
D
E
A
SOT505-2
X
c
HE
y
v M A
Z
5
8
A
A2
(A3)
A1
pin 1 index
θ
Lp
L
1
4
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D(1)
E(1)
e
HE
L
Lp
v
w
y
Z(1)
θ
mm
1.1
0.15
0.00
0.95
0.75
0.25
0.38
0.22
0.18
0.08
3.1
2.9
3.1
2.9
0.65
4.1
3.9
0.5
0.47
0.33
0.2
0.13
0.1
0.70
0.35
8°
0°
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
OUTLINE
VERSION
SOT505-2
Fig 8.
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
02-01-16
---
Package outline SOT505-2 (TSSOP8)
74AHC_AHCT2G08_3
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 03 — 12 January 2009
9 of 14
74AHC2G08; 74AHCT2G08
NXP Semiconductors
Dual 2-input AND gate
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
D
E
SOT765-1
A
X
c
y
HE
v M A
Z
5
8
Q
A
A2
A1
pin 1 index
(A3)
θ
Lp
1
4
e
L
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D(1)
E(2)
e
HE
L
Lp
Q
v
w
y
Z(1)
θ
mm
1
0.15
0.00
0.85
0.60
0.12
0.27
0.17
0.23
0.08
2.1
1.9
2.4
2.2
0.5
3.2
3.0
0.4
0.40
0.15
0.21
0.19
0.2
0.13
0.1
0.4
0.1
8°
0°
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT765-1
Fig 9.
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
02-06-07
MO-187
Package outline SOT765-1 (VSSOP8)
74AHC_AHCT2G08_3
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 03 — 12 January 2009
10 of 14
74AHC2G08; 74AHCT2G08
NXP Semiconductors
Dual 2-input AND gate
XSON8U: plastic extremely thin small outline package; no leads;
8 terminals; UTLP based; body 3 x 2 x 0.5 mm
B
D
SOT996-2
A
A
E
A1
detail X
terminal 1
index area
e1
v
w
b
e
L1
1
4
8
5
C
C A B
C
M
M
y
y1 C
L2
L
X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max
A1
b
D
E
e
e1
L
L1
L2
v
w
y
y1
mm
0.5
0.05
0.00
0.35
0.15
2.1
1.9
3.1
2.9
0.5
1.5
0.5
0.3
0.15
0.05
0.6
0.4
0.1
0.05
0.05
0.1
REFERENCES
OUTLINE
VERSION
IEC
SOT996-2
---
JEDEC
JEITA
---
EUROPEAN
PROJECTION
ISSUE DATE
07-12-18
07-12-21
Fig 10. Package outline SOT996-2 (XSON8U)
74AHC_AHCT2G08_3
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 03 — 12 January 2009
11 of 14
74AHC2G08; 74AHCT2G08
NXP Semiconductors
Dual 2-input AND gate
14. Abbreviations
Table 11.
Abbreviations
Acronym
Description
CDM
Charged Device Model
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
15. Revision history
Table 12.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74AHC_AHCT2G08_3
20090112
Product data sheet
-
74AHC_AHCT2G08_2
Modifications:
•
The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•
•
Legal texts have been adapted to the new company name where appropriate.
Added type number 74AHC2G08GD and 74AHCT2G08GD (XSON8U package).
74AHC_AHCT2G08_2
20041018
Product data sheet
-
74AHC_AHCT2G08_1
74AHC_AHCT2G08_1
20040206
Product specification
-
-
74AHC_AHCT2G08_3
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 03 — 12 January 2009
12 of 14
74AHC2G08; 74AHCT2G08
NXP Semiconductors
Dual 2-input AND gate
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
16.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
74AHC_AHCT2G08_3
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 03 — 12 January 2009
13 of 14
NXP Semiconductors
74AHC2G08; 74AHCT2G08
Dual 2-input AND gate
18. Contents
1
2
3
4
5
6
6.1
6.2
7
8
9
10
11
12
13
14
15
16
16.1
16.2
16.3
16.4
17
18
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 1
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 12
Legal information. . . . . . . . . . . . . . . . . . . . . . . 13
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Contact information. . . . . . . . . . . . . . . . . . . . . 13
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 12 January 2009
Document identifier: 74AHC_AHCT2G08_3