INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
• The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT4353
Triple 2-channel analog
multiplexer/demultiplexer with latch
Product specification
File under Integrated Circuits, IC06
December 1990
Philips Semiconductors
Product specification
Triple 2-channel analog
multiplexer/demultiplexer with latch
74HC/HCT4353
multiplexer has two independent inputs/outputs (nY0 and
nY1), a common input/output (nZ) and select inputs (S1 to
S3).
FEATURES
• Wide analog input voltage range: ± 5 V
• Low “ON” resistance:
80 Ω (typ.) at VCC − VEE = 4.5 V
70 Ω (typ.) at VCC − VEE = 6.0 V
60 Ω (typ.) at VCC − VEE = 9.0 V
Each multiplexer/demultiplexer contains two bidirectional
analog switches, each with one side connected to an
independent input/output (nY0 and nY1) and the other side
connected to a common input/output (nZ).
• Logic level translation:
to enable 5 V logic to communicate with ± 5 V analog
signals
With E1 LOW and E2 HIGH, one of the two switches is
selected (low impedance ON-state) by S1 to S3.
The data at the select inputs may be latched by using the
active LOW latch enable input (LE). When LE is HIGH, the
latch is transparent. When either of the two enable inputs,
E1 (active LOW) and E2 (active HIGH), is inactive, all
analog switches are turned off.
• Typical “break before make” built in
• Address latches provided
• Output capability: non-standard
• ICC category: MSI
VCC and GND are the supply voltage pins for the digital
control inputs (S1 to S3, LE, E1 and E2). The VCC to GND
ranges are 2.0 to 10.0 V for HC and 4.5 to 5.5 V for HCT.
The analog inputs/outputs (nY0 and nY1, and nZ) can
swing between VCC as a positive limit and VEE as a
negative limit. VCC − VEE may not exceed 10.0 V.
GENERAL DESCRIPTION
The 74HC/HCT4353 are high-speed Si-gate CMOS
devices. They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT4353 are triple 2-channel analog
multiplexers/demultiplexers with two common enable
inputs (E1 and E2) and a latch enable input (LE). Each
For operation as a digital multiplexer/demultiplexer, VEE is
connected to GND (typically ground).
QUICK REFERENCE DATA
VEE = GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
SYMBOL
PARAMETER
CONDITIONS
UNIT
HC
tPZH/ tPZL
turn “ON” time E1, E2 or Sn to Vos
tPHZ/ tPLZ
turn “OFF” time E1, E2 or Sn to Vos
CI
input capacitance
CPD
power dissipation capacitance per switch
CS
max. switch capacitance
HCT
29
21
ns
20
22
ns
3.5
3.5
pF
23
23
pF
independent (Y)
5
5
pF
common (Z)
8
8
pF
CL = 50 pF; RL = 1 kΩ;
VCC = 5 V
notes 1 and 2
Notes
∑ {(CL ×CS) × VCC2 × fo} = sum of outputs
1. CPD is used to determine the dynamic power
dissipation (PD in µW):
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
PD =
CPD × VCC2 × fi + ∑ {(CL + CS) × VCC2 × fo} where:
fi = input frequency in MHz
ORDERING INFORMATION
CL = output load capacitance in pF
See “74HC/HCT/HCU/HCMOS Logic Package
Information”.
fo = output frequency in MHz
CS = max. switch capacitance in pF
December 1990
2
Philips Semiconductors
Product specification
Triple 2-channel analog
multiplexer/demultiplexer with latch
74HC/HCT4353
PIN DESCRIPTION
PIN NO.
SYMBOL
NAME AND FUNCTION
2, 1
2Y0, 2Y1
independent inputs/outputs
5
3Z
common input/output
6, 4
3Y0, 3Y1
independent inputs/outputs
3, 14
n.c.
not connected
7
E1
enable input (active LOW)
8
E2
enable input (active HIGH)
9
VEE
negative supply voltage
10
GND
ground (0 V)
11
LE
latch enable input (active LOW)
15, 13, 12
S1 to S3
select inputs
16, 17
1Y0, 1Y1
independent inputs/outputs
18
1Z
common input/output
19
2Z
common input/output
20
VCC
positive supply voltage
Fig.1 Pin configuration.
December 1990
Fig.2 Logic symbol.
3
Fig.3 IEC logic symbol.
Philips Semiconductors
Product specification
Triple 2-channel analog
multiplexer/demultiplexer with latch
74HC/HCT4353
FUNCTION TABLE
INPUTS
CHANNEL
ON
E1
E2
LE
Sn
H
X
H
L
X
X
X
X
none
none
L
L
H
H
H
H
L
H
nY0 − nZ
nY1 − nZ
L
X
H
X
L
↓
X
X
(1)
(2)
Notes
1. Last selected channel “ON”.
2. Selected channels latched.
H = HIGH voltage level
L = LOW voltage level
X = don’t care
↓ = HIGH-to-LOW LE transition
APPLICATIONS
• Analog multiplexing and demultiplexing
• Digital multiplexing and demultiplexing
• Signal gating
Fig.4 Functional diagram.
Fig.5 Schematic diagram (one switch).
December 1990
4
Philips Semiconductors
Product specification
Triple 2-channel analog
multiplexer/demultiplexer with latch
74HC/HCT4353
RATINGS
Limiting values in accordance with the Absolute Maximum System (IEC 134)
Voltages are referenced to VEE = GND (ground = 0 V)
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
VCC
DC supply voltage
−0.5
+11.0
V
±IIK
DC digital input diode current
20
mA
for VI < −0.5 V or VI > VCC + 0.5 V
±ISK
DC switch diode current
20
mA
for VS < −0.5 V or VS > VCC + 0.5 V
±IS
DC switch current
25
mA
for −0.5 V < VS < VCC + 0.5 V
±IEE
DC VEE current
20
mA
±ICC;
±IGND
DC VCC or GND current
50
mA
Tstg
storage temperature range
+150
°C
Ptot
power dissipation per package
PS
−65
CONDITIONS
for temperature range: −40 to +125 °C
74HC/HCT
plastic DIL
750
mW
above +70 °C: derate linearly with 12 mW/K
plastic mini-pack (SO)
500
mW
above +70 °C: derate linearly with 8 mW/K
power dissipation per switch
100
mW
Note to ratings
1. To avoid drawing VCC current out of terminals nZ, when switch current flows in terminals nYn, the voltage drop across
the bidirectional switch must not exceed 0.4 V. If the switch current flows into terminals nZ, no VCC current will flow
out of terminals nYn. In this case there is no limit for the voltage drop across the switch, but the voltages at nYn and
nZ may not exceed VCC or VEE.
RECOMMENDED OPERATING CONDITIONS
74HC
74HCT
SYMBOL PARAMETER
UNIT
min. typ.
max.
min.
typ. max.
CONDITIONS
VCC
DC supply voltage VCC−GND
2.0
5.0
10.0
4.5
5.0
5.5
V
see Figs 6 and 7
VCC
DC supply voltage VCC−VEE
2.0
5.0
10.0
2.0
5.0
10.0
V
see Figs 6 and 7
VI
DC input voltage range
GND
VCC
GND
VCC
V
VS
DC switch voltage range
VEE
VCC
VEE
VCC
V
Tamb
operating ambient temperature range
−40
+85
−40
+85
°C
Tamb
operating ambient temperature range
−40
+125
−40
+125 °C
see DC and AC
CHARACTERISTICS
t r, t f
input rise and fall times
500
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
VCC = 10.0 V
6.0
December 1990
5
1000
500
400
250
6.0
ns
Philips Semiconductors
Product specification
Triple 2-channel analog
multiplexer/demultiplexer with latch
74HC/HCT4353
MBA334
10
handbook, halfpage
VCC - GND
(V)
8
operating area
6
4
2
0
Fig.6
0
2
4
6
8
10
VCC - V EE (V)
Fig.7
Guaranteed operating area as a function of
the supply voltages for 74HC4353.
Guaranteed operating area as a function of
the supply voltages for 74HCT4353.
DC CHARACTERISTICS FOR 74HC/HCT
For 74HC: VCC − GND or VCC − VEE = 2.0, 4.5, 6.0 and 9.0 V
For 74HCT: VCC − GND = 4.5 and 5.5 V; VCC − VEE = 2.0, 4.5, 6.0 and 9.0 V
Tamb (°C)
TEST CONDITIONS
74HC/HCT
SYMBOL
PARAMETER
min.
+25
−40 to +85
typ.
max. min. max.
−40 to +125
min.
UNIT V
CC VEE IS
Vis
(V) (V) (µA)
VI
max.
RON
ON resistance
(peak)
−
100
90
70
−
180
160
130
−
225
200
165
−
270
240
195
Ω
Ω
Ω
Ω
2.0
4.5
6.0
4.5
0
0
0
−4.5
100 VCC VIN
1000 to
or
1000 VEE VIL
1000
RON
ON resistance
(rail)
150
80
70
60
−
140
120
105
−
175
150
130
−
210
180
160
Ω
Ω
Ω
Ω
2.0
4.5
6.0
4.5
0
0
0
−4.5
100 VEE
1000
1000
1000
RON
ON resistance
150
90
80
65
−
160
140
120
−
200
175
150
−
240
210
180
Ω
Ω
Ω
Ω
2.0
4.5
6.0
4.5
0
0
0
−4.5
100 VCC VIH
1000
or
1000
VIL
1000
∆RON
maximum
∆ON resistance
between any two
channels
−
9
8
6
Ω
Ω
Ω
Ω
2.0
4.5
6.0
4.5
0
0
0
−4.5
VCC VIH
to
or
VEE VIL
VIH
or
VIL
Notes to DC characteristics
1. At supply voltages (VCC − VEE) approaching 2.0 V the analog switch ON-resistance becomes extremely non-linear.
There it is recommended that these devices be used to transmit digital signals only, when using these supply
voltages.
2. For test circuit measuring RON see Fig.8.
December 1990
6
Philips Semiconductors
Product specification
Triple 2-channel analog
multiplexer/demultiplexer with latch
74HC/HCT4353
DC CHARACTERISTICS FOR 74HC
Voltages are referenced to GND (ground = 0 V)
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
−40 to +85
+25
min. typ. max. min.
VIH
HIGH level
input voltage
VIL
LOW level
input voltage
±II
1.5
3.15
4.2
6.3
1.2
2.4
3.2
4.7
min.
VCC
(V)
VEE
(V)
VI
OTHER
max.
1.5
3.15
4.2
6.3
1.5
3.15
4.2
6.3
UNIT
V
2.0
4.5
6.0
9.0
0.5
1.35
1.8
2.7
0.5
1.35
1.8
2.7
0.5
1.35
1.8
2.7
V
2.0
4.5
6.0
9.0
input leakage
current
0.1
0.2
1.0
2.0
1.0
2.0
µA
6.0 0
10.0 0
VCC
or
GND
±IS
analog switch
OFF-state
current per
channel
0.1
1.0
1.0
µA
10.0 0
VIH
or
VIL
VS =
VCC − VEE
(see Fig.10)
±IS
analog switch
OFF-state
current all
channels
0.1
1.0
1.0
µA
10.0 0
VIH
or
VIL
VS =
VCC − VEE
(see Fig.10)
±IS
analog switch
ON-state
current
0.1
1.0
1.0
µA
10.0 0
VIH
or
VIL
VS =
VCC − VEE
ICC
quiescent
supply current
8.0
16.0
80.0
160.0
160.0
320.0
µA
6.0 0
10.0 0
VCC Vis = VEE or
VCC; Vos =
or
GND VCC or VEE
December 1990
0.8
2.1
2.8
4.3
max.
−40 to +125
7
(see Fig.11)
Philips Semiconductors
Product specification
Triple 2-channel analog
multiplexer/demultiplexer with latch
74HC/HCT4353
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HC
SYMBOL PARAMETER
+25
−40 to +85
−40 to +125
min. typ. max. min. max. min.
UNIT V
CC
(V)
VEE
OTHER
(V)
max.
tPHL/ tPLH
propagation delay
Vis to Vos
14
5
4
4
60
12
10
8
75
15
13
10
90
18
15
12
ns
2.0
4.5
6.0
4.5
0
RL = ∞;
0
CL = 50 pF
(see Fig.18)
0
−4.5
tPZH/ tPZL
turn “ON” time
E1; E2 to Vos
61
22
18
18
250
50
43
40
315
63
54
50
375
75
64
60
ns
2.0
4.5
6.0
4.5
0
RL = 1 kΩ;
0
CL = 50 pF
(see Fig.19)
0
−4.5
tPZH/ tPZL
turn “ON” time
LE to Vos
55
20
16
17
200
40
34
40
250
50
43
50
300
60
51
60
ns
2.0
4.5
6.0
4.5
0
RL = 1 kΩ;
0
CL = 50 pF
0
(see Fig.19)
−4.5
tPZH/ tPZL
turn “ON” time
Sn to Vos
61
22
18
17
225
45
38
40
280
56
48
50
340
68
58
60
ns
2.0
4.5
6.0
4.5
0
RL = 1 kΩ;
0
CL = 50 pF
0
(see Fig.19)
−4.5
tPHZ/ tPLZ
turn “OFF” time
E1; E2 to Vos
66
24
19
19
250
50
43
40
315
63
54
50
375
75
64
60
ns
2.0
4.5
6.0
4.5
0
RL = 1 kΩ;
0
CL = 50 pF
(see Fig.19)
0
−4.5
tPHZ/ tPLZ
turn “OFF” time
Sn to Vos; LE to Vos
55
20
16
19
200
40
34
40
250
50
43
50
300
60
51
60
ns
2.0
4.5
6.0
4.5
0
RL = 1 kΩ;
0
CL = 50 pF
0
(see Fig.19)
−4.5
tsu
set-up time Sn to LE
60
12
10
18
17
6
5
8
75
15
13
23
90
18
15
27
ns
2.0
4.5
6.0
4.5
0
RL = 1 kΩ;
0
CL = 50 pF
0
(see Fig.20)
−4.5
th
hold time Sn to LE
5
5
5
5
−6
−2
−2
−3
5
5
5
5
5
5
5
5
ns
2.0
4.5
6.0
4.5
0
RL = 1 kΩ;
0
CL = 50 pF
0
(see Fig.20)
−4.5
tW
LE minimum pulse
width HIGH
80
16
14
16
11
4
3
6
100
20
17
20
120
24
20
24
ns
2.0
4.5
6.0
4.5
0
RL = 1 kΩ;
0
CL = 50 pF
0
(see Fig.20)
−4.5
December 1990
8
Philips Semiconductors
Product specification
Triple 2-channel analog
multiplexer/demultiplexer with latch
74HC/HCT4353
DC CHARACTERISTICS FOR 74HCT
Voltages are referenced to GND (ground = 0 V)
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
VIH
HIGH level input
voltage
VIL
LOW level input
voltage
±II
+25
−40 to +85
−40 to +125
min. typ. max. min. max.
min.
2.0
2.0
1.6
1.2
2.0
UNIT
VCC VEE
VI
(V) (V)
OTHER
max.
V
4.5
to
5.5
0.8
0.8
0.8
V
4.5
to
5.5
input leakage
current
0.1
1.0
1.0
µA
5.5
±IS
analog switch
OFF-state
current per
channel
0.1
1.0
1.0
µA
10.0 0
VIH
or
VIL
VS =
VCC − VEE
Fig.10
±IS
analog switch
OFF-state current
all channels
0.1
1.0
1.0
µA
10.0 0
VIH
or
VIL
VS =
VCC − VEE
Fig.10
±IS
analog switch
ON-state current
0.1
1.0
1.0
µA
10.0 0
VIH
or
VIL
VS =
VCC − VEE
Fig.11
ICC
quiescent supply
current
8.0
16.0
80.0
160.0
160.0
320.0
µA
5.5
5.0
0
VCC
or
GND
0
VCC Vis = VEE
−5.0 or
or VCC;
GND Vos =
VCC or VEE
∆ICC
additional
quiescent supply
current per input
pin for unit load
coefficient is 1
(note 1)
100 360
450
490
µA
4.5
to
5.5
0
VCC
−2.1
V
Note to HCT types
1. The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given here.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
UNIT LOAD COEFFICIENT
E1, E2
Sn
LE
0.50
0.50
1.5
December 1990
9
other
inputs at
VCC or
GND
Philips Semiconductors
Product specification
Triple 2-channel analog
multiplexer/demultiplexer with latch
74HC/HCT4353
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
−40 to +85
+25
min. typ. max. min. max.
−40 to +125
min.
UNIT V
CC
(V)
VEE
OTHER
(V)
max.
tPHL/ tPLH
propagation delay
Vis to Vos
5
4
12
8
15
10
18
12
ns
4.5
4.5
0
RL = ∞;
−4.5 CL = 50 pF
(see Fig.18)
tPZH/ tPZL
turn “ON” time
E1 to Vos
26
22
55
45
69
56
83
68
ns
4.5
4.5
0
RL = 1 kΩ;
−4.5 CL = 50 pF
(see Fig.19)
tPZH/ tPZL
turn “ON” time
E2 to Vos
22
18
50
40
63
50
75
60
ns
4.5
4.5
0
RL = 1 kΩ;
−4.5 CL = 50 pF
(see Fig.19)
tPZH/ tPZL
turn “ON” time
LE to Vos
21
17
45
40
56
50
68
60
ns
4.5
4.5
0
RL = 1 kΩ;
−4.5 CL = 50 pF
(see Fig.19)
tPZH/ tPZL
turn “ON” time
Sn to Vos
25
19
50
45
63
56
75
68
ns
4.5
4.5
0
RL = 1 kΩ;
−4.5 CL = 50 pF
(see Fig.19)
tPHZ/ tPLZ
turn “OFF” time
E1 to Vos
23
19
50
40
63
50
75
60
ns
4.5
4.5
0
RL = 1 kΩ;
−4.5 CL = 50 pF
(see Fig.19)
tPHZ/ tPLZ
turn “OFF” time
E2 to Vos
27
23
50
40
63
50
75
60
ns
4.5
4.5
0
RL = 1 kΩ;
−4.5 CL = 50 pF
(see Fig.19)
tPHZ/ tPLZ
turn “OFF” time
LE to Vos
19
19
40
40
50
50
60
60
ns
4.5
4.5
0
RL = 1 kΩ;
−4.5 CL = 50 pF
(see Fig.19)
tPHZ/ tPLZ
turn “OFF” time
Sn to Vos
22
22
45
45
56
56
68
68
ns
4.5
4.5
0
RL = 1 kΩ;
−4.5 CL = 50 pF
(see Fig.19)
tsu
set-up time
Sn to LE
12
15
7
9
15
19
18
22
ns
4.5
4.5
0
RL = 1 kΩ;
−4.5 CL = 50 pF
(see Fig.20)
th
hold time
Sn to LE
5
5
0
−2
5
5
5
5
ns
4.5
4.5
0
RL = 1 kΩ;
−4.5 CL = 50 pF
(see Fig.20)
tW
LE minimum pulse
width HIGH
16
16
3
5
20
20
24
24
ns
4.5
4.5
0
RL = 1 kΩ;
−4.5 CL = 50 pF
(see Fig.20)
December 1990
10
Philips Semiconductors
Product specification
Triple 2-channel analog
multiplexer/demultiplexer with latch
74HC/HCT4353
Fig.9
Fig.8 Test circuit for measuring RON.
Typical RON as a function of input voltage
Vis for Vis = 0 to VCC − VEE.
Fig.10 Test circuit for measuring OFF-state current.
Fig.11 Test circuit for measuring ON-state current.
December 1990
11
Philips Semiconductors
Product specification
Triple 2-channel analog
multiplexer/demultiplexer with latch
74HC/HCT4353
ADDITIONAL AC CHARACTERISTICS FOR 74HC/HCT
Recommended conditions and typical values
GND = 0 V; Tamb = 25 °C
SYMBOL PARAMETER
typ.
UNIT
VCC
(V)
VEE
(V)
Vis(p-p)
(V)
CONDITIONS
sine-wave distortion
f = 1 kHz
0.04
0.02
%
%
2.25
4.5
−2.25
−4.5
4.0
8.0
RL = 10 kΩ; CL = 50 pF
(see Fig.14)
sine-wave distortion
f = 10 kHz
0.12
0.06
%
%
2.25
4.5
−2.25
−4.5
4.0
8.0
RL = 10 kΩ; CL = 50 pF
(see Fig.14)
switch “OFF” signal
feed-through
−50
−50
dB
dB
2.25
4.5
−2.25
−4.5
note 1
RL = 600 Ω; CL = 50 pF
f = 1 MHz (see Figs 12 and 15)
crosstalk between
any two switches/
multiplexers
−60
−60
dB
dB
2.25
4.5
−2.25
−4.5
note 1
RL = 600 Ω; CL = 50 pF;
f = 1 MHz (see Fig.16)
V(p−p)
crosstalk voltage between
control and any switch
(peak-to-peak value)
110
220
mV
mV
4.5
4.5
0
−4.5
fmax
minimum frequency response
(−3dB)
160
170
MHz
MHz
2.25
4.5
−2.25
−4.5
CS
maximum switch capacitance
independent (Y)
common (Z)
5
12
pF
pF
RL = 600 Ω; CL = 50 pF;
f = 1 MHz (E1, E2 or Sn,
square-wave between
VCC and GND, tr = tf = 6 ns)
(see Fig.17)
note 2
RL = 50 Ω; CL = 10 pF
(see Figs 13 and 14)
Notes to the AC characteristics
1. Adjust input voltage Vis to 0 dBm level (0 dBm = 1 mW into 600 Ω).
2. Adjust input voltage Vis to 0 dBm level at Vos for 1 MHz (0 dBm = 1 mW into 50 Ω).
General note
Vis is the input voltage at an nYn or nZ terminal, whichever is assigned as an input.
Vos is the output voltage at an nYn or nZ terminal, whichever is assigned as an output.
Test conditions:
VCC = 4.5 V; GND = 0 V; VEE = − 4.5 V;
RL = 50 Ω; Rsource = 1 kΩ.
Fig.12 Typical switch “OFF” signal feed-through as a function of frequency.
December 1990
12
Philips Semiconductors
Product specification
Triple 2-channel analog
multiplexer/demultiplexer with latch
74HC/HCT4353
Test conditions:
VCC = 4.5 V; GND = 0 V; VEE = − 4.5 V;
RL = 50 Ω; Rsource = 1 kΩ.
Fig.13 Typical frequency response.
Fig.14 Test circuit for measuring sine-wave
distortion and minimum frequency
response.
Fig.15 Test circuit for measuring switch
“OFF” signal feed-through.
(a) = channel ON condition
(b) channel OFF condition.
Fig.16 Test circuits for measuring crosstalk between any two switches/multiplexers.
The crosstalk is defined as follows
(oscilloscope output):
Fig.17 Test circuit for measuring crosstalk between control and any switch.
December 1990
13
Philips Semiconductors
Product specification
Triple 2-channel analog
multiplexer/demultiplexer with latch
74HC/HCT4353
AC WAVEFORMS
(1) HC : VM = 50%; VI = GND to VCC.
HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.19 Waveforms showing the turn-ON and
turn-OFF times.
Fig.18 Waveforms showing the input (Vis) to
output (Vos) propagation delays.
(1) HC : VM = 50%; VI = GND to VCC.
HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.20 Waveforms showing the set-up and hold
times from Sn inputs to LE input, and
minimum pulse width of LE.
December 1990
14
Philips Semiconductors
Product specification
Triple 2-channel analog
multiplexer/demultiplexer with latch
74HC/HCT4353
TEST CIRCUIT AND WAVEFORMS
Conditions
TEST
SWITCH
Vis
tPZH
tPZL
tPHZ
tPLZ
others
VEE
VCC
VEE
VCC
open
VCC
VEE
VCC
VEE
pulse
tr; tf
FAMILY
AMPLITUDE
VM
fmax;
PULSE WIDTH
OTHER
74HC
VCC
50%
< 2 ns
6 ns
74HCT
3.0 V
1.3 V
< 2 ns
6 ns
CL
=
load capacitance including jig and probe capacitance (see AC CHARACTERISTICS for values).
RT
=
termination resistance should be equal to the output impedance ZO of the pulse generator.
tr
=
tf = 6 ns; when measuring fmax, there is no constraint on tr, tf with 50% duty factor.
Fig.21 Test circuit for measuring AC performance.
Conditions
TEST
SWITCH
Vis
tPZH
tPZL
tPHZ
tPLZ
others
VEE
VCC
VEE
VCC
open
VCC
VEE
VCC
VEE
pulse
tr; tf
FAMILY
AMPLITUDE
VM
fmax;
PULSE WIDTH
OTHER
74HC
VCC
50%
< 2 ns
6 ns
74HCT
3.0 V
1.3 V
< 2 ns
6 ns
CL
=
load capacitance including jig and probe capacitance (see AC CHARACTERISTICS for values).
RT
=
termination resistance should be equal to the output impedance ZO of the pulse generator.
tr
=
tf = 6 ns; when measuring fmax, there is no constraint on tr, tf with 50% duty factor.
Fig.22 Input pulse definitions.
December 1990
15
Philips Semiconductors
Product specification
Triple 2-channel analog
multiplexer/demultiplexer with latch
74HC/HCT4353
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990
16