PHILIPS SCN2652AC2A44

INTEGRATED CIRCUITS
SCN2652/SCN68652
Multi-protocol communications controller
(MPCC)
Product specification
IC19 Data Handbook
1995 May 01
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
DESCRIPTION
SCN2652/SCN68652
FEATURES
• DC to 2Mbps data rate
• Bit-oriented protocols (BOP): SDLC, ADCCP, HDLC
• Byte-control protocols (BCP): DDCMP, BISYNC (external CRC)
• Programmable operation
The SCN2652/68652 Multi-Protocol Communications Controller
(MPCC) is a monolithic n-channel MOS LSI circuit that formats,
transmits and receives synchronous serial data while supporting
bit-oriented or byte control protocols. The chip is TTL compatible,
operates from a single +5V supply, and can interface to a processor
with an 8 or 16-bit bidirectional data bus.
– 8 or 16-bit tri-state data bus
– Error control – CRC or VRC or none
APPLICATIONS
– Character length – 1 to 8 bits for BOP or 5 to 8 bits for BCP
• Intelligent terminals
• Line controllers
• Network processors
• Front end communications
• Remote data concentrators
• Communication test equipment
• Computer to computer links
– SYNC or secondary station address comparison for BCP-BOP
– Idle transmission of SYNC/FLAG or MARK for BCP-BOP
• Automatic detection and generation of special BOP control
sequences, i.e., FLAG, ABORT, GA
• Zero insertion and deletion for BOP
• Short character detection for last BOP data character
• SYNC generation, detection, and stripping for BCP
• Maintenance mode for self-testing
• TTL compatible
• Single +5V supply
PIN CONFIGURATION
INDEX
CORNER
CE
1
40 MM
RxC
2
39 TxC
RxSI
3
38 TxSQ
S/F
4
37 TxE
RxA
5
36 TxU
RxDA
6
35 TxBE
RxSA
7
34 TxA
RxE
8
33 RESET
6
40
1
7
39
PLCC
29
17
GND 9
DB08 10
18
32 VCC
DIP
Pin Function
31 DB00
DB09 11
30 DB01
DB10 12
29 DB02
DB11 13
28 DB03
DB12 14
27 DB04
DB13 15
26 DB05
DB14 16
25 DB06
DB15 17
24 DB07
R/W 18
23 DBEN
A2 19
22 BYTE
A1 20
21 A0
28
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
NC
CE
RxC
RxSI
S/F
RxA
RxDA
RxSA
RxE
GND
DB08
NC
DB09
DB10
DB11
DB12
DB13
DB14
DB15
R/W
A2
A1
Pin Function
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
NC
A0
BYTE
DBEN
DB07
DB06
DB05
DB04
DB03
DB02
DB01
NC
DB00
VCC
RESET
TxA
TxBE
TxU
TxE
TxSQ
TxC
MM
TOP VIEW
NOTE: DB00 is least significant bit, highest number
(that is, DB15, A2) is most significant bit.
SD00057
Figure 1. Pin Configuration
1995 May 01
2
853-1068 15179
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
ORDERING CODE
VCC = 5V +5%
PACKAGES
Commercial
0°C to +70°C
DWG #
Industrial
-40°C to +85°C
40-Pin Ceramic Dual In-Line Package (DIP)
SCN2652AC2F40 / SCN68652AC2F40
0590B
40-Pin Plastic Dual In-Line Package (DIP)
SCN2652AC2N40 / SCN68652AC2N40
Contact Factory
SOT129-1
44-Pin Square Plastic Lead Chip Carrier (PLCC)
SCN2652AC2A44 / SCN68652AC2A44
Contact Factory
SOT187-2
ABSOLUTE MAXIMUM RATINGS1
SYMBOL
PARAMETER
TA
Operating ambient temperature2
TSTG
Storage temperature
RATING
UNIT
Note 4
°C
–65 to +150
°C
VCC
All inputs with respect to GND3
–0.3 to +7
V
NOTES:
1. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or at any other condition above those indicated in the operation sections of this specification
is not implied.
2. For operating at elevated temperatures the device must be derated based on +150°C maximum junction temperature.
3. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.
4. Parameters are valid over operating temperature range unless otherwise specified. See ordering code table for applicable temperature
range and operating supply range.
BLOCK DIAGRAM
DATA
BUS
BUFFER
DB15–
DB00
16 BITS
8 BITS
PARAMETER CONTROL
SYNC/ADDRESS
REGISTER
PARAMETER
CONTROL
REGISTER
PCSAR
VCC
GND
PCR
16
RECEIVER
DATA/STATUS
REGISTER
RESET
RDSR
TRANSMITTER
DATA/STATUS
REGISTER
TDSR
MM
INTERNAL
BUS
A2–A0
16
16
BYTE
R/W
CE
READ/
WRITE
LOGIC
AND
CONTROL
RECEIVER
LOGIC AND
CONTROL
DBEN
S/F
RxE
RxA
RxDA
RxSA
RxC RxSI
TRANSMITTER
LOGIC AND
CONTROL
TxC TxSO
TxE
TxA
TxBE
TxU
SD00058
Figure 2. Block Diagram
1995 May 01
3
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
PIN DESCRIPTION
MNEMONIC
PIN NO.
TYPE
NAME AND FUNCTION
DB15–DB00
17–10
24–31
I/O
A2–A0
19–21
I
Address Bus: A2–A0 select internal registers. The four 16-bit registers can be addressed on a word or
byte basis. See Register Address section.
BYTE
22
I
Byte: Single byte (8-bit) data bus transfers are specified when this input is high. A low level specifies
16-bit data bus transfers.
CE
1
I
Chip Enable: A high input permits a data bus operation when DBEN is activated.
R/W
18
I
Read/Write: R/W controls the direction of data bus transfer. When high, the data is to be loaded into the
addressed register. A low input causes the contents of the addressed register to be presented on the
data bus.
DBEN
23
I
Data Bus Enable: After A2–A0, CE, BYTE and R/W are set up, DBEN may be strobed. During a read,
the 3-state data bus (DB) is enabled with information for the processor. During a write, the stable data is
loaded into the addressed register and TxBE will be reset if TDSR was addressed.
RESET
33
I
Reset: A high level initializes all internal registers (to zero) and timing.
MM
40
I
Maintenance Mode: MM internally gates TxSO back to RxSI and TxC to RxC for off line diagnostic
purposes. The RxC and RxSI inputs are disabled and TxSO is high when MM is asserted.
RxE
8
I
Receiver Enable: A high level input permits the processing of RxSI data. A low level disables the
receiver logic and initializes all receiver registers and timing.
Data Bus: DB07–DB00 contain bidirectional data while DB15–DB08 contain control and status
information to or from the processor. Corresponding bits of the high and low order bytes can be wire
OR’ed onto an 8-bit bus. The data bus is floating if either CE or DBEN are low.
RxA
5
O
Receiver Active: RxA is asserted when the first data character of a message is ready for the processor.
In the BOP mode this character is the address. The received address must match the secondary station
address if the MPCC is a secondary station. In BCP mode, if strip-SYNC (PCSAR13) is set, the first
non-SYNC character is the first data character; if strip-SYNC is zero, the character following the second
SYNC is the first data character. In the BOP mode, the closing FLAG resets RxA. In the BCP mode, RxA
is reset by a low level at RxE.
RxDA*
6
O
Receiver Data Available: RxDA is asserted when an assembled character is in RDSRL and is ready to
be presented to the processor. This output is reset when RDSRL is read.
RxC
2
I
Receiver Clock: RxC (1X) provides timing for the receiver logic. The positive going edge shifts serial
data into the RxSR from RxSI.
S/F
4
O
SYNC/FLAG: S/F is asserted for one RxC clock time when a SYNC or FLAG character is detected.
RxSA*
7
O
Receiver Status Available: RxSA is asserted when there is a zero to one transition of any bit in RDSRH
except for RSOM. It is cleared when RDSRH is read.
RxSI
3
I
Receiver Serial Input: RxSI is the received serial data. Mark = ‘1’, space = ‘0’.
TxE
37
I
Transmitter Enable: A high level input enables the transmitter data path between TDSRL and TxSO. At
the end of a message, a low level input causes TxSO = 1(mark) and TxA = 0 after the closing FLAG
(BOP) or last character (BCP) is output on TxSO.
TxA
34
O
Transmitter Active: TxA is asserted after TSOM (TDSR8) is set and TxE is raised. This output will reset
when TxE is low and the closing FLAG (BOP) or last character (BCP) has been output on TxSO.
TxBE*
35
O
Transmitter Buffer Empty: TxBE is asserted when theTDSR is ready to be loaded with new control
information or data. The processor should respond by loading theTDSR which resets TxBE.
TxU*
36
O
Transmitter Underrun: TxU is asserted during a transmit sequence when the service of TxBE has been
delayed for one character time. This indicates the processor is not keeping up with the transmitter. Line
fill depends on PCSAR11. TxU is reset by RESET or setting of TSOM (TDSR8), synchronized by the
falling edge of TxC.
TxC
39
I
Transmitter Clock: TxC (1X) provides timing for the transmitter logic. The positive going edge shifts
data out of the TxSR to TxSO.
TxSO
38
O
Transmitter Serial Output: TxSO is the transmitted serial data. Mark = ‘1’, space = ‘0’.
VCC
32
I
+5V: Power supply.
GND
9
I
Ground: 0V reference ground.
*Indicates possible interrupt signal
1995 May 01
4
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
Table 1.
SCN2652/SCN68652
Register Access
REGISTERS
NO. OF BITS
DESCRIPTION*
16
PCSARH and PCR contain parameters common to the
receiver and transmitter. PCSARL contains a programmable
SYNC character (BCP) or secondary station address (BOP).
Addressable
PCSAR
Parameter control sync/
address register
PCR
Parameter control register
8
RDSRH contains receiver status information.
RDSR
Receive data/status register
16
RDSRL = RxDB contains the received assembled character.
TDSR
Transmit data/status register
16
TDSRH contains transmitter command and status
information. TDSRL = TxDB contains the character to be
transmitted
Non-Addressable
CCSR
Control character shift register
8
HSR
Holding shift register
16
RxSR
Receiver shift register
8
TxSR
Transmitter shift register
8
RxCRC
Receiver CRC accumulation
register
16
TxCRC
Transmitter CRC generation
register
16
These registers are used for character assembly (CSSR
(CSSR,
HSR,, RxSR),
), disassembly
y (TxSR),
(
), and CRC
accumulation/generation (RxCRC, TxCRC).
NOTES:
*H = High byte – bits 15–8
L = Low byte – bits 7–0
Table 2.
Error Control
CHARACTER
FCS
BCC
Table 3.
DESCRIPTION
Frame check sequence is transmitted/received
as 16 bits following the last data character of a
BOP message. The divisor is usually
CRC–CCITT (X16 + X12 + X5 + 1) with dividend
preset to 1’s but can be other wise determined
by ECM. The inverted remainder is transmitter as
the FCS.
15
14
APA
PROTO
SS/GA
14
13
15
13
TxCL
PCR
15
RDSR
RERR
TDSR
TERR
15
14
13
12
A B C
14
13
12
NOT DEFINED
FLAG
01111110
Frame message
ABORT
11111111 generation
Terminate communication
GA
01111111
Terminate loop mode
repeater function
Address
(PCSARL)1
Secondary station address
(PCSARL) or
(TxDB)2 generation
Character synchronization
BCP
SYNC
NOTES:
1. ( ) = contents of.
2. For IDLE = 0 or 1 respectively.
11
SAM
IDLE
10
11
10
ROR
RAB/
GA
10
9
8
7
6
ECM
12
11
10
Tx
Rx
CL
CL
E
E
11
5
4
3
2 1
0
S/AR
9
8
RxCL
9
8
REOM RSOM
9
RxDB
8
TABORT TEOM TSOM
TxDB
NOTE:
Refer to Register Formats for mnemonics and description.
SD00059
Figure 3. Short Form Register Bit Formats
1995 May 01
FUNCTION
01111111 detection
12
TGA
BIT PATTERN
BOP
Block check character is transmitted/received as
two successive characters following the last data
character of a BCP message. The polynomial is
CRC–16 (X16 + X15 + X2 + 1) or CRC–CCITT
with dividend preset to 0’s (as specified by
ECM). The true remainder is transmitted as the
BCC.
PCSAR
Special Characters
OPERATION
5
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
BCP . CRC
TO
RDSRL
BOP . CRC
BCP . CRC
8
RxSI
M
U
X
SYNC
FF
SEL
CCSR (8)
M
U
X
HSR (16)
RxSR (8)
BOP . CRC
1-BIT
DELAY
ZERO (BOP)
DELETION
LOGIC
SYNC/FLAG1
FROM
XMITTER
8
COMPARATOR
MM
ZERO
DELETION
CONTROL
PARITY (BCP)
LOGIC
BOP
S/F
M
U
X
BCP
CRC–16 (BCP) OR
CCRC–CCITT
(BOP)
RxCRC ACC
RESET
RxE
RxA
RxDA
RxSA
CRC–16 = 0
COMPARATOR
CRC–CCIT = F0B8
RERR
RECEIVER
CONTROL
LOGIC
RxC
NOTES:
1. Detected in SYNC FF and 7 MS bits of CCSR.
2. In BOP mode, a minimum of two data characters must be received to turn the receiver active.
SD00060
Figure 4. MPCC Receiver Data Path
FROM OR PCSAR (SYNC)
L
TDSARL
RESET
TxE
TxA
TxBE
TRANSMITTER
CONTROL
LOGIC
SYNC
FF
TXSR (8)
TxSO
1 BIT
DELAY
TxU
M
U
X
TXCRC ACC (16)
CRC–16 OR CRC–CCITT
SEL1, 2
BOP
ZERO
INSERTION
LOGIC
ZERO
INSERTION
CONTROL
BCP
PARITY
GENERATION
TxC
CONTROL
CHARACTER
GENERATOR
FLAG
ABORT
GA
NOTES:
1. TxCRC selected if TEOM = 1 and the last data character has been shifted out of TxSR.
2. In BCP parity selected will be generated after each character is shifted out of TxSR.
SD00088
Figure 5. MPCC Transmitter Data Path
1995 May 01
6
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
should check RDSR9–15 each time RxSA is asserted. If RDSR9 is
set, then RDSR12–15 should be examined.
FUNCTIONAL DESCRIPTION
The MPCC can be functionally partitioned into receiver logic,
transmitter logic, registers that can be read or loaded by the
processor, and data bus control circuitry. The register bit formats are
shown in Figure 3 while the receiver and transmitter data paths are
depicted in Figures 4 and 3.
Receiver character length may be changed dynamically in response
to RxDA: read the character in RxDB and write the new character
length into RxCL. The character length will be changed on the next
receiver character boundary. A received residual (short) character
will be transferred into RxDB after the previous character in RxDB
has been read, i.e. there will not be an overrun. In general the last
two characters are protected from overrun.
RECEIVER OPERATION
The CRC–CCITT, if specified by PCSAR8–10, is accumulated in
RxCRC on each character following the FLAG. When the closing
FLAG is detected in the CCSR, the received CRC is in the 16-bit
HSR. At that time, the Receive End of Message bit (REOM) will be
set; RxSA and RxDA will be asserted. The processor should read
the last data character in RDSRL and the receiver status in
RDSR9–15. If RDSR15 = 1, there has been a transmission error; the
accumulated CRC–CCITT is incorrect. If RDSR12–14 ≠ 0, last data
character is not of prescribed length. Neither the received CRC nor
closing FLAG are presented to the processor. The processor may
drop RxE or leave it active at the end of the received message.
General
After initializing the parameter control registers (PCSAR and PCR),
the RxE input must be set high to enable the receiver data path. The
serial data on the RxSI is synchronized and shifted into an 8-bit
Control Character Shift Register (CCSR) on the rising edge of RxC.
A comparison between CCSR contents and the FLAG (BOP) or
SYNC (BCP) character is made until a match is found. At that time,
the S/F output is asserted for one RxC time and the 16-bit Holding
Shift Register (HSR) is enabled. The receiver then operates as
described below.
BOP Operation
RxBCP Operation
A flowchart of receiver operation in BOP mode appears in Figure 6.
Zero deletion (after five ones are received) is implemented on the
received serial data so that a data character will not be interpreted
as a FLAG, ABORT, or GA. Bits following the FLAG are shifted
through the CCSR, HSR, and into the Receiver Shift Register
(RxSR). A character will be assembled in the RxSR and transferred
to the RDSRL for presentation to the processor. At that time the
RxDA output will be asserted and the processor must take the
character no later than one RxC time after the next character is
assembled in the RxSR. If not, an overrun (RDSR11 = 1) will occur
and succeeding characters will be lost.
The operation of the receiver in BCP mode is shown in Figure 7.
The receiver initially searches for two successive SYNC characters,
of length specified by PCR8–10, that match the contents of PCSARL.
The next non-SYNC character or next SYNC character, if stripping is
not specified (PCSAR13 = 0), causes RxA to be asserted and
enables the receiver data path. Once enabled, all characters are
assembled in RxSR and loaded into RDSRL. RxDA is active when a
character is available in RDSRL. RxSA is active on a 0 to 1
transition of any bit in RDSRH. The signals are cleared when RDSRl
or RDSRH are read respectively.
If CRC–16 error control is specified by PCSAR8–10, the processor
must determine the last character received prior to the CRC field.
When that character is loaded into RDSRL and RxDA is asserted,
the received CRC will be in CCSR and HSRL. To check for a
transmission error, the processor must read the receiver status
(RDSRH) and examine RDSR15. This bit will be set for one
character time if an error free message has been received. If
RDSR15 = 0, the CRC–16 is in error. The state of RDSR15 in BCP
CRC mode does not set RxSA. Note that this bit should be
examined only at the end of a message. The accumulated CRC will
include all characters starting with the first non-SYNC character if
PCSAR13 = 1, or the character after the opening two SYNCs if
PCSAR13 = 0. This necessitates external CRC generation/checking
when supporting IBM’s
The first character following the FLAG is the secondary station
address. If the MPCC is a secondary station (PCSAR12 = 1), the
contents of RxSR are compared with the address stored in
PCSARL. A match indicates the forthcoming message is intended
for the station; the RxA output is asserted, the character is loaded
into RDSRL, RxDA is asserted and the Receive Start of Message bit
(RSOM) is set. No match indicates that another station is being
addressed and the receiver searches for the next FLAG.
If the MPCC is a primary station, (PCSAR12 = 0), no secondary
address check is made; RxA is asserted and RSOM is set once the
first non-FLAG character has been loaded into RDSRL and RxDA
has been asserted. Extended address field can be supported by
software if PCSAR12 = 0.
When the 8 bits following the address character have been loaded
into RDSRL and RxDA has been asserted, RSOM will be cleared.
The processor should read this 8-bit character and interpret it as the
Control field.
BISYNC. This can be accomplished using the Philips
Semiconductors SCN2653 Polynomial Generator/Checker. See
Typical Applications.
If VRC has been selected for error control, parity (odd or even) is
regenerated on each character and checked when the parity bit is
received. A discrepancy causes RDSR15 to be set and RxSA to be
asserted. This must be sensed by the processor. The received parity
bit is stripped before the character is presented to the processor.
Received serial data that follows is read and interpreted as the
information field by the processor. It will be assembled into character
lengths as specified by PCR8–10. As before, RxDA is asserted each
time a character has been transferred into RDSRL and is cleared
when RDSRL is read by the processor. RDSRH should only be read
when RxSA is asserted. This occurs on a zero to one transition of
any bit in RDSRH except for RSOM. RxSA and all bits in RDSRH
except RSOM are cleared when RDSRH is read. The processor
1995 May 01
SCN2652/SCN68652
When the processor has read the last character of the message, it
should drop RxE which disables the receiver logic and initializes all
receiver registers and timing.
7
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
INITIALIZE PCSAR, PCR
PROCESSOR
A
RxE
= 1?
RxE = 1
NO
YES
* TEST MADE
EVERY RxC TIME
FLAG
IN CCSR*
?
NO
YES
S/F = 1
FOR ONE RxC
BIT TIME
FLAG
IN CCSR*
?
YES
NO
ASSEMBLE CHARACTER
IN RxSR. ZERO DELETION,
ACCUMULATE CRC IF
SPECIFIED
NO
IS
IT 1st
CHARACTER
AFTER FLAG
?
SECONDARY
STATION
ADDRESS
YES
SEC.
STATION
MODE
?
START OF
MESSAGE
RxA = 1
RSOM = 1
FOR ONE
CHARACTER
TIME
RxDA = 1
(PROCESSOR
SHOULD
READ RxDB)
RXSA = 1
(PROCESSOR SHOULD
READ AND EXAMINE
RDSRH – REOM, RAB/GA,
ROVRN, ABC, RERR)
(1) OVERRUN (ROVRN)
CAUSES LOSS OF
SUBSEQUENT
CHARACTERS
YES
(PCSAR12 = 1)
IS
CHARACTER
= PCSARL
?
NO
(PCSAR12 = 0)
NO
YES
RxSR → RxDB
RECEIVER
STATUS BIT 0 → 1
EXCEPT RSOM
?
NO
YES
FLAG
IN CCSR*
?
NO
YES – END OF MESSAGE
S/F = 1 FOR ONE RxC
BIT TIME
REOM = 1, RxA = 0
RxE → 0
?
NO
YES
A
SD00061
Figure 6. BOP Receive
TRANSMITTER OPERATION
General
TxBOP Operation
Transmitter operation for BOP is shown in Figure 8. A FLAG is sent
after the processor sets the Transmit Start of Message bit (TSOM)
and raises TxE. The FLAG is used to synchronize the message that
follows. TxA will also be asserted. When TxBE is asserted by the
After the parameter control registers (PCSAR and PCR) have been
initialized, TxSO is held at mark until TSOM (TDSR8) is set and TxE
is raised. Then, transmitter operation depends on protocol mode.
1995 May 01
8
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
CRC–16, if specified by PCSAR8–10, is generated on each
character transmitted from TDSRL when TSOM =0. The processor
must set TEOM = 1 after the last data character has been sent to
TxSR (TxBE = 1). The MPCC will finish transmitting the last data
character and the CRC–16 field before sending SYNC characters
which are transmitted as long as TEOM = 1. If SYNCs are not
desired after CRC–16 transmission, the processor should clear
TEOM and lower TxE when the TxBE corresponding to the start of
CRC–16 transmission is asserted. When TEOM = 0, the line is
marked and a new message may be initiated by setting TSOM and
raising TxE.
MPCC, the processor should load TDSRL with the first character of
the message. TSOM should be cleared at the same time TDSRL is
loaded (16-bit data bus) or immediately thereafter (8-bit data bus).
FLAGS are sent as long as TSOM = 1. For counting the number of
FLAGs, the processor should reassert TSOM in response to the
assertion of TxBE.All succeeding characters are loaded into TDSRL
by the processor when TxBE = 1. Each
character is serialized in TxSR and transmitted on TxSO. Internal
zero insertion logic stuffs a “0” into the serial bit stream after five
successive “1s” are sent. This insures a data character will not
match a FLAG, ABORT, or GA reserved control character. As each
character is transmitted, the Frame Check Sequence (FCS) is
generated as specified by Error Control Mode (PCSAR8–10). The
FCS should be the CRC–CCITT polynomial (X16 + X12 + X5 + 1)
preset to 1s. If an underrun occurs (processor is not keeping up with
the transmitter), TxU and TERR (TDSR15) will be asserted with
ABORT or FLAG used as the TxSO line fill depending on the state
of IDLE (PCSAR11). The processor must set TSOM to reset the
underrun condition. To retransmit the message, the processor
should proceed with the normal start of message sequence.
If VRC is specified, it is generated on each data character and the
data character length must not exceed 7 bits. For software LRC or
CRC, TEOM should be set only if SYNC’s are required at the end of
the message block.
SPECIAL CASE: The capability to transmit 16 spaces is provided
for line turnaround in half duplex mode or for a control recovery
situation. This is achieved by setting TSOM and TEOM, clearing
TEOM when TxBE = 1, and proceeding as required.
PROGRAMMING
A residual character of 1 to 7 bits may be transmitted at the end of
the information field. In response to TxBE, write the residual
character length into TxCL and load TxDB with the residual
character. Dynamic alteration of character length should be done in
exactly the same sequence. The character length will be changed
on the next transmit character boundary.
Prior to initiating data transmission or reception, PCSAR and PCR
must be loaded with control information from the processor. The
contents of these registers (see Register Format section) will
configure the MPCC for the user’s specific data communication
environment. These registers should be loaded during power-on
initialization and after a reset operation. They can be changed at any
time that the respective transmitter or receiver is disabled.
After the last data character has been loaded into TDSRL and sent
to TxSR (TxBE = 1), the processor should set TEOM (TDSR9). The
MPCC will finish transmitting the last character followed by the FCS
and the closing FLAG. The processor should clear TEOM and drop
TxE when the next TxBE is asserted. This corresponds to the start
of closing FLAG transmission. When TxE has been dropped. TxA
will be low 1 1/2 bit times after the last bit of the closing FLAG has
been transmitted. TxSO will be marked after the closing FLAG has
been transmitted.
The default value for all registers is zero. This corresponds to BOP,
primary station mode, 8-bit character length, FCS = CRC–CCITT
preset to 1s.
For BOP mode the character length register (PCR) may be set to
the desired values during system initialization. The address and
control fields will automatically be 8-bits. If a residual character is to
be transmitted, TxCL should be changed to the residual character
length prior to transmission of that character.
If TxE and TEOM are high, the transmitter continues to send
FLAGs. The processor may initiate the next message by resetting
TEOM and setting TSOM, or by loading TDSRL with a data
character and then simply resetting TSOM (without setting TSOM).
DATA BUS CONTROL
The processor must set up the MPCC register address (A2–A0),
chip enable (CE), byte select (BYTE), and read/write (R/W) inputs
before each data bus transfer operation.
TxBCP Operation
Transmitter operation for BCP mode is shown in Figure 9. TxA will
be asserted after TSOM = 1 and TxE is raised. At that time SYNC
characters are sent from PCSARL or TDSRL (IDLE = 0 or 1) as long
as TSOM = 1. TxBE is asserted at the start of transmission of the
first SYNC character. For counting the number of SYNCs, the
processor should reassert TSOM in response to the assertion of
TxBE. When TSOM = 0 transmission is from TDSRL, which must be
loaded with characters from the processor each time TxBE is
asserted. If this loading is delayed for more than one character time,
an underrun results: TxU and TERR are asserted and the
During a read operation (R/W = 0), the leading edge of DBEN will
initiate an MPCC read cycle. The addressed register will place its
contents on the data bus. If BYTE = 1, the 8-bit byte is placed on
DB15–08 or DB07–00 depending on the H/L status of the register
addressed. Unused bits in RDSRL are zero. If BYTE = 0, all 16 bits
(DB15–00) contain MPCC information. The trailing edge of DBEN
will reset RxDA and/or RxSA if RDSRL or RDSRH is addressed
respectively.
DBEN acts as the enable and strobe so that the MPCC will not
begin its internal read cycle until DBEN is asserted.
TxSO line fill depend on IDLE (PCSAR11). The processor must set
TSOM and retransmit the message to recover. This is not
compatible with IBM’s BISYNC, so that the user must not underrun
when supporting that protocol.
1995 May 01
SCN2652/SCN68652
During a write operation (R/W = 1), data must be stable on DB15–08
and/or DB07–00 prior to the leading edge of DBEN. The stable data
is strobed into the addressed register by DBEN. TxBE will be
cleared if the addressed register was TDSRH or TDSRL.
9
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
PROCESSOR
SCN2652/SCN68652
INITIALIZE PCSAR, PCR
A
RxE
= 1?
RxE = 1
NO
YES
SYNC
DETECT1
IN CCSR?
NO
YES
SYNC
DETECT2
IN CCSR?
S/F = 1 FOR ONE
RxC BIT TIME
NO
YES
SYNC
DETECT IN
CCSR?
YES
NO
STRIP
SYNC (PCSAR13)
= 1?
YES
NO
RxA = 1
(1) SYNCs ARE ASSEMBLED
(2) OVERRUN (ROVRN) CAUSES
LOSS OF SUBSEQUENT
CHARACTERS
ASSEMBLE CHARACTER
IN RxSR, STRIP VRC IF
SPECIFIED, ACCUMULATE
CRC IF SPECIFIED
RxDA = 1
(PROCESSOR
SHOULD READ
RxDB)
RxSR → RxDB
ANY
RECEIVER
STATUS BIT
0→1
?
RxSA = 1
(PROCESSOR SHOULD
READ AND EXAMINE
RDSRH – ROVRN,
RERR (IF VRC
SPECIFIED)
NO
YES
RxE
= 0?
RxE = 0
WHEN LAST
CHARACTER HAS
BEEN SERVICED
NO
YES
A
NOTES:
1. Test made every RxC time.
2. Test made on Rx character boundary.
SD00062
Figure 7. BCP Receive
1995 May 01
10
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
(PROCESSOR MUST CLEAR
TABORT/GA IN RESPONSE
TO TxBE = 1)
INITIALIZE PCSAR, PCR, TDSRH
A
TxSO = MARK
TSOM
TxE =
1?
TSOM = 1
TxE = 1
NO
YES
B
TxA = 1
TxBE = 1
PROCESSOR
SHOULD LOAD
TxDB AND
TSOM = 0)
TRANSMIT FLAG
ON TxSO
TSOM
= 0?
(PROCESSOR MAY
SET TABORT, TGA,
AS REQUIRED)
NO
YES
TABORT
= 1?
YES
TxSO = ABORT = 11111111 IF IDLE = 0
FLAG = 01111110 IF IDLE = 1
NO
ON UNDERRUN:
TxU = 1, TERR = 1
(PROCESSOR
SHOULD
SET TSOM)
TxBE = 1
(PROCESSOR
SHOULD LOAD
TxDB WITH NEXT
DATA CHAR)
UNDER
RUN?
YES
TxSO = ABORT IF IDLE = 0
FLAG IF IDLE = 1
NO
NO
SERIALIZE DATA CHARACTER
IN TxDB, ZERO INSERTION,
ACCUMULATE CRC IF
SPECIFIED BY ECM,
TRANSMIT ON TxSO
TSOM
= 1?
YES
B
NO
TEOM
= 1?
YES
TRANSMIT ACCUMULATED
FCS (IF SPECIFIED) AS
INVERTED REMAINDER
TxBE = 1
TRANSMIT FLAG ON TxSO*
TEOM
= 0?
(PROCESSOR SHOULD
RESET TEOM AND SET
TSOM OR DROP TxE)
NO
YES
TSOM
= 1?
B
YES
NO
NO
TxE
= 0?
TxA = 0
YES
A
*GA will be transmitted if TGA is set together with TEOM.
SD00063
Figure 8. BOP Transmit
1995 May 01
11
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
INITIALIZE PCSAR, PCR, TDSRH
PROCESSOR
A
TxSO = MARK
TSOM,
TxE
= 1?
YES
TSOM = 1
TxE = 1
TxA = 1
NO
B
TRANSMIT SYNC ON TxSO
SYNC FROM PCSARL – IDLE = 0
SYNC FROM TxDB IDLE = 1
TxBE = 1
AFTER SYNC(S), PROCESSOR
LOADS DATA CHARACTER
IN TxDB AND TSOM = 0
TSOM
= 0?
NO
YES
SERIALIZE DATA CHARACTER
IN TxDB, GENERATE VRC
OR ACCUMULATE CRC AS
SPECIFIED, TRANSMIT ON TxSO
TxBE = 1
(PROCESSOR
SHOULD LOAD TxDB)
(PROCESSOR SHOULD
GET TEOM AT END OF
MESSAGE IF CRC
SPECIFIED)
TEOM
= 1?
NO
NO
C
UNDERRUN?
YES
YES
TxU = 1, TERR = 1
(PROCESSOR SHOULD
SET TSOM = 1)
TRANSMIT ACCUMULATED
CRC SPECIFIED (IF NO
CRC, TEOM SHOULD = 0)
TxSO = SYNC FROM PCSARL IF IDLE = 0
MARK IF IDLE = 1
UNTIL TSOM = 1
B
TxBE = 1
(PROCESSOR
SHOULD CLEAR
TEOM AND DROP
TxE)
TEOM
= 0?
C
NO
TxSO = SYNC OR TxDB DEPENDING ON
IDLE BIT
YES
TxE
= 0?
TxA = 0
NO
YES
A
SD00064
Figure 9. BCP Transmit
1995 May 01
12
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
Table 4.
MPCC Register Addressing
A2
Byte = 0
A1
A0
REGISTER
(16-Bit Data Bus = DB15 – DB00)
0
0
1
1
Byte = 1
SCN2652/SCN68652
0
1
0
1
X
X
X
X
RDSR
TDSR
PCSAR
PCR*
(8-Bit Data Bus = DB7–0 or DB15–8**)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
RDSRL
RDSRH
TDSRL
TDSRH
PCSARL
PCSARH
PCRL*
PCRH
NOTES:
* PCR lower byte does not exist. It will be all “0”s when read.
** Corresponding high and low order pins must be tied together.
Table 5.
Parameter Control Register (PCR)–(R/W)
BIT
NAME
00–07
Not Defined
08–10
RxCL
MODE
FUNCTION
BOP/BCP
Receiver character length is loaded by the processor when RxCLE = 0. The character length is
valid after transmission of single byte address and control fields have been received.
10
0
0
0
0
1
1
1
1
9
0
0
1
1
0
0
1
1
8
0
1
0
1
0
1
0
1
Char length (bits)
8
1
2
3
4
5
6
7
11
RxCLE
BOP/BCP
Receiver character length enable should be zero when the processor loads RxCL. The
remaining bits of PCR are not affected during loading. Always 0 when read.
12
TxCLE
BOP/BCP
Transmitter character length enable should be zero when the processor loads TxCL. The
remaining bits of PCR are not affected during loading. Always 0 when read.
13–15
TxCL
BOP/BCP
Transmitter character length is loaded by the processor when TxCLe = 0. Character bit length
specification format is identical to RxCL. It is valid after transmission of single byte address and
control fields.
1995 May 01
13
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
Table 6.
Parameter Control SYNC/Address Register (PCSAR)–(R/W)
BIT
NAME
MODE
00–07
S/AR
BOP
BCP
08–10
ECM
11
IDLE
BOP/BCP
BOP
BCP
12
SAM
13
SS/GA
BOP
BOP
BCP
14
PROTO
BOP
BCP
15
1995 May 01
SCN2652/SCN68652
APA
BOP
FUNCTION
SYNC/address register. Contains the secondary station address if the MPCC is a secondary
station. The contents of this register is compared with the first received non-FLAG character
to determine if the message is meant for this station.
SYNC character is loaded into this register by the processor. It is used for receive and
transmit bit synchronization with bit length specified by RxCL and TxCL.
Error Control Mode
10
9
8
Suggested Mode
Char. length
CRC–CCITT preset to 1’s 0
0
0
BOP
1–8
CRC–CCITT preset to 0’s 0
0
1
BCP
8
Not used
0
1
0
–––
CRC–16 preset to 0’s
0
1
1
BCP
8
VRC odd
1
0
0
BCP
5–7
VRC even
1
0
1
BCP
5–7
Not used
1
1
0
–––
No error control
1
1
1
BCP/BOP
5–8
ECM should be loaded by the processor during initialization or when both data paths are idle.
Determines line fill character to be used if transmitter underrun occurs (TxU asserted and
TERR set) and transmission of special characters for BOP/BCP.
IDLE = 0, transmit ABORT characters during underrun and when TABORT = 1.
IDLE = 1, transmit FLAG characters during underrun and when TABORT = 1.
IDLE = 0 transmit initial SYNC characters and underrun line fill characters from theS/AR.
IDLE = 1 transmit initial SYNC characters from TxDB and marks TxSO during underrun.
Secondary Address Mode = 1 if the MPCC is a secondary station. This facilitates automatic
recognition of the received secondary station address. When transmitting, the processor must
load the secondary address into TxDB.
SAM = 0 inhibits the received secondary address comparison which serves to activate the
receiver after the first non-FLAG character has been received.
Strip SYNC/Go Ahead. Operation depends on mode.
SS/GA = 1 is used for loop mode only and enables GA detection. When a GA is detected as a
closing character, REOM and RAB/GA will be set and the processor should terminate the
repeater function. SS/GA = 0 is the normal mode which enables ABORT detection. It causes
the receiver to terminate the frame upon detection of an ABORT or FLAG.
SS/GA = 1, causes the receiver to strip SYNC’s immediately following the first two SYNC’s
detected. SYNC’s in the middle of a message will not be stripped. SS/GA = 0, presents any
SYNC’s after the initial two SYNC’s to the processor.
Determines MPCC Protocol mode
PROTO = 0
PROTO = 1
All parties address. If this bit is set, the receiver data path is enabled by an address field of
‘11111111’ as well as the normal secondary station address.
14
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
Table 7.
Transmit Data/Status Register (TDSR) (R/W except TDSR15)
BIT
NAME
MODE
00–07
TxDB
BOP/BCP
08
TSOM
BOP
BCP
09
SCN2652/SCN68652
TEOM
BOP
BCP
FUNCTION
Transmit data buffer. Contains processor loaded characters to be serialized in TxSR and
transmitted on TxSO.
Transmitter start of message. Set by the processor to initiate message transmission provided
TxE = 1.
TSOM = 1 generates FLAGs. When TSOM = 0 transmission is from TxDB and FCS
generation (if specified) begins. FCS, as specified by PCSAR8–10, should be CRC–CCITT
preset to 1’s.
TSOM = 1 generates SYNCs from PCSARL or transmits from TxDB for IDLE = 0 or 1
respectively. When TSOM = 0 transmission is from TxDB and CRC generation (if specified)
begins.
Transmit end of message. Used to terminate a transmitted message.
TEOM = 1 causes the FCS and the closing FLAG to be transmitted following the transmission
of the data character in TxSR. FLAGs are transmitted until TEOM = 0. ABORT or GA are
transmitted if TABORT or TGA are set when TEOM = 1.
TEOM = 1 causes CRC–16 to be transmitted (if selected) followed by SYNCs from PCSARL
or TxDB (IDLE = 0 or 1). Clearing TEOM prior to the end of CRC–16 transmission (when
TxBE = 1) causes TxSO to be marked following the CRC–16. TxE must be dropped before a
new message can be initiated. If CRC is not selected, TEOM should not be set.
10
TABORT
BOP
Transmitter abort = 1 will cause ABORT or FLAG to be sent (IDLE = 1 or 1) after the current
character is transmitted. (ABORT = 11111111)
11
TGA
BOP
Transmit go ahead (GA) instead of FLAG when TEOM = 1. This facilitates repeater
termination in loop mode. (GA = 01111111)
12–14
Not Defined
15
TERR
Read
only
Transmitter error = 1 indicates the TxDB has not been loaded in time (one character time–1/2
TxC period after TxBE is asserted) to maintain continuous transmission. TxU will be asserted
to inform the processor of this condition. TERR is cleared by setting TSOM. See timing
diagram.
ABORT’s or FLAG’s are sent as fill characters (IDLE = 0 or 1)
SYNC’s or MARK’s are sent as fill characters (IDLE = 0 or 1). For IDLE = 1 the last character
before underrun is not valid.
BOP
BCP
1995 May 01
15
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
Table 8.
SCN2652/SCN68652
Receiver Data/Status Register (RDSR)–(Read Only)
BIT
NAME
MODE
FUNCTION
00–07
RxDB
BOP/BCP
Receiver data buffer. Contains assembled characters from the RxSR. If VRC is specified, the
parity bit is stripped.
08
RSOM
BOP
Receiver start of message = 1 when a FLAG followed by a non-FLAG has been received and
the latter character matches the secondary station if SAM = 1. RxA will be asserted when
RSOM = 1. RSOM resets itself after one character time and has no affect on RxSA.
09
REOM
BOP
Receiver end of message = 1 when the closing FLAG is detected and the last data character
is loaded into RxDB or when an ABORT/GA character is received. REOM is cleared on
reading RDSRH, reset operation, or dropping of RxE.
10
RAB/GA
BOP
Received ABORT or GA character = 1 when the receiver senses an ABORT character if
SS/GA = 0 or a GA character if SS/GA = 1. RAB/GA is cleared on reading RDSRH, reset
operation, or dropping of RxE. A received abort does not set RxDA.
11
ROR
BOP/BCP
Receiver overrun = 1 indicates the processor has not read last character in the RxDB within
one character time + 1/2 RxC period after RxDA is asserted. Subsequent characters will be
lost. ROR is cleared on reading RDSRH, reset operation, or dropping of RxE.
12–14
ABC
BOP
Assembled bit count. Specifies the number of bits in the last received data character of a
message and should be examined by the processor when REOM = 1(RxDA and RxSA
asserted). ABC = 0 indicates the message was terminated (by a flag or GA) on a character
boundary as specified by PCR8–10. Otherwise, ABC = number of bits in the last data
character. ABC is cleared when RDSRH is read, reset operation, or dropping RxE. The
residual character is right justified inRDSRL.
15
RERR
BOP/BCP
Receiver error indicator should be examined by the processor when REOm = 1 in BOP, or
when the processor determines the last data character of the message in BCP with CRC or
when RxSA is set in BCP with VRC.
CRC–CCITT preset to 1’s/0’s as specified by PCSAR8–10:
RERR = 1 indicates FCS error (CRC ≠ F0B8 or ≠ 0)
RERR = 0 indicates FCS received correctly (CRC = F0B8 or = 0)
CRC–16 preset to 0’s on 8-bit characters specified by PSCAR8–10:
RERR = 1 indicates CRC–16 received correctly (CRC = 0).
RERR = 0 indicates CRC–16 error (CRC≠0)
VRC specified by PCSAR8–10:
RERR = 1 indicates VRC error
RERR = 0 indicates VRC is correct.
DC ELECTRICAL CHARACTERISTICS1, 2
PARAMETER
TEST CONDITIONS
Input voltage
VIL
Low
VIH
High
Output voltage
VOL
Low
VOH
High
ICC
Typ
Max
UNIT
0.8
V
0.4
V
2.0
IOL = 1.6mA
IOH = –100µA
2.4
VCC = 5.25V, TA = 0°C
150
mA
Leakage current
IIL
Input
IOL
Output
VIN = 0 to 5.25V
VOUT = 0 to 5.25V
10
10
µA
Capacitance
CIN
Input
COUT
Output
VIN = 0V, f = 1MHz
VOUT = 0V, f = 1MHz
20
20
pF
1995 May 01
Power supply current
LIMITS
Min
16
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
AC ELECTRICAL CHARACTERISTICS1, 2, 3
2MHz CLOCK
PARAMETER
Min
Set-up and hold time
tACS
Address/control set-up
tACH
Address/control hold
tDS
Data bus set-up (write)
tDH
Data bus hold (write)
tRXS
Receiver serial data set-up
tRxH
Receiver serial data hold
50
0
50
0
150
150
Pulse width
tRES
RESET
tDBEN
DBEN
250
250
Delay Time
tDD
Data bus (read)
tTxD
Transmit serial data
tDBEND DBEN to DBEN delay
tDF
Data bus float time (read)
f
Clock (RxC, TxC) frequency
tCLK1
tCLK2
tCLK0
Clock high (MM = 0)
Clock high (MM = 1)
Clock low
Typ
UNIT
Max
ns
ns
m4
170
250
ns
150
ns
2.0
MHz
200
165
240
240
ns
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified. See ordering code table for applicable temperature
range and operating supply range.
2. All voltage measurements are referenced to ground. All time measurements are at 0.8V or 2.0V. Input voltage levels for testing are 0.4V and
2.4V.
3. Output load CL = 100pF.
4. m = TxC low and applies to writing to TDSRH only.
TIMING DIAGRAMS
RESET
RESET AND WRITE DATA BUS
DBEN
tDBEN
A0, A2
tACS
tACH
CE, R/W,
BYTE
RESET
tRES
tACS
D0–D15
(READ)
FLOATING
tACH
NOT
VALID
tDD
VALID
FLOATING
tDF
D0–D15
(WRITE)
tDS
tDH
SD00065
Figure 10. Timing Diagrams
1995 May 01
17
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
TIMING DIAGRAMS (Continued)
CLOCK
1/f
TxC
tCLK1
tCLK0
TxSO
TxD
RxC
tCLK0
tRxS
tCLK1
tRxH
RxSI
SD00066
Figure 11. Timing Diagrams (cont.)
TRANSMIT – START OF MESSAGE
TxC
8 TxC1
SYNC/FLAG1
MARK
TxSO
1ST CHAR
3
TxBE
SET TSOM
LOAD 1st CHAR
RESET TSOM
LOAD 2nd CHAR
DBEN
TxE
2
TxA
NOTES:
1. SYNC may be 5 to 8 bits and will contain parity bit as specified.
2. TxA goes high relative to TxC rising edge after TSOM has been set and TxE has been raised.
3. TxBE goes low relative to DBEN falling edge on the first write transfer into TDSR. It is reasserted 1 TxC time before the first bit of the transmitted SYNC/FLAG. TxBE then goes
low relative to DBEN falling edge when writing into TDSRH and/or TDSRL. It is reasserted on the rising edge of the TxC that corresponds to the transmission of the last bit of each
character, except in BOP mode when the CRC is to be sent as the next character (see Transmit Timing–End of Message).
SD00067
Figure 12. Timing Diagrams (cont.)
1995 May 01
18
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
TIMING DIAGRAMS (Continued)
TRANSMIT – END OF BOP MESSAGE
TxC
TxSO
NEXT TO LAST CHAR
LAST CHAR
CRC
FLAG
MARK
TxBE1
LOAD LAST CHAR
SET TEOM
RESET TEOM
DBEN
TxE2
TxA3
NOTES:
1. TxBE goes low relative to the falling edge of DBEN corresponding to loading TDSRH/L. It goes high one TxC before character transmission begins and also when TxA has been
dropped.
2. TxE can be dropped before resetting TEOM if TxBE (corresponding to the closing FLAG) is high. Alternatively TxE can remain high and a new message initiated.
3. TxA goes low after TxE has been dropped and 1 1/2 TxC’s after the last bit of the closing FLAG has been transmitted.
SD00068
Figure 13. Timing Diagrams (cont.)
TRANSMIT TIMING – END OF BCP MESSAGE
TxC
TxSO
NEXT TO LAST CHAR
CRC1
LAST CHAR
MARK
TxBE
LOAD LAST CHAR
SET TEOM
RESET TEOM
DBEN
TxE
TxA
NOTE:
1. When SCN2652 generated CRC is not required. TEOM should only be set if SYNCs are to follow the message block. In that case, TxE should be dropped in response to TxBE
(which corresponds to the start of transmission of the last character). When CRC is required, TxE must be dropped before CRC transmission is complete. Otherwise, the contents
of TxDB will be shifted out on TxSO. This facilitates transmission of contiguous messages.
SD00069
Figure 14. Timing Diagrams (cont.)
1995 May 01
19
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
TIMING DIAGRAMS (Continued)
TRANSMIT UNDERRUN
TxC
TxU1
SET TSOM
DBEN2
NOTES:
1. TxU goes active relative to TxC falling edge if TxBE has not been serviced after n-1/2 TxC times (where n = transmit character length). TxU is reset on the TxC falling edge following assertion of the TSOM command.
2. An underrun will occur at the next character boundary if TEOM is reset and the transmitter remains enabled, unless the TSOM command is asserted or a character is loaded into
the TxDB.
SD00070
Figure 15. Timing Diagrams (cont.)
RECEIVE – START OF MESSAGE
RxC
1
RxA
RxDA2
1st CHAR READY
TO BE READ
2nd CHAR READY
TO BE READ
1st CHAR READ
2nd CHAR READ
DBEN
S/F3
RxE
NOTES:
1. RxA goes high relative to falling edge of RxC when RxE is high and: a. A data character following two SYNC’s is in RxDB (BCP mode). b. Character following FLAG is in RxDB
(BOP primary station mode). c. Character following FLAG is in RxDB and character matches the secondary station address or all parties address (BOP secondary station mode).
2. RxDA goes high on RxC falling edge when a character in RxDB is ready to be read. It comes up before RxSA and goes low on the falling edge of DBEN when RxDB is read.
3. S/F goes high relative to rising edge of RxC anytime a SYNC (BCP) or FLAG (BOP) is detected.
SD00071
Figure 16. Timing Diagrams (cont.)
1995 May 01
20
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
TIMING DIAGRAMS (Continued)
RECEIVE END OF MESSAGE
RxC
RxDA
RxSA1
READ
DATA
READ
STATUS
DBEN
(8-BIT)
S/F
RxE2
RxA3
NOTES:
1. At the end of a BOP message, RxSA goes high when FLAG detection (S/F 1) forces REOm to be set. Processor should read the last data character (RDSRL) and status (RDSRH)
which resets RxDA and RxSA respectively. For BCP end of message, RxSA may not be set and S/F = 0. The processor should read the last data character and status.
2. RxE must be dropped for BCP with non-contiguous messages. It may be left on at the end of a BOP message (see BOP Receive Operation).
3. RxA is reset relative to the falling edge of RxC after the closing FLAG of a BOP message (REOM = 1 and RxSA active.) or when RxE is dropped.
SD00072
Figure 17. Timing Diagrams (cont.)
TYPICAL APPLICATIONS
SCN2652 MPCC MICROPROCESSOR INTERFACE
RESET
TS BUFFER
RESET
TxC
STATUS
RxC
DB0–DB7
8-BIT
µP
CLOCK
LR
DATA BUS
LR
MPCC
SCN2652
ADDRESS CONTROL
A2–A0, R/W DBEN CE
TxSO
Φ
“1”
MODEM
CONTROL
LOGIC
RxSI
BYTE
RxE
TxE
DCD
CTS
LD
SYNCHRONOUS
MODEM
LR
RTS, CTS,
DTR, DSR,
DCD
NOTES:
1. Possible µP interrupt requests are: RxDA RxSA TxBE TxU
2. Other SCN2652 status signals and possible uses are S F line idle indicator, frame delimiter. RxA handshake on RxE, line turn around control. TxA handshake on TxE, line turn
around control.
3. Line drivers/receivers (LD/LR) convert EIA to TTL voltages and vice-versa.
4. RTS should be dropped after the CRC (BCP) or FLAG (BOP) has been transmitted. This forces CTS low and TxE low.
5. Corresponding high and low order bits of DB must be OR tied.
SD00073
Figure 18. Typical Applications
1995 May 01
21
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
TYPICAL APPLICATIONS (Continued)
DMA/PROCESSOR INTERFACE
DATA BUS
WORD COUNT
8 OR 16 BITS
DB15–DB00
RxDA
RxA
RDREQ
ADDRESS PTR
R/W CONTROL
TO PROCESSOR
WRREQ
TxBE
RxE
RxSA
TxA
PROCESSOR (P)
AND
SUPPORT LOGIC:
1. INITIALIZES
SCN2652
2. SETS/RESETS
TSOM, TEOM
3. RESPONDS
TO RxSA
TxE
SCN2652
DMA
CONTROLLER
TxU
S/F
A2–A0
BYTE
R/W
CE
DBEN
SCN2652
ADDRESS AND
CONTROL
ADDRESS
R/W CONTROLS
DATA BUS
DB15–DB00
RESET
RxDA
TxBE
R/W
MEMORY
MM
ADDRESS,
CE, R/W
ADDRESS, R/W,
CONTROL
RxC TxC RxSI TxSO
MODEM OR DCE
SYSTEM ADDRESS AND CONTROL BUS
For non-DMA operation TxBE and RxDA are set to the processor which then loads or reads data characters as required.
SD00074
Figure 19. Typical Applications (cont.)
CHANNEL INTERFACE
BAUD
RATE
GENERATOR
BAUD
RATE
GENERATOR
TxC
COMPUTER
OR
TERMINAL
LD
LR
LR
LD
RxC
TxC
MPCC
SCN2652
MPCC
SCN2652
TxSO
LD
LR
RxSI
RxSI
LR
LD
TxSO
RxC
COMPUTER
OR
TERMINAL
No Modem – DC Baseband Transmission
SD00075
Figure 20. Typical Applications (cont.)
1995 May 01
22
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68652
SCN2652/SCN2653 INTERFACE TYPICAL PROTOCOLS:
BISYNC, DDCMP, SDLC, HDLC
INTERRUPTS
TxBE, TxU, RxDA, RxSA
DB7–DB0
MPCC
SCN2652
TxD
A2
A1
A0
RxD
TxC
R/W
RxC
DBEN
CE
DB7–DB0
CPU
CE0
PGC
SCN2653
A1
R/W
A0
CE1
INT
(OPEN DRAIN)
5V
SD00076
Figure 21. Typical Applications (cont.)
1995 May 01
23
0.598 (15.19)
0.571 (14.50)
–E–
2. Dimension and tolerancing per ANSI Y14. 5M-1982.
3. “T”, “D”, and “E” are reference datums on the body
and include allowance for glass overrun and meniscus
on the seal line, and lid to base mismatch.
4. These dimensions measured with the leads
constrained to be perpendicular to plane T.
5. Pin numbers start with Pin #1 and continue
counterclockwise to Pin #40 when viewed
from the top.
6. Denotes window location for EPROM products.
PIN # 1
0.100 (2.54) BSC
2.087 (53.01)
2.038 (51.77)
–D–
24
0.620 (15.75)
0.590 (14.99)
(NOTE 4)
0.070 (1.78)
0.050 (1.27)
0.225 (5.72) MAX.
–T–
SEATING
PLANE
0.165 (4.19)
0.125 (3.18)
0.023 (0.58)
0.015 (0.38)
T
E D
0.175 (4.45)
0.145 (3.68)
0.055 (1.40)
0.020 (0.51)
0.010 (0.254)
0.695 (17.65)
0.600 (15.24)
Product specification
SCN2652/SCN68562
0.015 (0.38)
0.010 (0.25)
BSC
0.600 (15.24)
(NOTE 4)
Philips Semiconductors
NOTES:
1. Controlling dimension: Inches. Millimeters are
shown in parentheses.
0.098 (2.49)
0.040 (1.02)
40-PIN (600 mils wide) CERAMIC DUAL IN-LINE (F) PACKAGE (WITH WINDOW (FA) PACKAGE)
SEE NOTE 6
Multi-protocol communications controller (MPCC)
0590B
853–0590B 06688
1998 May 01
0.098 (2.49)
0.040 (1.02)
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
DIP40: plastic dual in-line package; 40 leads (600 mil)
1998 May 01
25
SCN2652/SCN68562
SOT129-1
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
PLCC44: plastic leaded chip carrier; 44 leads
1998 May 01
SCN2652/SCN68562
SOT187-2
26
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
NOTES
1998 May 01
27
SCN2652/SCN68562
Philips Semiconductors
Product specification
Multi-protocol communications controller (MPCC)
SCN2652/SCN68562
Data sheet status
Data sheet
status
Product
status
Definition [1]
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
 Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Document order number:
1998 May 01
28
Date of release: 08-98