INTEGRATED CIRCUITS 74LVT543 3.3V Octal latched transceiver with dual enable (3-State) Product specification Supersedes data of 1994 May 20 IC23 Data Handbook 1998 Feb 19 Philips Semiconductors Product specification 3.3V Octal latched transceiver with dual enable (3-State) FEATURES 74LVT543 DESCRIPTION • Combines 74LVT245 and 74LVT373 type functions in one device • 8-bit octal transceiver with D-type latch • Back-to-back registers for storage • Separate controls for data flow in each direction • Output capability: +64mA/–32mA • TTL input and output switching levels • Input and output interface capability to systems at 5V supply • Bus-hold data inputs eliminate the need for external pull-up The 74LVT543 is a high-performance BiCMOS product designed for VCC operation at 3.3V. This device contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate Latch Enable (LEAB, LEBA) and Output Enable (OEAB, OEBA) inputs are provided for each register to permit independent control of data transfer in either direction. The outputs are guaranteed to sink 64mA. FUNCTIONAL DESCRIPTION The 74LVT543 contains two sets of eight D–type latches, with separate control pins for each set. Using data flow from A to B as an example, when the A-to-B Enable (EAB) input and the A-to-B Latch Enable (LEAB) input are Low the A-to-B path is transparent. A subsequent Low-to-High transition of the LEAB signal puts the A data into the latches where it is stored and the B outputs no longer change with the A inputs. With EAB and OEAB both Low, the 3-State B output buffers are active and display the data present at the outputs of the A latches. resistors to hold unused inputs • Live insertion/extraction permitted • No bus current loading when output is tied to 5V bus • Power-up 3-State • Power-up reset • Latch-up protection exceeds 500mA per JEDEC Std 17 • ESD protection exceeds 2000V per MIL STD 883 Method 3015 Control of data flow from B to A is similar, but using the EBA, LEBA, and OEBA inputs. and 200V per Machine Model QUICK REFERENCE DATA SYMBOL CONDITIONS Tamb = 25°C; GND = 0V PARAMETER tPLH tPHL Propagation delay An to Bn or Bn to An CL = 50pF; VCC = 3.3V CIN Input capacitance VI = 0V or 3.0V CI/O I/O capacitance Outputs disabled; VI/O = 0V or 3.0V ICCZ Total supply current Outputs disabled; VCC = 3.6V TYPICAL UNIT 2.3 3.0 ns 4 pF 10 pF 0.13 mA ORDERING INFORMATION TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER 24-Pin Plastic SOL PACKAGES –40°C to +85°C 74LVT543 D 74LVT543 D SOT137-1 24-Pin Plastic SSOP Type II –40°C to +85°C 74LVT543 DB 74LVT543 DB SOT340-1 24-Pin Plastic TSSOP Type I –40°C to +85°C 74LVT543 PW 74LVT543PW DH SOT355-1 PIN CONFIGURATION LOGIC SYMBOL LEBA 1 24 VCC OEBA 2 23 EBA A0 3 22 B0 A1 4 21 B1 5 20 B2 A2 6 19 B3 A4 7 18 B4 A5 8 17 B5 9 16 B6 A3 A6 A7 10 3 14 LEAB GND 12 13 OEAB 5 6 7 8 9 10 A0 A1 A2 A3 A4 A5 A6 A7 11 EAB 23 EBA OEAB 13 14 LEAB OEBA 2 1 LEBA B0 B1 B2 B3 B4 B5 B6 B7 15 B7 EAB 11 4 22 21 20 19 18 17 16 15 SV00027 SV00026 1998 Feb 19 2 853-1749 18988 Philips Semiconductors Product specification 3.3V Octal latched transceiver with dual enable (3-State) LOGIC SYMBOL (IEEE/IEC) 74LVT543 LOGIC DIAGRAM DETAIL A D 2 1EN3 23 22 Q B0 LE G1 1 13 IC5 ZEN4 (AB) 11 A0 GZ. 14 3 Q ZC6 D LE 3 22 V3 5D 6D 2V 4 21 5 20 6 19 7 18 8 17 9 16 10 15 A1 A2 A3 A4 A5 A6 A7 OEBA 4 5 6 7 8 9 10 21 20 19 18 17 16 15 DETAIL A X 7 2 13 EBA LEBA B1 B2 B3 B4 B5 B6 B7 OEAB 23 11 1 14 SV00028 EAB LEAB SV00029 PIN DESCRIPTION PIN NUMBER SYMBOL 14, 1 LEAB / LEBA 11, 23 EAB / EBA FUNCTION A to B / B to A Latch Enable input (active-Low) A to B / B to A Enable input (active-Low) 13, 2 OEAB / OEBA 3, 4, 5, 6, 7, 8, 9, 10 A0 – A7 A to B / B to A Output Enable input (active-Low) Port A, 3-State outputs 22, 21, 20, 19, 18, 17, 16, 15 B0 – B7 Port B, 3-State outputs 12 GND Ground (0V) 24 VCC Positive supply voltage FUNCTION TABLE INPUTS OEXX OUTPUTS STATUS EXX LEXX An or Bn Bn or An H X X X Z Disabled X H X X Z Disabled L L ↑ ↑ L L h l Z Z Disabled + Latch L L L L ↑ ↑ h l H L Latch + Display L L L L L L H L H L Transparent L L H X H = High voltage level h = High voltage level one set-up time prior to the Low-to-High transition of LEXX or EXX (XX = AB or BA) L = Low voltage level l = Low voltage level one set-up time prior to the Low-to-High transition of LEXX or EXX (XX = AB or BA) 1998 Feb 19 X = ↑ = NC= Z = 3 NC Hold Don’t care Low-to-High transition of LEXX or EXX (XX = AB or BA) No change High impedance or “off” state Philips Semiconductors Product specification 3.3V Octal latched transceiver with dual enable (3-State) 74LVT543 ABSOLUTE MAXIMUM RATINGS1, 2 PARAMETER SYMBOL VCC IIK CONDITIONS RATING UNIT –0.5 to +4.6 V –50 mA –0.5 to +7.0 V VO < 0 –50 mA Output in Off or High state –0.5 to +7.0 V Output in Low state 128 Output in High state –64 DC supply voltage DC input diode current VI < 0 voltage3 VI DC input IOK DC output diode current voltage3 VOUT DC output IOUT O DC output current Tstg Storage temperature range mA –65 to 150 °C NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. 3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL VCC PARAMETER UNIT DC supply voltage MIN MAX 2.7 3.6 V 0 5.5 V VI Input voltage VIH High-level input voltage VIL Low-level input voltage 0.8 V IOH High-level output current –32 mA Low-level output current 32 Low-level output current; current duty cycle ≤ 50%; f ≥ 1kHz 64 ∆t/∆v Input transition rise or fall rate; outputs enabled 10 ns/V Tamb Operating free-air temperature range +85 °C IOL O 1998 Feb 19 2.0 mA –40 4 V Philips Semiconductors Product specification 3.3V Octal latched transceiver with dual enable (3-State) 74LVT543 DC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C MIN VIK Input clamp voltage VCC = 2.7V; IIK = –18mA VCC = 2.7 to 3.6V; IOH = –100µA VOH VOL VRST High-level output voltage Low-level output voltage Power-up output low voltage5 2.4 2.5 VCC = 3.0V; IOH = –32mA 2.0 2.2 0.1 0.2 VCC = 2.7V; IOL = 24mA 0.3 0.5 VCC = 3.0V; IOL = 16mA 0.25 0.4 VCC = 3.0V; IOL = 32mA 0.3 0.5 VCC = 3.0V; IOL = 64mA 0.4 0.55 VCC = 3.6V; IO = 1mA; VI = GND or VCC 0.13 0.55 ±0.1 ±1 1 10 1 20 0.1 1 –1 -5 1 ±100 Control pins VCC = 3.6V; VI = 5.5V I/O Data pins4 VCC = 0V; VI or VO = 0 to 4.5V VCC = 3V; VI = 0.8V IHOLD IEX IPU/PD Bus Hold current A inputs6 VCC = 3V; VI = 2.0V –75 –150 VCC = 0V to 3.6V; VCC = 3.6V ±500 V V µA µA µA VO = 5.5V; VCC = 3.0V 60 125 µA Power up/down 3-State output current3 VCC ≤ 1.2V; VO = 0.5V to VCC; VI = GND or VCC; OE/OE = Don’t care 15 ±100 µA VCC = 3.6V; Outputs High, VI = GND or VCC, IO = 0 0.13 0.19 VCC = 3.6V; Outputs Low, VI = GND or VCC, IO = 0 3 12 VCC = 3.6V; Outputs Disabled; VI = GND or VCC, IO = 0 0.13 0.19 VCC = 3V to 3.6V; One input at VCC -0.6V, Other inputs at VCC or GND 0.1 0.2 Quiescent supply current ICCZ ∆ICC 150 V Current into an output in the High state when VO > VCC ICCH ICCL 75 UNIT V VCC = 2.7V; IOL = 100µA VCC = 3.6V; VI = 0 Output off current –1.2 VCC = 2.7V; IOH = –8mA VCC = 3.6V; VI = VCC IOFF –0.9 VCC-0.1 VCC = 0 or 3.6V; VI = 5.5V Input leakage current MAX VCC-0.2 VCC = 3.6V; VI = VCC or GND II TYP1 Additional supply current per input pin2 mA mA NOTES: 1. All typical values are at VCC = 3.3V and Tamb = 25°C. 2. This is the increase in supply current for each input at the specified voltage level other than VCC or GND 3. This parameter is valid for any VCC between 0V and 1.2V with a transition time of up to 10msec. From VCC = 1.2V to VCC = 3.3V ± 0.3V a transition time of 100µsec is permitted. This parameter is valid for Tamb = 25°C only. 4. Unused pins at VCC or GND. 5. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. 6. This is the bus hold overdrive current required to force the input to the opposite logic state. 1998 Feb 19 5 Philips Semiconductors Product specification 3.3V Octal latched transceiver with dual enable (3-State) 74LVT543 AC CHARACTERISTICS GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω; Tamb = –40°C to +85°C. LIMITS SYMBOL PARAMETER VCC = 3.3V ±0.3V WAVEFORM VCC = 2.7V UNIT MIN TYP1 MAX MAX 2.3 3.0 4.7 4.6 5.5 5.8 ns tPLH tPHL Propagation delay An to Bn, Bn to An 2 1.0 1.0 tPLH tPHL Propagation delay LEBA to An, LEAB to Bn 1 2 1.0 1.0 3.6 4.2 5.9 5.7 7.3 7.3 ns tPZH tPZL Output enable time OEBA to An, OEAB to Bn 4 5 1.0 1.1 3.8 3.8 5.8 6.4 7.6 8.2 ns tPHZ tPLZ Output disable time OEBA to An, OEAB to Bn 4 5 2.4 2.0 3.7 3.5 6.5 5.8 7.1 5.9 ns tPZH tPZL Output enable time EBA to An, EAB to Bn 4 5 1.0 1.4 4.0 4.1 6.0 6.7 7.6 8.3 ns 4 5 2.3 2.0 3.7 3.5 6.4 5.4 7.1 5.6 ns tPHZ Output disable time tPLZ EBA to An, EAB to Bn NOTE: 1. All typical values are at VCC = 3.3V and Tamb = 25°C. AC SETUP REQUIREMENTS GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω; Tamb = –40°C to +85°C. LIMITS SYMBOL PARAMETER VCC = 3.3V ±0.3V WAVEFORM MIN VCC = 2.7V MAX UNIT MIN ts(H) ts(L) Setup time An to LEAB, Bn to LEBA 3 0 0.8 0 1.1 ns th(H) th(L) Hold time An to LEAB, Bn to LEBA 3 1.7 1.7 1.7 1.7 ns ts(H) ts(L) Setup time An to EAB, Bn to EBA 3 0 0.9 0 1.2 ns th(H) th(L) Hold time An to EAB, Bn to EBA 3 1.8 1.8 1.8 1.8 ns tw(L) Latch enable pulse width, Low 3 3.3 3.3 ns AC WAVEFORMS VM = 1.5V, VIN = GND to 2.7V 2.7V 2.7V VIN 1.5V VIN 1.5V 1.5V 1.5V 0V 0V tPHL VOUT tPLH 1.5V tPLH VOH VOUT 1.5V 1.5V VOH 1.5V VOL VOL SV00030 SV00113 Waveform 2. Propagation Delay For Non-Inverting Output Waveform 1. Propagation Delay For Inverting Output 1998 Feb 19 tPHL 6 Philips Semiconductors Product specification 3.3V Octal latched transceiver with dual enable (3-State) ÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉÉÉÉÉ ÉÉÉ 74LVT543 2.7V 2.7V An, Bn 1.5V 1.5V 1.5V 0V ts(H) ts(L) th(H) 1.5V OEAB, OEBA, EAB, EBA 1.5V 1.5V 0V tPZL th(L) tPLZ 3.0V 2.7V LEAB, LEBA, EAB, EBA tw(L) 1.5V 1.5V An, Bn 1.5V VOL+0.3V VOL 0V NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. SV00116 Waveform 5. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level SV00114 Waveform 3. Data Setup and Hold Times And Latch Enable Pulse Width 2.7V OEAB, OEBA, EAB, EBA 1.5V 1.5V 0V tPZH tPHZ VOH An, Bn VOH–0.3V 1.5V 0V SV00115 Waveform 4. 3-State Output Enable Time to High Level and Output Disable Time from High Level TEST CIRCUIT AND WAVEFORM 6.0V VCC Open VIN VOUT PULSE GENERATOR RL GND tW 90% NEGATIVE PULSE 90% VM VM 10% 10% D.U.T. RT 0V CL tTHL (tF) RL tTLH (tR) tTLH (tR) tTHL (tF) 90% Test Circuit for 3-State Outputs POSITIVE PULSE AMP (V) 90% VM VM 10% 10% tW SWITCH POSITION TEST SWITCH tPLH/tPHL Open tPLZ/tPZL 6V tPHZ/tPZH GND AMP (V) 0V VM = 1.5V Input Pulse Definition INPUT PULSE REQUIREMENTS DEFINITIONS FAMILY RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. 74LVT Amplitude Rep. Rate 2.7V 10MHz tW tR tF 500ns 2.5ns 2.5ns RT = Termination resistance should be equal to ZOUT of pulse generators. SV00092 1998 Feb 19 7 Philips Semiconductors Product specification 3.3V Octal latched transceiver with dual enable (3-State) SO24: plastic small outline package; 24 leads; body width 7.5 mm 1998 Feb 19 8 74LVT543 SOT137-1 Philips Semiconductors Product specification 3.3V Octal latched transceiver with dual enable (3-State) SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm 1998 Feb 19 9 74LVT543 SOT340-1 Philips Semiconductors Product specification 3.3V Octal latched transceiver with dual enable (3-State) TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm 1998 Feb 19 10 74LVT543 SOT355-1 Philips Semiconductors Product specification 3.3V Octal latched transceiver with dual enable (3-State) NOTES 1998 Feb 19 11 74LVT543 Philips Semiconductors Product specification 3.3V Octal latched transceiver with dual enable (3-State) 74LVT543 Data sheet status Data sheet status Product status Definition [1] Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 print code Document order number: yyyy mmm dd 12 Date of release: 05-96 9397-750-03537