INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4000B gates Dual 3-input NOR gate and inverter Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification HEF4000B gates Dual 3-input NOR gate and inverter DESCRIPTION The HEF4000B provides the positive dual 3-input NOR function. A single stage inverting function with standard output performance is also accomplished. The outputs are fully buffered for highest noise immunity and pattern insensitivity of output impedance. Fig.2 Pinning diagram. HEF4000BP(N): 14-lead DIL; plastic (SOT27-1) HEF4000BD(F): 14-lead DIL; ceramic (cerdip) HEF4000BT(D): 14-lead SO; plastic (SOT73) (SOT108-1) ( ): Package Designator North America Fig.1 Functional diagram. FAMILY DATA, IDD LIMITS category GATES See Family Specifications Fig.3 Logic diagram. January 1995 2 Philips Semiconductors Product specification HEF4000B gates Dual 3-input NOR gate and inverter DC CHARACTERISTICS For the single inverter stage (I7/O3): see Family Specifications for input voltages HIGH and LOW (unbuffered stages only). AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V Propagation delays 5 I1 to I6 → O1,O2 10 SYMBOL tPHL; tPLH 15 5 I7 → O3 10 (unbuffered output) 15 Output transition times HIGH to LOW LOW to HIGH Dynamic power dissipation per package (P) tPHL; tPLH 5 TYP. MAX. TYPICAL EXTRAPOLATION FORMULA 70 140 ns 43 ns + (0,55 ns/pF) CL 35 70 ns 24 ns + (0,23 ns/pF) CL 30 55 ns 22 ns + (0,16 ns/pF) CL 45 90 ns 18 ns + (0,55 ns/pF) CL 25 50 ns 14 ns + (0,23 ns/pF) CL 20 40 ns 12 ns + (0,16 ns/pF) CL 10 ns + (1,0 ns/pF) CL 60 120 ns 30 60 ns 9 ns + (0,42 ns/pF) CL 15 20 40 ns 6 ns + (0,28 ns/pF) CL 5 60 120 ns 10 tTHL 10 ns + (1,0 ns/pF) CL 30 60 ns 9 ns + (0,42 ns/pF) CL 15 20 40 ns 6 ns + (0,28 ns/pF) CL VDD V TYPICAL FORMULA FOR P (µW) 10 tTLH 5 1 000 fi + ∑ (foCL) × VDD2 where 10 7 700 fi + ∑ (foCL) × VDD 2 fi = input freq. (MHz) 15 28 700 fi + ∑ (foCL) × VDD 2 fo = output freq. (MHz) CL = load capacitance (pF) ∑ (foCL) = sum of outputs VDD = supply voltage (V) January 1995 3 Philips Semiconductors Product specification HEF4000B gates Dual 3-input NOR gate and inverter APPLICATION INFORMATION The following information (Figs 4 to 7) is only for the single inverter stage (I7/O3). Fig.4 Fig.5 Voltage gain (VO/VI) as a function of supply voltage. Supply current as a function of supply voltage. This is also an example of an analogue amplifier using the single inverter stage (I7/O3) of the HEF4000B. Fig.6 Test set-up for measuring graphs of Figs 4 and 5. January 1995 4 Philips Semiconductors Product specification HEF4000B gates Dual 3-input NOR gate and inverter Fig.7 Test set-up for measuring forward transconductance gfs = dio/dvi at vo is constant (see also graph Fig.8). A: average B: average + 2 s, C: average − 2 s, in where ‘s’ is the observed standard deviation. Fig.8 Typical forward transconductance gfs as a function of the supply voltage at Tamb = 25 °C. January 1995 5