INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4086B gates 4-wide 2-input AND-OR-invert gate Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification HEF4086B gates 4-wide 2-input AND-OR-invert gate DESCRIPTION The HEF4086B is a 4-wide 2-input AND-OR-invert (AOI) gate with two additional inputs (I8 or I9) which can be used as either expander or inhibit inputs by connecting them to any standard LOCMOS output. A HIGH on I8 or a LOW on I9 forces the output (O) LOW independent of the other eight inputs (I0 to I7). The output (O) is fully buffered for highest noise immunity and pattern insensitivity of output impedance. Fig.2 Pinning diagram. HEF4086BP(N): 14-lead DIL; plastic (SOT27-1) HEF4086BD(F): 14-lead DIL; ceramic (cerdip) (SOT73) HEF4086BT(D): 14-lead SO; plastic (SOT108-1) ( ): Package Designator North America Fig.1 Functional diagram. PINNING I0 to I8 gate inputs I9 gate input (active LOW) O output (active LOW) FAMILY DATA, IDD LIMITS category GATES See Family Specifications January 1995 2 Philips Semiconductors Product specification HEF4086B gates 4-wide 2-input AND-OR-invert gate Fig.3 Logic diagram. LOGIC EQUATION O = I0 ⋅ I1 + I2 ⋅ I3 + I4 ⋅ I5 + I6 ⋅ I7 + I8 + I9 January 1995 3 Philips Semiconductors Product specification HEF4086B gates 4-wide 2-input AND-OR-invert gate AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V SYMBOL TYP. TYPICAL EXTRAPOLATION FORMULA MAX. Propagation delays I0 to I7 → O HIGH to LOW 5 10 tPHL 15 5 LOW to HIGH 10 tPLH 15 I8 → O HIGH to LOW 5 10 tPHL 15 5 LOW to HIGH 10 tPLH 15 I9 → O HIGH to LOW LOW to HIGH Output transition times HIGH to LOW LOW to HIGH dissipation per package (P) 180 ns 63 ns + (0,55 ns/pF) CL 65 ns 19 ns + (0,23 ns/pF) CL 20 40 ns 12 ns + (0,16 ns/pF) CL 80 155 ns 53 ns + (0,55 ns/pF) CL 30 60 ns 19 ns + (0,23 ns/pF) CL 20 40 ns 12 ns + (0,16 ns/pF) CL 70 140 ns 43 ns + (0,55 ns/pF) CL 25 55 ns 14 ns + (0,23 ns/pF) CL 20 40 ns 12 ns + (0,16 ns/pF) CL 55 115 ns 28 ns + (0,55 ns/pF) CL 20 40 ns 9 ns + (0,23 ns/pF) CL 15 25 ns 7 ns + (0,16 ns/pF) CL 55 105 ns 28 ns + (0,55 ns/pF) CL 20 45 ns 9 ns + (0,23 ns/pF) CL 15 15 30 ns 7 ns + (0,16 ns/pF) CL 5 45 90 ns 18 ns + (0,55 ns/pF) CL 5 10 tPHL 15 35 ns 4 ns + (0,23 ns/pF) CL 15 10 25 ns 2 ns + (0,16 ns/pF) CL 5 60 120 ns 10 tPLH 10 ns + (1,0 ns/pF) CL 30 60 ns 9 ns + (0,42 ns/pF) CL 15 20 40 ns 6 ns + (0,28 ns/pF) CL 5 60 120 ns 30 60 ns 9 ns + (0,42 ns/pF) CL 20 40 ns 6 ns + (0,28 ns/pF) CL 10 10 15 Dynamic power 90 30 tTHL tTLH VDD V TYPICAL FORMULA FOR P (µW) 5 525 fi + ∑ (foCL) × VDD2 10 2600 fi + ∑ (foCL) × VDD 2 15 7300 fi + ∑ (foCL) × VDD 2 10 ns + (1,0 ns/pF) CL where fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) ∑ (foCL) = sum of outputs VDD = supply voltage (V) January 1995 4 Philips Semiconductors Product specification HEF4086B gates 4-wide 2-input AND-OR-invert gate APPLICATION INFORMATION Figure 4 shows two HEF4086B ICs connected to obtain an 8-wide 2-input AOI function. The output (OA) of the first IC is fed directly into the I9B gate input of the second IC. Similarly, any NAND gate output can be fed directly into the I9 gate input to obtain a 5-wide AOI function. In addition, any AND gate output can be fed directly into the I8 gate input with the same result. Fig.4 Two HEF4086B ICs connected as an 8-wide 2-input AOI gate. Logic equation for Fig.4: O B = I 0A ⋅ I 1A + I 2A ⋅ I 3A + I 4A ⋅ I 5A + I 6A ⋅ I 7A + I 0B ⋅ I 1B + I 2B ⋅ I 3B + I 4B ⋅ I 5B + I 6B ⋅ I 7B January 1995 5