CBT3126 Quad FET bus switch Rev. 03 — 9 December 2008 Product data sheet 1. General description The CBT3126 is a quad FET bus switch with independent line switches. Each switch is disabled when the associated Output Enable (OE) input is LOW. The CBT3126 is characterized for operation from −40 °C to +85 °C. 2. Features n n n n n n n Standard ’126-type pinout Multiple package options 5 Ω switch connection between two ports TTL-compatible input levels Minimal propagation delay through the switch Latch-up protection exceeds 500 mA per JEDEC standard JESD78 class II level A ESD protection: u HBM JESD22-A114E exceeds 2000 V u MM JESD22-A115-A exceeds 200 V u CDM JESD22-C101C exceeds 1000 V n Specified from −40 °C to +85 °C 3. Ordering information Table 1. Ordering information Type number Temperature range Package Name Description Version CBT3126D −40 °C to +85 °C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 CBT3126DB −40 °C to +85 °C SSOP14 plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 CBT3126PW −40 °C to +85 °C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 CBT3126DS −40 °C to +85 °C SSOP16[1] plastic shrink small outline package; 16 leads; body width 3.9 mm; lead pitch 0.635 mm SOT519-1 [1] Also known as QSOP16. CBT3126 NXP Semiconductors Quad FET bus switch 4. Functional diagram 1A 1OE 1A 1OE 1B 2A 2OE 2A 2B 2OE 3OE 3A 3A 3B 3OE 4OE 4A 4A 4B 4OE 2 3 1B 1 5 6 2B 4 9 8 3B 10 12 11 4B 13 001aaj023 001aaj024 Pin numbers are for the 14 pin packages. Fig 1. Logic symbol Fig 2. Logic diagram 5. Pinning information 5.1 Pinning CBT3126 1OE 14 VCC 1 1A 2 13 4OE 1B 3 12 4A 2OE 4 11 4B 2A 5 10 3OE 2B 6 GND 7 9 8 3A 3B CBT3126 CBT3126 Pin configuration SOT108-1 (SO14) 1 16 VCC 2 15 4OE 1A 3 14 4A 1A 2 1B 3 12 4A 1B 4 13 4B 2OE 4 11 4B 2OE 5 12 3OE 2A 5 10 3OE 2A 6 11 3A 2B 6 9 3A 2B 7 10 3B GND 7 8 3B GND 8 001aaj025 001aaj111 Fig 3. n.c. 1OE 14 VCC 13 4OE 1OE 1 Fig 4. Pin configuration SOT337-1 (SSOP14) and SOT402-1 (TSSOP14) 9 n.c. 001aaj026 Fig 5. Pin configuration SOT519-1 (SSOP16) 5.2 Pin description Table 2. Pin description Symbol Pin Description SOT108-1 SOT337-1 and SOT402-1 SOT519-1 1OE to 4OE 1, 4, 10, 13 2, 5, 12, 15 output enable input 1A to 4A, 2, 5, 9, 12 3, 6, 11, 14 A input/output 1B to 4B 3, 6, 8, 11 4, 7, 10, 13 B output/input CBT3126_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 9 December 2008 2 of 13 CBT3126 NXP Semiconductors Quad FET bus switch Table 2. Symbol Pin description …continued Pin Description SOT108-1 SOT337-1 and SOT402-1 SOT519-1 GND 7 8 ground (0 V) VCC 14 16 positive supply voltage n.c. - 1, 9 not connected 6. Functional description Table 3. Function selection H = HIGH voltage level; L = LOW voltage level. Inputs Switch nOE L nA to nB disconnected H nA to nB connected 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions supply voltage VCC VI input voltage [1] Min Max Unit −0.5 +7.0 V −0.5 +7.0 V ICC supply current continuous current through each VCC or GND pin - 128 mA IIK input clamping current VI < 0 V −50 - mA Tstg storage temperature −65 +150 °C total power dissipation Ptot Tamb = −40 °C to +125 °C [2] SO14 package [3] - 500 mW SSOP14 and SSOP16 package [4] - 500 mW TSSOP14 package [4] - 500 mW [1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. [2] The package thermal impedance is calculated from JESD51-7. [3] For SO14 package; Ptot derates linearly with 8 mW/K above 70 °C. [4] For SSOP14, SSOP16 and TSSOP14 packages; Ptot derates linearly with 5.5 mW/K above 70 °C. 8. Recommended operating conditions Table 5. Operating conditions All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Symbol Parameter VCC Conditions Min Max Unit supply voltage 4.5 5.5 V VIH HIGH-level input voltage 2.0 - V VIL LOW-level input voltage - 0.8 V Tamb ambient temperature −40 +85 °C operating in free-air CBT3126_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 9 December 2008 3 of 13 CBT3126 NXP Semiconductors Quad FET bus switch 9. Static characteristics Table 6. Static characteristics Tamb = −40 °C to +85 °C. Symbol Parameter Conditions Min Typ[1] Max Unit VIK input clamping voltage VCC = 4.5 V; II = −18 mA - - −1.2 V Vpass pass voltage VI = VCC = 5.0 V; IO = −100 µA - 3.8 - V II input leakage current VCC = 5.5 V; VI = GND or 5.5 V - - ±1 µA ICC supply current VCC = 5.5 V; IO = 0 mA; VI = VCC or GND - - 3 µA ∆ICC additional supply current control pins; per input; VCC = 5.5 V; one input at 3.4 V, other inputs at VCC or GND - - 2.5 mA CI input capacitance control pins; VI = 3 V or 0 V - 1.7 - pF Cio(off) off-state input/output capacitance VO = 3 V or 0 V; OE = VCC - 3.4 - pF RON ON resistance VCC = 4.0 V - 16 22 Ω VI = 0 V; II = 64 mA - 5 7 Ω VI = 0 V; II = 30 mA - 5 7 Ω VI = 2.4 V; II = 15 mA - 10 15 Ω VI = 2.4 V; II = 15 mA [2] [3] VCC = 4.5 V [1] All typical values are measured at VCC = 5 V; Tamb = 25 °C. [2] This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. [3] Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. ON resistance is determined by the lowest voltage of the two (A or B) terminals. 10. Dynamic characteristics Table 7. Dynamic characteristics Tamb = −40 °C to +85 °C; VCC = 4.5 V to 5.5 V; for test circuit see Figure 8. Symbol Parameter propagation delay tpd enable time ten disable time tdis Conditions nA to nB or nB to nA; see Figure 6 [1][2] Min Max Unit - 0.25 ns OE to nA or nB; see Figure 7 [2] 1.6 4.5 ns OE to nA or nB; see Figure 7 [2] 1.0 5.4 ns [1] This parameter is warranted but not production tested. The propagation delay is based on the RC time constant of the typical ON resistance of the switch and a load capacitance, when driven by an ideal voltage source (zero output impedance). [2] tPLH and tPHL are the same as tpd; tPZL and tPZH are the same as ten; tPLZ and tPHZ are the same as tdis. CBT3126_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 9 December 2008 4 of 13 CBT3126 NXP Semiconductors Quad FET bus switch 11. AC waveforms VI input VM VM 0V tPHL tPLH VOH VM output VM VOL 001aai367 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 6. The input (nA, nB) to output (nB, nA) propagation delay times VI nOE input VM GND tPLZ tPZL VCC output LOW-to-OFF OFF-to-LOW VM VX VOL tPHZ VOH tPZH VY output HIGH-to-OFF OFF-to-HIGH VM GND switch enabled switch disabled switch enabled 001aaj027 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 7. Table 8. Enable and disable times Measurement points Input Output VM VM VX VY 1.5 V 1.5 V VOL + 0.3 V VOH − 0.3 V CBT3126_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 9 December 2008 5 of 13 CBT3126 NXP Semiconductors Quad FET bus switch 12. Test information VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VEXT VCC VI RL VO G DUT RT CL RL 001aae331 Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 8. Table 9. Test circuit for measuring switching times Test data Supply voltage Input Load VEXT VCC VI tr, tf CL RL tPLH, tPHL tPLZ, tPZL tPHZ, tPZH 4.5 V to 5.5 V GND to 3.0 V ≤ 2.5 ns 50 pF 500 Ω open 7.0 V open CBT3126_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 9 December 2008 6 of 13 CBT3126 NXP Semiconductors Quad FET bus switch 13. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.010 0.057 inches 0.069 0.004 0.049 0.05 0.244 0.039 0.041 0.228 0.016 0.028 0.024 0.01 0.01 0.028 0.004 0.012 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. Fig 9. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Package outline SOT108-1 (SO14) CBT3126_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 9 December 2008 7 of 13 CBT3126 NXP Semiconductors Quad FET bus switch SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm D SOT337-1 E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp L 7 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.4 0.9 8 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT337-1 REFERENCES IEC JEDEC JEITA MO-150 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 10. Package outline SOT337-1 (SSOP14) CBT3126_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 9 December 2008 8 of 13 CBT3126 NXP Semiconductors Quad FET bus switch TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig 11. Package outline SOT402-1 (TSSOP14) CBT3126_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 9 December 2008 9 of 13 CBT3126 NXP Semiconductors Quad FET bus switch SSOP16: plastic shrink small outline package; 16 leads; body width 3.9 mm; lead pitch 0.635 mm D E SOT519-1 A X c y HE v M A Z 9 16 A2 A (A 3) A1 θ Lp L 8 1 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp v w y Z (1) θ mm 1.73 0.25 0.10 1.55 1.40 0.25 0.31 0.20 0.25 0.18 5.0 4.8 4.0 3.8 0.635 6.2 5.8 1 0.89 0.41 0.2 0.18 0.09 0.18 0.05 8o o 0 Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-05-04 03-02-18 SOT519-1 Fig 12. Package outline SOT519-1 (SSOP16) CBT3126_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 9 December 2008 10 of 13 CBT3126 NXP Semiconductors Quad FET bus switch 14. Abbreviations Table 10. Abbreviations Acronym Description CDM Charged Device Model ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 15. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes CBT3126_3 20081209 Product data sheet - CBT3126_2 Modifications: • • • • Section 5 “Pinning information” SOT108-1 pin configuration drawing added. • Section 13 “Package outline” SOT108-1, SOT337-1and SOT402-1 package outline drawings added. Section 5 “Pinning information” SOT337-4 number changed to SOT337-1 Section 9 “Static characteristics” in Cio(off) conditions OE changed to OE Section 13 “Package outline” SOT109-1, SOT338-1, SOT403-1and SOT763-1 package outline drawings removed. CBT3126_2 20081023 Product data sheet - CBT3126_1 CBT3126_1 20011212 Product data sheet - - CBT3126_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 9 December 2008 11 of 13 CBT3126 NXP Semiconductors Quad FET bus switch 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 16.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] CBT3126_3 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 9 December 2008 12 of 13 CBT3126 NXP Semiconductors Quad FET bus switch 18. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Recommended operating conditions. . . . . . . . 3 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Dynamic characteristics . . . . . . . . . . . . . . . . . . 4 AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Test information . . . . . . . . . . . . . . . . . . . . . . . . . 6 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 7 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 11 Legal information. . . . . . . . . . . . . . . . . . . . . . . 12 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Contact information. . . . . . . . . . . . . . . . . . . . . 12 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 9 December 2008 Document identifier: CBT3126_3