PHILIPS SC16C650BIN40

SC16C650B
5 V, 3.3 V and 2.5 V UART with 32-byte FIFOs
and infrared (IrDA) encoder/decoder
Rev. 03 — 10 December 2004
Product data
1. General description
The SC16C650B is a Universal Asynchronous Receiver and Transmitter (UART)
used for serial data communications. Its principal function is to convert parallel data
into serial data, and vice versa. The UART can handle serial data rates up to 3 Mbit/s.
The SC16C650B is pin compatible with the ST16C650A and it will power-up to be
functionally equivalent to the 16C450. Programming of control registers enables the
added features of the SC16C650B. Some of these added features are the 32-byte
receive and transmit FIFOs, automatic hardware or software flow control and infrared
encoding/decoding. The selectable auto-flow control feature significantly reduces
software overload and increases system efficiency while in FIFO mode by
automatically controlling serial data flow using RTS output and CTS input signals.
The SC16C650B also provides DMA mode data transfers through FIFO trigger levels
and the RXRDY and TXRDY signals. On-board status registers provide the user with
error indications, operational status, and modem interface control. System interrupts
may be tailored to meet user requirements. An internal loop-back capability allows
on-board diagnostics.
The SC16C650B operates at 5 V, 3.3 V and 2.5 V, and the industrial temperature
range, and is available in plastic DIP40, PLCC44, LQFP48, and HVQFN32 packages.
2. Features
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Single channel
5 V, 3.3 V and 2.5 V operation
5 V tolerant inputs
Industrial temperature range (−40 °C to +85 °C)
After reset, all registers are identical to the typical 16C450 register set
Capable of running with all existing generic 16C450 software
Pin compatibility with the industry-standard ST16C450/550, TL16C450/550,
PC16C450/550. Software compatible with ST16C650.
Up to 3 Mbit/s transmit/receive operation at 5 V, 2 Mbit/s at 3.3 V, and 1 Mbit/s at
2.5 V
32 byte transmit FIFO
32 byte receive FIFO with error flags
Programmable auto-RTS and auto-CTS
◆ In auto-CTS mode, CTS controls transmitter
◆ In auto-RTS mode, RxFIFO contents and threshold control RTS
Automatic software/hardware flow control
Programmable Xon/Xoff characters
SC16C650B
Philips Semiconductors
UART with 32-byte FIFOs and IrDA encoder/decoder
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■
■
■
■
■
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■
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Software selectable Baud Rate Generator
Supports IrDA version 1.0 (up to 115.2 kbit/s)
Four selectable Receive and Transmit FIFO interrupt trigger levels
Standard modem interface or infrared IrDA encoder/decoder interface
Sleep mode
Standard asynchronous error and framing bits (Start, Stop, and Parity Overrun
Break)
Independent receiver clock input
Transmit, Receive, Line Status, and Data Set interrupts independently controlled
Fully programmable character formatting:
◆ 5, 6, 7, or 8-bit characters
◆ Even, Odd, or No-Parity formats
◆ 1, 11⁄2, or 2-stop bit
◆ Baud generation (DC to 3 Mbit/s)
False start-bit detection
Complete status reporting capabilities
3-State output TTL drive capabilities for bi-directional data bus and control bus
Line Break generation and detection
Internal diagnostic capabilities:
◆ Loop-back controls for communications link fault isolation
Prioritized interrupt system controls
Modem control functions (CTS, RTS, DSR, DTR, RI, DCD).
3. Ordering information
Table 1:
Ordering information
Industrial: VCC = 2.5 V, 3.3 V or 5 V ± 10%; Tamb = −40 °C to +85 °C.
Type number
Package
Name
Description
Version
SC16C650BIA44
PLCC44
plastic leaded chip carrier; 44 leads
SOT187-2
SC16C650BIB48
LQFP48
plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm
SOT313-2
SC16C650BIBS
HVQFN32
plastic thermal enhanced very thin quad flat package; no leads;
32 terminals; body 5 × 5 × 0.85 mm
SOT617-1
SC16C650BIN40
DIP40
plastic dual in-line package; 40 leads (600 mil)
SOT129-1
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14451
Product data
Rev. 03 — 10 December 2004
2 of 51
SC16C650B
Philips Semiconductors
UART with 32-byte FIFOs and IrDA encoder/decoder
4. Block diagram
SC16C650B
TRANSMIT
FIFO
REGISTERS
D0–D7
IOR, IOR
IOW, IOW
RESET
TX
DATA BUS
AND
CONTROL LOGIC
REGISTER
SELECT
LOGIC
INTERCONNECT BUS LINES
AND
CONTROL SIGNALS
FLOW
CONTROL
LOGIC
A0–A2
CS0, CS1, CS2
AS
TRANSMIT
SHIFT
REGISTER
RECEIVE
FIFO
REGISTERS
FLOW
CONTROL
LOGIC
IR
ENCODER
RECEIVE
SHIFT
REGISTER
RX
IR
DECODER
DDIS
DTR
RTS
OUT1, OUT2
MODEM
CONTROL
LOGIC
INT
TXRDY
RXRDY
INTERRUPT
CONTROL
LOGIC
CTS
RI
DCD
DSR
CLOCK AND
BAUD RATE
GENERATOR
002aaa602
XTAL1
RCLK
XTAL2
BAUDOUT
Fig 1. Block diagram.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14451
Product data
Rev. 03 — 10 December 2004
3 of 51
SC16C650B
Philips Semiconductors
UART with 32-byte FIFOs and IrDA encoder/decoder
5. Pinning information
40 CTS
41 DSR
42 DCD
43 RI
44 VCC
1 n.c.
2 D0
3 D1
4 D2
5 D3
6 D4
5.1 Pinning
D5
7
39 RESET
D6
8
38 OUT1
D7
9
37 DTR
RCLK 10
36 RTS
RX 11
35 OUT2
SC16C650BIA44
n.c. 12
34 n.c.
TX 13
33 INT
AS 28
TXRDY 27
DDIS 26
IOR 25
29 A2
IOR 24
BAUDOUT 17
n.c. 23
30 A1
GND 22
CS2 16
IOW 21
31 A0
IOW 20
CS1 15
XTAL2 19
32 RXRDY
XTAL1 18
CS0 14
002aaa603
Fig 2. PLCC44 pin configuration.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14451
Product data
Rev. 03 — 10 December 2004
4 of 51
SC16C650B
Philips Semiconductors
37 n.c.
38 CTS
39 DSR
40 DCD
41 RI
42 VCC
43 D0
44 D1
45 D2
46 D3
47 D4
48 n.c.
UART with 32-byte FIFOs and IrDA encoder/decoder
n.c.
1
36 n.c.
D5
2
35 RESET
D6
3
34 OUT1
D7
4
33 DTR
RCLK
5
32 RTS
n.c.
6
31 OUT2
SC16C650BIB48
RX
7
30 INT
TX
8
29 RXRDY
CS0
9
28 A0
CS1 10
27 A1
CS2 11
26 A2
AS 24
TXRDY 23
n.c. 21
25 CTS
DDIS 22
IOR 20
IOR 19
27 VCC
26 DSR
GND 18
IOW 17
IOW 16
XTAL2 15
XTAL1 14
25 n.c.
n.c. 13
BAUDOUT 12
002aaa604
28 D0
29 D1
30 D2
32 D4
terminal 1
index area
31 D3
Fig 3. LQFP48 pin configuration.
D5
1
24 RESET
D6
2
23 OUT
D7
3
22 DTR
RCLK
4
RX
5
TX
6
19 RXRDY
CS
7
18 A0
BAUDOUT
8
17 A1
21 RTS
SC16C650BIBS
20 INT
A2 16
TXRDY 15
IOR 14
n.c. 12
GND 13
IOW 11
XTAL2 10
XTAL1
9
(top view)
002aaa947
Fig 4. HVQFN32 pin configuration (top view).
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14451
Product data
Rev. 03 — 10 December 2004
5 of 51
SC16C650B
Philips Semiconductors
UART with 32-byte FIFOs and IrDA encoder/decoder
40 VCC
D1 2
39 RI
D2 3
38 DCD
D3 4
37 DSR
D4 5
36 CTS
D5 6
35 RESET
D6 7
34 OUT1
D7 8
33 DTR
RCLK 9
RX 10
TX 11
CS0 12
SC16C650BIN40
D0 1
32 RTS
31 OUT2
30 INT
29 RXRDY
CS1 13
28 A0
CS2 14
27 A1
BAUDOUT 15
26 A2
XTAL1 16
25 AS
XTAL2 17
24 TXRDY
IOW 18
23 DDIS
IOW 19
22 IOR
GND 20
21 IOR
002aaa605
Fig 5. DIP40 pin configuration.
5.2 Pin description
Table 2:
Pin description
Symbol
Pin
Type
Description
PLCC44 LQFP48 HVQFN32 DIP40
A0-A2
31, 30,
29
28, 27,
26
18, 17, 16 28,
I
27, 26
Register select. A0-A2 are used during read and write
operations to select the UART register to read from or write
to. Refer to Table 3 for register addresses and refer to AS
description.
AS
28
24
-
25
I
Address strobe. When AS is active (LOW), A0, A1, and A2
and CS0, CS1, and CS2 drive the internal select logic
directly; when AS is HIGH, the register select and chip select
signals are held at the logic levels they were in when the
LOW-to-HIGH transition of AS occurred.
BAUDOUT
17
12
8
15
O
Baud out. BAUDOUT is a 16× clock signal for the
transmitter section of the UART. The clock rate is established
by the reference oscillator frequency divided by a divisor
specified in the baud generator divisor latches. BAUDOUT
may also be used for the receiver section by tying this output
to RCLK.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14451
Product data
Rev. 03 — 10 December 2004
6 of 51
SC16C650B
Philips Semiconductors
UART with 32-byte FIFOs and IrDA encoder/decoder
Table 2:
Pin description…continued
Symbol
Pin
Type
Description
PLCC44 LQFP48 HVQFN32 DIP40
CS0, CS1,
CS2
14, 15,
16
9, 10,
11
-
12,
I
13, 14
Chip select. When CS0 and CS1 are HIGH and CS2 is
LOW, these three inputs select the UART. When any of these
inputs are inactive, the UART remains inactive (refer to AS
description).
CS
-
-
7
-
I
CTS
40
38
25
36
I
Clear to send. CTS is a modem status signal. Its condition
can be checked by reading bit 4 (CTS) of the modem status
register. Bit 0 (∆CTS) of the modem status register indicates
that CTS has changed states since the last read from the
modem status register. If the modem status interrupt is
enabled when CTS changes levels and the auto-CTS mode
is not enabled, an interrupt is generated. CTS is also used in
the auto-CTS mode to control the transmitter.
D7-D0
9-2
4-2,
47-43
3-1, 32-28 8-1
I/O
Data bus. Eight data lines with 3-State outputs provide a
bi-directional path for data, control and status information
between the UART and the CPU.
DCD
42
40
-
38
I
Data carrier detect. DCD is a modem status signal. Its
condition can be checked by reading bit 7 (DCD) of the
modem status register. Bit 3 (∆DCD) of the modem status
register indicates that DCD has changed states since the
last read from the modem status register. If the modem
status interrupt is enabled when DCD changes levels, an
interrupt is generated.
DDIS
26
22
-
23
O
Driver disable. DDIS is active (LOW) when the CPU is not
reading data. When active, DDIS can disable an external
transceiver.
DSR
41
39
26
37
I
Data set ready. DSR is a modem status signal. Its condition
can be checked by reading bit 5 (DSR) of the modem status
register. Bit 1 (∆DSR) of the modem status register indicates
DSR has changed levels since the last read from the modem
status register. If the modem status interrupt is enabled
when DSR changes levels, an interrupt is generated.
DTR
37
33
22
33
O
Data terminal ready. When active (LOW), DTR informs a
modem or data set that the UART is ready to establish
communication. DTR is placed in the active level by setting
the DTR bit of the modem control register. DTR is placed in
the inactive level either as a result of a Master Reset, during
loop mode operation, or clearing the DTR bit.
INT
33
30
20
30
O
Interrupt. When active (HIGH), INT informs the CPU that
the UART has an interrupt to be serviced. Four conditions
that cause an interrupt to be issued are: a receiver error,
received data that is available or timed out (FIFO mode
only), an empty transmitter holding register or an enabled
modem status interrupt. INT is reset (deactivated) either
when the interrupt is serviced or as a result of a Master
Reset.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14451
Product data
Rev. 03 — 10 December 2004
7 of 51
SC16C650B
Philips Semiconductors
UART with 32-byte FIFOs and IrDA encoder/decoder
Table 2:
Pin description…continued
Symbol
Pin
Type
Description
PLCC44 LQFP48 HVQFN32 DIP40
OUT1,
OUT2
38, 35
34, 31
-
34, 31 O
Outputs 1 and 2. These are user-designated output
terminals that are set to the active (low) level by setting
respective modem control register (MCR) bits (OUT1 and
OUT2). OUT1 and OUT2 are set to inactive the (HIGH) level
as a result of Master Reset, during loop mode operations, or
by clearing bit 2 (OUT1) or bit 3 (OUT2) of the MCR.
OUT
-
-
23
-
O
RCLK
10
5
4
9
I
Receiver clock. RCLK is the 16× baud rate clock for the
receiver section of the UART.
Read inputs. When either IOR or IOR is active (LOW or
HIGH, respectively) while the UART is selected, the CPU is
allowed to read status information or data from a selected
UART register. Only one of these inputs is required for the
transfer of data during a read operation; the other input
should be tied to its inactive level (i.e., IOR tied LOW or IOR
tied HIGH).
IOR
25
20
-
22
I
IOR
24
19
14
21
I
RESET
39
35
24
35
I
Master Reset. When active (HIGH), MR clears most UART
registers and sets the levels of various output signals.
RI
43
41
-
39
I
Ring indicator. RI is a modem status signal. Its condition
can be checked by reading bit 6 (RI) of the modem status
register. Bit 2 (∆RI) of the modem status register indicates
that RI has transitioned from a LOW to a HIGH level since
the last read from the modem status register. If the modem
status interrupt is enabled when this transition occurs, an
interrupt is generated.
RTS
36
32
21
32
O
Request to send. When active, RTS informs the modem or
data set that the UART is ready to receive data. RTS is set to
the active level by setting the RTS modem control register bit
and is set to the inactive (HIGH) level either as a result of a
Master Reset or during loop mode operations or by clearing
bit 1 (RTS) of the MCR. In the auto-RTS mode, RTS is set to
the inactive level by the receiver threshold control logic.
RXRDY
32
29
19
29
O
Receiver ready. Receiver direct memory access (DMA)
signaling is available with RXRDY. When operating in the
FIFO mode, one of two types of DMA signaling can be
selected using the FIFO control register bit 3 (FCR[3]).
When operating in the 16C450 mode, only DMA mode 0 is
allowed. Mode 0 supports single-transfer DMA in which a
transfer is made between CPU bus cycles. Mode 1 supports
multi-transfer DMA in which multiple transfers are made
continuously until the receiver FIFO has been emptied. In
DMA mode 0 (FCR0 = 0 or FCR0 = 1, FCR3 = 0), when
there is at least one character in the receiver FIFO or
receiver holding register, RXRDY is active (LOW). When
RXRDY has been active but there are no characters in the
FIFO or holding register, RXRDY goes inactive (HIGH). In
DMA mode 1 (FCR0 = 1, FCR3 = 1), when the trigger level
or the time-out has been reached, RXRDY goes active
(LOW); when it has been active but there are no more
characters in the FIFO or holding register, it goes inactive
(HIGH).
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14451
Product data
Rev. 03 — 10 December 2004
8 of 51
SC16C650B
Philips Semiconductors
UART with 32-byte FIFOs and IrDA encoder/decoder
Table 2:
Pin description…continued
Symbol
Pin
Type
Description
PLCC44 LQFP48 HVQFN32 DIP40
RX
11
7
5
10
I
Serial data input. RX is serial data input from a connected
communications device.
TX
13
8
6
11
O
Serial data output. TX is composite serial data output to a
connected communication device. TX is set to the marking
(HIGH) level as a result of Master Reset.
TXRDY
27
23
15
24
O
Transmitter ready. Transmitter DMA signaling is available
with TXRDY. When operating in the FIFO mode, one of two
types of DMA signaling can be selected using FCR[3]. When
operating in the 16C450 mode, only DMA mode 0 is allowed.
Mode 0 supports single-transfer DMA in which a transfer is
made between CPU bus cycles. Mode 1 supports
multi-transfer DMA in which multiple transfers are made
continuously until the transmit FIFO has been filled.
VCC
44
42
27
40
Power 2.5 V, 3 V or 5 V supply voltage.
GND
22
18
13
20
Power Ground voltage.
IOW
21
17
-
19
I
IOW
20
16
11
18
I
XTAL1
18
14
9
16
I
Crystal connection or External clock input.
XTAL2[1]
19
15
10
17
O
Crystal connection or the inversion of XTAL1 if XTAL1 is
driven.
n.c.
1, 12,
23, 34
1, 6, 13, 12
21, 25,
36, 37,
48
-
-
not connected
[1]
Write inputs. When either IOW or IOW is active (LOW or
HIGH, respectively) and while the UART is selected, the
CPU is allowed to write control words or data into a selected
UART register. Only one of these inputs is required to
transfer data during a write operation; the other input should
be tied to its inactive level (i.e., IOW tied LOW or IOW tied
HIGH).
In sleep mode, XTAL2 is left floating.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14451
Product data
Rev. 03 — 10 December 2004
9 of 51
SC16C650B
Philips Semiconductors
UART with 32-byte FIFOs and IrDA encoder/decoder
6. Functional description
The SC16C650B provides serial asynchronous receive data synchronization,
parallel-to-serial and serial-to-parallel data conversions for both the transmitter and
receiver sections. These functions are necessary for converting the serial data
stream into parallel data that is required with digital data systems. Synchronization for
the serial data stream is accomplished by adding start and stop bits to the transmit
data to form a data character (character orientated protocol). Data integrity is insured
by attaching a parity bit to the data character. The parity bit is checked by the receiver
for any transmission bit errors. The SC16C650B is fabricated with an advanced
CMOS process to achieve low drain power and high speed requirements.
The SC16C650B is an upward solution that provides 32 bytes of transmit and receive
FIFO memory, instead of none in the 16C450, or 16 in the 16C550. The SC16C650B
is designed to work with high speed modems and shared network environments that
require fast data processing time. Increased performance is realized in the
SC16C650B by the larger transmit and receive FIFOs. This allows the external
processor to handle more networking tasks within a given time. In addition, the four
selectable levels of FIFO trigger interrupt and automatic hardware/software flow
control is uniquely provided for maximum data throughput performance, especially
when operating in a multi-channel environment. The combination of the above greatly
reduces the bandwidth requirement of the external controlling CPU, increases
performance, and reduces power consumption.
The SC16C650B is capable of operation up to 3 Mbit/s with a 48 MHz external clock
input (at 5 V).
The rich feature set of the SC16C650B is available through internal registers.
Automatic hardware/software flow control, selectable transmit and receive FIFO
trigger level, selectable TX and RX baud rates, modem interface controls, and a sleep
mode are some of these features.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14451
Product data
Rev. 03 — 10 December 2004
10 of 51
SC16C650B
Philips Semiconductors
UART with 32-byte FIFOs and IrDA encoder/decoder
6.1 Internal registers
The SC16C650B provides 17 internal registers for monitoring and control. These
registers are shown in Table 3. Twelve registers are similar to those already available
in the standard 16C550. These registers function as data holding registers
(THR/RHR), interrupt status and control registers (IER/ISR), a FIFO control register
(FCR), line status and control registers (LCR/LSR), modem status and control
registers (MCR/MSR), programmable data rate (clock) control registers (DLL/DLM),
and a user accessible scratchpad register (SPR). Beyond the general 16C550
features and capabilities, the SC16C650B offers an enhanced feature register set
(EFR, Xon/Xoff1-2) that provides on-board hardware/software flow control. Register
functions are more fully described in the following paragraphs.
Table 3:
A2
Internal registers decoding
A1
A0
READ mode
WRITE mode
General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LSR, SPR)[1]
0
0
0
Receive Holding Register
Transmit Holding Register
0
0
1
Interrupt Enable Register
Interrupt Enable Register
0
1
0
Interrupt Status Register
FIFO Control Register
0
1
1
Line Control Register
Line Control Register
1
0
0
Modem Control Register
Modem Control Register
1
0
1
Line Status Register
n/a
1
1
0
Modem Status Register
n/a
1
1
1
Scratchpad Register
Scratchpad Register
Baud rate register set
(DLL/DLM)[2]
0
0
0
LSB of Divisor Latch
LSB of Divisor Latch
0
0
1
MSB of Divisor Latch
MSB of Divisor Latch
Enhanced register set (EFR, Xon/off 1-2)[3]
0
1
0
Enhanced Feature Register
Enhanced Feature Register
1
0
0
Xon1 word
Xon1 word
1
0
1
Xon2 word
Xon2 word
1
1
0
Xoff1 word
Xoff1 word
1
1
1
Xoff2 word
Xoff2 word
[1]
[2]
[3]
These registers are accessible only when LCR[7] is a logic 0.
These registers are accessible only when LCR[7] is a logic 1.
Enhanced Feature Register, Xon1, 2 and Xoff1, 2 are accessible only when the LCR is set to “BF”
(HEX).
6.2 FIFO operation
The 32-byte transmit and receive data FIFOs are enabled by the FIFO Control
Register bit-0 (FCR[0]). With 16C550 devices, the user can set the receive trigger
level, but not the transmit trigger level. The SC16C650B provides independent trigger
levels for both receiver and transmitter. To remain compatible with SC16C550, the
transmit interrupt trigger level is set to 16 following a reset. It should be noted that the
user can set the transmit trigger levels by writing to the FCR register, but activation
will not take place until EFR[4] is set to a logic 1. The receiver FIFO section includes
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14451
Product data
Rev. 03 — 10 December 2004
11 of 51
SC16C650B
Philips Semiconductors
UART with 32-byte FIFOs and IrDA encoder/decoder
a time-out function to ensure data is delivered to the external CPU. An interrupt is
generated whenever the Receive Holding Register (RHR) has not been read
following the loading of a character or the receive trigger level has not been reached.
Table 4:
Flow control mechanism
Selected trigger level
(characters)
INT pin activation
Negate RTS or
send Xoff
Assert RTS or
send Xon
8
8
8
0
16
16
16
7
24
24
24
15
28
28
28
23
6.3 Hardware flow control
When automatic hardware flow control is enabled, the SC16C650B monitors the CTS
pin for a remote buffer overflow indication and controls the RTS pin for local buffer
overflows. Automatic hardware flow control is selected by setting EFR[6] (RTS) and
EFR[7] (CTS) to a logic 1. If CTS transitions from a logic 0 to a logic 1 indicating a
flow control request, ISR[5] will be set to a logic 1 (if enabled via IER[6,7]), and the
SC16C650B will suspend TX transmissions as soon as the stop bit of the character in
process is shifted out. Transmission is resumed after the CTS input returns to a
logic 0, indicating more data may be sent.
With the Auto-RTS function enabled, an interrupt is generated when the receive FIFO
reaches the programmed trigger level. The RTS pin will not be forced to a logic 1
(RTS off), until the receive FIFO reaches the next trigger level. However, the RTS pin
will return to a logic 0 after the data buffer (FIFO) is unloaded to the next trigger level
below the programmed trigger level. However, under the above described conditions,
the SC16C650B will continue to accept data until the receive FIFO is full.
6.4 Software flow control
When software flow control is enabled, the SC16C650B compares one or two
sequential receive data characters with the programmed Xon or Xoff character
value(s). If received character(s) match the programmed Xoff values, the
SC16C650B will halt transmission (TX) as soon as the current character(s) has
completed transmission. When a match occurs, the receive ready (if enabled via Xoff
IER[5]) flags will be set and the interrupt output pin (if receive interrupt is enabled) will
be activated. Following a suspension due to a match of the Xoff characters’ values,
the SC16C650B will monitor the receive data stream for a match to the Xon1,2
character value(s). If a match is found, the SC16C650B will resume operation and
clear the flags (ISR[4]).
Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic 0.
Following reset, the user can write any Xon/Xoff value desired for software flow
control. Different conditions can be set to detect Xon/Xoff characters and
suspend/resume transmissions. When double 8-bit Xon/Xoff characters are selected,
the SC16C650B compares two consecutive receive characters with two software flow
control 8-bit values (Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions
accordingly. Under the above described flow control mechanisms, flow control
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UART with 32-byte FIFOs and IrDA encoder/decoder
characters are not placed (stacked) in the user accessible RX data buffer or FIFO.
When using a software flow control the Xon/Xoff characters cannot be used for data
transfer.
In the event that the receive buffer is overfilling and flow control needs to be executed,
the SC16C650B automatically sends an Xoff message (when enabled) via the serial
TX output to the remote modem. The SC16C650B sends the Xoff1,2 characters as
soon as received data passes the programmed trigger level. To clear this condition,
the SC16C650B will transmit the programmed Xon1,2 characters as soon as receive
data drops below the next low or programmed trigger level.
6.5 Special feature software flow control
A special feature is provided to detect an 8-bit character when EFR[5] is set. When
8-bit character is detected, it will be placed on the user-accessible data stack along
with normal incoming RX data. This condition is selected in conjunction with
EFR[0:3]. Note that software flow control should be turned off when using this special
mode by setting EFR[0:3] to a logic 0.
The SC16C650B compares each incoming receive character with Xoff2 data. If a
match exists, the received data will be transferred to the FIFO, and ISR[4] will be set
to indicate detection of a special character. Although the Internal Register Table
(Table 8) shows each X-Register with eight bits of character information, the actual
number of bits is dependent on the programmed word length. Line Control Register
bits LCR[0:1] define the number of character bits, i.e., either 5 bits, 6 bits, 7 bits or
8 bits. The word length selected by LCR[0:1] also determine the number of bits that
will be used for the special character comparison. Bit 0 in the X-registers corresponds
with the LSB bit for the receive character.
6.6 Hardware/software and time-out interrupts
Three special interrupts have been added to monitor the hardware and software flow
control. The interrupts are enabled by IER[5:7]. Care must be taken when handling
these interrupts. Following a reset, the transmitter interrupt is enabled, the
SC16C650B will issue an interrupt to indicate that the Transmit Holding Register is
empty. This interrupt must be serviced prior to continuing operations. The ISR
register provides the current singular highest priority interrupt only. It could be noted
that CTS and RTS interrupts have lowest interrupt priority. A condition can exist
where a higher priority interrupt may mask the lower priority CTS/RTS interrupt(s).
Only after servicing the higher pending interrupt will the lower priority CTS/TRS
interrupt(s) be reflected in the status register. Servicing the interrupt without
investigating further interrupt conditions can result in data errors.
When two interrupt conditions have the same priority, it is important to service these
interrupts correctly. Receive Data Ready and Receive Time Out have the same
interrupt priority (when enabled by IER[0]). The receiver issues an interrupt after the
number of characters have reached the programmed trigger level. In this case, the
SC16C650B FIFO may hold more characters than the programmed trigger level.
Following the removal of a data byte, the user should re-check LSR[0] for additional
characters. A Receive Time Out will not occur if the receive FIFO is empty. The
time-out counter is reset at the center of each stop bit received or each time the
receive holding register (RHR) is read. The actual time-out value is 4 character time.
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UART with 32-byte FIFOs and IrDA encoder/decoder
6.7 Programmable baud rate generator
The SC16C650B supports high speed modem technologies that have increased
input data rates by employing data compression schemes. For example, a 33.6 kbit/s
modem that employs data compression may require a 115.2 kbit/s input data rate.
A 128.0 kbit/s ISDN modem that supports data compression may need an input
data rate of 460.8 kbit/s.
X1
1.8432 MHz
C1
22 pF
XTAL2
XTAL1
XTAL2
XTAL1
A single baud rate generator is provided for the transmitter and receiver, allowing
independent TX/RX channel control. The programmable Baud Rate Generator is
capable of accepting an input clock up to 48 MHz, as required for supporting a
3 Mbit/s data rate. The SC16C650B can be configured for internal or external clock
operation. For internal clock oscillator operation, an industry standard microprocessor
crystal (parallel resonant/22-33 pF load) is connected externally between the XTAL1
and XTAL2 pins (see Figure 6). Alternatively, an external clock can be connected to
the XTAL1 pin to clock the internal baud rate generator for standard or custom rates
(see Table 5).
X1
1.8432 MHz
C2
33 pF
C1
22 pF
1.5 kΩ
C2
47 pF
002aaa586
Fig 6. Crystal oscillator connection.
The generator divides the input 16× clock by any divisor from 1 to 216 − 1. The
SC16C650B divides the basic crystal or external clock by 16. The frequency of the
BAUDOUT output pin is exactly 16× (16 times) of the selected baud rate
(BAUDOUT = 16 Baud Rate). Customized baud rates can be achieved by selecting
the proper divisor values for the MSB and LSB sections of baud rate generator.
Setting MCR[7] to a logic 1 provides an additional divide-by-4, whereas setting
MCR[7] to a logic 0 only divides by 1 (see Table 5 and Figure 7).
Programming the Baud Rate Generator registers DLM (MSB) and DLL (LSB)
provides a user capability for selecting the desired final baud rate. The example in
Table 5 shows selectable baud rates when using a 1.8432 MHz crystal and setting
MCR[7] to a logic 0.
For custom baud rates, the divisor value can be calculated using the following
equation:
XTAL1 clock frequency
Divisor (in decimal) = ----------------------------------------------------------serial data rate × 16
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UART with 32-byte FIFOs and IrDA encoder/decoder
Table 5:
Baud rates using 1.8432 MHz or 3.072 MHz crystal
Using 1.8432 MHz crystal
Desired
baud rate
Divisor for
16× clock
50
Using 3.072 MHz crystal
Baud rate
error
Desired
baud rate
Divisor for
16× clock
2304
50
3840
75
1536
75
2560
110
1047
0.026
110
1745
0.026
134.5
857
0.058
134.5
1428
0.034
150
768
150
1280
300
384
300
640
600
192
600
320
1200
96
1200
160
1800
64
1800
107
2000
58
2000
96
2400
48
2400
80
3600
32
3600
53
4800
24
4800
40
7200
16
7200
27
9600
12
9600
20
19200
6
19200
10
38400
3
38400
5
56000
2
0.69
XTAL2
0.312
0.628
1.23
2.86
DIVIDE-BY-1
LOGIC
XTAL1
Baud rate
error
MCR[7] = 0
CLOCK
OSCILLATOR
LOGIC
BAUD RATE
GENERATOR
LOGIC
DIVIDE-BY-4
LOGIC
BAUDOUT
MCR[7] = 1
002aaa208
Fig 7. Baud rate generator circuitry.
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UART with 32-byte FIFOs and IrDA encoder/decoder
6.8 DMA operation
The SC16C650B FIFO trigger level provides additional flexibility to the user for block
mode operation. The user can optionally operate the transmit and receive FIFOs in
the DMA mode (FCR[3]). The DMA mode affects the state of the RXRDY and TXRDY
output pins. Tables 6 and 7 show this.
Table 6:
Effect of DMA mode on state of RXRDY pin
Non-DMA mode
DMA mode
1 = FIFO empty
0-to-1 transition when FIFO empties
0 = at least 1 byte in FIFO
1-to-0 transition when FIFO reaches trigger level,
or time-out occurs
Table 7:
Effect of DMA mode on state of TXRDY pin
Non-DMA mode
DMA mode
1 = at least 1 byte in FIFO
0-to-1 transition when FIFO becomes full
0 = FIFO empty
1-to-0 transition when FIFO has 1 empty space
6.9 Sleep mode
The SC16C650B is designed to operate with low power consumption. A special sleep
mode is included to further reduce power consumption when the chip is not being
used. With EFR[4] and IER[4] enabled (set to a logic 1), the SC16C650B enters the
sleep mode, but resumes normal operation when a start bit is detected, a change of
state on any of the modem input pins RI, CTS, DSR, DCD, RX pin, or a transmit data
is provided by the user. If the sleep mode is enabled and the SC16C650B is
awakened by one of the conditions described above, it will return to the sleep mode
automatically after the last character is transmitted or read by the user. In any case,
the sleep mode will not be entered while an interrupt(s) is pending. The SC16C650B
will stay in the sleep mode of operation until it is disabled by setting IER[4] to a
logic 0.
6.10 Loop-back mode
The internal loop-back capability allows on-board diagnostics. In the loop-back mode,
the normal modem interface pins are disconnected and reconfigured for loop-back
internally. MCR[0:3] register bits are used for controlling loop-back diagnostic testing.
In the loop-back mode, OUT1 and OUT2 in the MCR register (bits 2:3) control the
modem RI and DCD inputs, respectively. MCR signals DTR and RTS (bits 0:1) are
used to control the modem DSR and CTS inputs, respectively. The transmitter output
(TX) and the receiver input (RX) are disconnected from their associated interface
pins, and instead are connected together internally (see Figure 8). The CTS, DSR,
DCD, and RI are disconnected from their normal modem control input pins, and
instead are connected internally to DTR, RTS, OUT1 and OUT2. Loop-back test data
is entered into the transmit holding register via the user data bus interface, D0-D7.
The transmit UART serializes the data and passes the serial data to the receive
UART via the internal loop-back connection. The receive UART converts the serial
data back into parallel data that is then made available at the user data interface
D0-D7. The user optionally compares the received data to the initial transmitted data
for verifying error-free operation of the UART TX/RX circuits.
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UART with 32-byte FIFOs and IrDA encoder/decoder
In this mode, the receiver and transmitter interrupts are fully operational. The Modem
Control Interrupts are also operational. However, the interrupts can only be read
using lower four bits of the Modem Status Register (MSR[0:3]) instead of the four
Modem Status Register bits 4:7. The interrupts are still controlled by the IER.
SC16C650B
TRANSMIT
FIFO
REGISTERS
DATA BUS
AND
CONTROL LOGIC
REGISTER
SELECT
LOGIC
INTERCONNECT BUS LINES
AND
CONTROL SIGNALS
FLOW
CONTROL
LOGIC
A0–A2
CS0, CS1
CS2
AS
TX
RECEIVE
FIFO
REGISTERS
FLOW
CONTROL
LOGIC
IR
ENCODER
MCR[4] = 1
D0–D7
IOR, IOR
IOW, IOW
RESET
TRANSMIT
SHIFT
REGISTER
RECEIVE
SHIFT
REGISTER
RX
IR
DECODER
RTS
DDIS
CTS
DTR
MODEM
CONTROL
LOGIC
DSR
OUT1
INT
TXRDY
RXRDY
INTERRUPT
CONTROL
LOGIC
RI
CLOCK AND
BAUD RATE
GENERATOR
OUT2
DCD
002aaa606
XTAL1
RCLK
XTAL2
BAUDOUT
Fig 8. Internal loop-back mode diagram.
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UART with 32-byte FIFOs and IrDA encoder/decoder
7. Register descriptions
Table 8 details the assigned bit functions for the fifteen SC16C650B internal registers.
The assigned bit functions are more fully defined in Section 7.1 through Section 7.11.
Table 8:
SC16C650B internal registers
Shaded bits are only accessible when EFR[4] is set.
A2 A1 A0 Register Default[1] Bit 7
General Register
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Set[2]
0
0
0
RHR
XX
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0
0
0
THR
XX
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0
0
1
IER
00
CTS
interrupt
RTS
interrupt
Xoff
interrupt
Sleep
mode
modem
status
interrupt
receive
transmit
line status holding
interrupt
register
receive
holding
register
0
1
0
FCR
00
RCVR
trigger
(MSB)
RCVR
trigger
(LSB)
TX
trigger
(MSB)
TX trigger DMA
(LSB)
mode
select
XMIT
FIFO
reset
RCVR
FIFO
reset
FIFO
enable
0
1
0
ISR
01
FIFOs
enabled
FIFOs
enabled
INT
priority
bit 4
INT
priority
bit 3
INT
priority
bit 2
INT
priority
bit 1
INT
priority
bit 0
INT
status
0
1
1
LCR
00
divisor
latch
enable
set break set parity even
parity
parity
enable
stop bits
word
length
bit 1
word
length
bit 0
1
0
0
MCR
00
Clock
select
IR enable INT type loop back OUT2,
select
INT
enable
OUT1
RTS
DTR
1
0
1
LSR
60
FIFO
data
error
trans.
empty
trans.
holding
empty
break
interrupt
framing
error
parity
error
overrun
error
receive
data
ready
1
1
0
MSR
X0
DCD
RI
DSR
CTS
∆DCD
∆RI
∆DSR
∆CTS
1
1
1
SPR
FF
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
XX
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
XX
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Special Register
Set[3]
0
0
0
DLL
0
0
1
DLM
Enhanced Register
Set[4]
0
1
0
EFR
00
Auto
CTS
Auto RTS Special
char.
select
Enable
Cont-3
IER[4:7], Tx, Rx
ISR[4,5], Control
FCR[4,5],
MCR[5:7]
Cont-2
Tx, Rx
Control
Cont-1
Tx, Rx
Control
Cont-0
Tx, Rx
Control
1
0
0
Xon-1
00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
1
0
1
Xon-2
00
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
1
1
0
Xoff-1
00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
1
1
1
Xoff-2
00
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
[1]
[2]
[3]
[4]
The value shown represents the register’s initialized HEX value; X = n/a.
These registers are accessible only when LCR[7] = 0.
The Special Register set is accessible only when LCR[7] is set to a logic 1.
Enhanced Feature Register, Xon-1,2 and Xoff-1,2 are accessible only when LCR is set to ‘BFHex’.
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UART with 32-byte FIFOs and IrDA encoder/decoder
7.1 Transmit (THR) and Receive (RHR) Holding Registers
The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and
Transmit Shift Register (TSR). The status of the THR is provided in the Line Status
Register (LSR). Writing to the THR transfers the contents of the data bus (D7-D0) to
the THR, providing that the THR or TSR is empty. The THR empty flag in the LSR
register will be set to a logic 1 when the transmitter is empty or when data is
transferred to the TSR. Note that a write operation can be performed when the THR
empty flag is set (logic 0 = FIFO full; logic 1 = at least one FIFO location available).
The serial receive section also contains an 8-bit Receive Holding Register (RHR).
Receive data is removed from the SC16C650B and receive FIFO by reading the RHR
register. The receive section provides a mechanism to prevent false starts. On the
falling edge of a start or false start bit, an internal receiver counter starts counting
clocks at the 16× clock rate. After 7-1⁄2 clocks, the start bit time should be shifted to
the center of the start bit. At this time the start bit is sampled, and if it is still a logic 0
it is validated. Evaluating the start bit in this manner prevents the receiver from
assembling a false character. Receiver status codes will be posted in the LSR.
7.2 Interrupt Enable Register (IER)
The Interrupt Enable Register (IER) masks the interrupts from receiver ready,
transmitter empty, line status and modem status registers. These interrupts would
normally be seen on the INT output pin.
Table 9:
Interrupt Enable Register bits description
Bit
Symbol
Description
7
IER[7]
CTS interrupt.
Logic 0 = Disable the CTS interrupt (normal default condition).
Logic 1 = Enable the CTS interrupt. The SC16C650B issues an interrupt
when the CTS pin transitions from a logic 0 to a logic 1.
6
IER[6]
RTS interrupt.
Logic 0 = Disable the RTS interrupt (normal default condition).
Logic 1 = Enable the RTS interrupt. The SC16C650B issues an interrupt
when the RTS pin transitions from a logic 0 to a logic 1.
5
IER[5]
Xoff interrupt.
Logic 0 = Disable the software flow control, receive Xoff interrupt
(normal default condition).
Logic 1 = Enable the software flow control, receive Xoff interrupt. See
Section 6.4 “Software flow control” for details.
4
IER[4]
Sleep mode.
Logic 0 = Disable sleep mode (normal default condition).
Logic 1 = Enable sleep mode. See Section 6.9 “Sleep mode” for details.
3
IER[3]
Modem Status Interrupt.
Logic 0 = Disable the modem status register interrupt (normal default
condition).
Logic 1 = Enable the modem status register interrupt.
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UART with 32-byte FIFOs and IrDA encoder/decoder
Table 9:
Interrupt Enable Register bits description…continued
Bit
Symbol
Description
2
IER[2]
Receive Line Status interrupt. This interrupt will be issued whenever a fully
assembled receive character is transferred from RSR to the RHR/FIFO,
i.e., data ready, LSR[0].
Logic 0 = Disable the receiver line status interrupt (normal default
condition).
Logic 1 = Enable the receiver line status interrupt.
1
IER[1]
Transmit Holding Register interrupt. This interrupt will be issued whenever
the THR is empty, and is associated with LSR[1].
Logic 0 = Disable the transmitter empty interrupt (normal default
condition).
Logic 1 = Enable the transmitter empty interrupt.
0
IER[0]
Receive Holding Register interrupt. This interrupt will be issued when the
FIFO has reached the programmed trigger level, or is cleared when the
FIFO drops below the trigger level in the FIFO mode of operation.
Logic 0 = Disable the receiver ready interrupt (normal default condition).
Logic 1 = Enable the receiver ready interrupt.
7.2.1
IER versus Receive FIFO interrupt mode operation
When the receive FIFO (FCR[0] = logic 1), and receive interrupts (IER[0] = logic 1)
are enabled, the receive interrupts and register status will reflect the following:
• The receive data available interrupts are issued to the external CPU when the
FIFO has reached the programmed trigger level. It will be cleared when the FIFO
drops below the programmed trigger level.
• FIFO status will also be reflected in the user accessible ISR register when the
FIFO trigger level is reached. Both the ISR register status bit and the interrupt will
be cleared when the FIFO drops below the trigger level.
• The data ready bit (LSR[0]) is set as soon as a character is transferred from the
shift register to the receive FIFO. It is reset when the FIFO is empty.
7.2.2
IER versus Receive/Transmit FIFO polled mode operation
When FCR[0] = logic 1, resetting IER[0:3] enables the SC16C650B in the FIFO
polled mode of operation. Since the receiver and transmitter have separate bits in the
LSR, either or both can be used in the polled mode by selecting respective transmit or
receive control bit(s).
•
•
•
•
LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO.
LSR[1:4] will provide the type of errors encountered, if any.
LSR[5] will indicate when the transmit FIFO is empty.
LSR[6] will indicate when both the transmit FIFO and transmit shift register are
empty.
• LSR[7] will indicate any FIFO data errors.
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UART with 32-byte FIFOs and IrDA encoder/decoder
7.3 FIFO Control Register (FCR)
This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO
trigger levels, and select the DMA mode.
7.3.1
DMA mode
Mode 0 (FCR bit 3 = 0): Set and enable the interrupt for each single transmit or
receive operation, and is similar to the 16C450 mode. Transmit Ready (TXRDY) will
go to a logic 0 whenever an empty transmit space is available in the Transmit Holding
Register (THR). Receive Ready (RXRDY) will go to a logic 0 whenever the Receive
Holding Register (RHR) is loaded with a character.
Mode 1 (FCR bit 3 = 1): Set and enable the interrupt in a block mode operation. The
transmit interrupt is set when the transmit FIFO is below the programmed trigger
level. The receive interrupt is set when the receive FIFO fills to the programmed
trigger level. However, the FIFO continues to fill regardless of the programmed level
until the FIFO is full. RXRDY remains a logic 0 as long as the FIFO fill level is above
the programmed trigger level.
7.3.2
FIFO mode
Table 10:
FIFO Control Register bits description
Bit
Symbol
Description
7-6
FCR[7]
(MSB),
FCR[6]
(LSB)
RCVR trigger. These bits are used to set the trigger level for the receive
FIFO interrupt.
FCR[5]
(MSB),
FCR[4]
(LSB)
Logic 0 or cleared is the default condition; TX trigger level = 16.
FCR[3]
DMA mode select.
5-4
3
An interrupt is generated when the number of characters in the FIFO
equals the programmed trigger level. However, the FIFO will continue to
be loaded until it is full. Refer to Table 11.
These bits are used to set the trigger level for the transmit FIFO
interrupt. The SC16C650B will issue a transmit empty interrupt when the
number of characters in FIFO drops below the selected trigger level.
Refer to Table 12.
Logic 0 = Set DMA mode ‘0’ (normal default condition).
Logic 1 = Set DMA mode ‘1’
Transmit operation in mode ‘0’: When the SC16C650B is in the
16C450 mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO mode
(FIFOs enabled; FCR[0] = logic 1; FCR[3] = logic 0), and when there are
no characters in the transmit FIFO or transmit holding register, the
TXRDY pin will be a logic 0. Once active, the TXRDY pin will go to a
logic 1 after the first character is loaded into the transmit holding
register.
Receive operation in mode ‘0’: When the SC16C650B is in 16C450
mode, or in the FIFO mode (FCR[0] = logic 1; FCR[3] = logic 0) and
there is at least one character in the receive FIFO, the RXRDY pin will
be a logic 0. Once active, the RXRDY pin will go to a logic 1 when there
are no more characters in the receiver.
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UART with 32-byte FIFOs and IrDA encoder/decoder
Table 10:
Bit
FIFO Control Register bits description…continued
Symbol
Description
Transmit operation in mode ‘1’: When the SC16C650B is in FIFO
mode (FCR[0] = logic 1; FCR[3] = logic 1), the TXRDY pin will be a
logic 1 when the transmit FIFO is completely full. It will be a logic 0 when
FIFO has 1 empty space.
Receive operation in mode ‘1’: When the SC16C650B is in FIFO
mode (FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has been
reached, or a Receive Time-Out has occurred, the RXRDY pin will go to
a logic 0. Once activated, it will go to a logic 1 after there are no more
characters in the FIFO.
2
FCR[2]
XMIT FIFO reset.
Logic 0 = No FIFO transmit reset (normal default condition).
Logic 1 = Clears the contents of the transmit FIFO and resets the
FIFO counter logic (the transmit shift register is not cleared or
altered). This bit will return to a logic 0 after clearing the FIFO.
1
FCR[1]
RCVR FIFO reset.
Logic 0 = No FIFO receive reset (normal default condition).
Logic 1 = Clears the contents of the receive FIFO and resets the FIFO
counter logic (the receive shift register is not cleared or altered). This
bit will return to a logic 0 after clearing the FIFO.
0
FCR[0]
FIFO enable.
Logic 0 = Disable the transmit and receive FIFO (normal default
condition).
Logic 1 = Enable the transmit and receive FIFO. This bit must be a
‘1’ when other FCR bits are written to, or they will not be
programmed.
Table 11:
RCVR trigger levels
FCR[7]
FCR[6]
RX FIFO trigger level (bytes)
0
0
8
0
1
16
1
0
24
1
1
28
Table 12:
TX FIFO trigger levels
FCR[5]
FCR[4]
TX FIFO trigger level (bytes)
0
0
16
0
1
8
1
0
24
1
1
30
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SC16C650B
Philips Semiconductors
UART with 32-byte FIFOs and IrDA encoder/decoder
7.4 Interrupt Status Register (ISR)
The SC16C650B provides six levels of prioritized interrupts to minimize external
software interaction. The Interrupt Status Register (ISR) provides the user with six
interrupt status bits. Performing a read cycle on the ISR will provide the user with the
highest pending interrupt level to be serviced. No other interrupts are acknowledged
until the pending interrupt is serviced. Whenever the interrupt status register is read,
the interrupt status is cleared. However, it should be noted that only the current
pending interrupt is cleared by the read. A lower level interrupt may be seen after
re-reading the interrupt status bits. Table 13 “Interrupt source” shows the data values
(bits 0:5) for the six prioritized interrupt levels and the interrupt sources associated
with each of these interrupt levels.
Table 13:
Interrupt source
Priority
level
ISR[5]
ISR[4]
ISR[3]
ISR[2]
ISR[1]
ISR[0]
Source of the interrupt
1
0
0
0
1
1
0
LSR (Receiver Line Status
Register)
2
0
0
0
1
0
0
RXRDY (Received Data
Ready)
2
0
0
1
1
0
0
RXRDY (Receive Data
time-out)
3
0
0
0
0
1
0
TXRDY (Transmitter
Holding Register Empty)
4
0
0
0
0
0
0
MSR (Modem Status
Register)
5
0
1
0
0
0
0
RXRDY (Received Xoff
signal) / Special character
6
1
0
0
0
0
0
CTS, RTS change of state
Table 14:
Interrupt Status Register bits description
Bit
Symbol
Description
7:6
ISR[7:6]
FIFOs enabled. These bits are set to a logic 0 when the FIFO is
not being used. They are set to a logic 1 when the FIFOs are
enabled.
Logic 0 or cleared = default condition.
5:4
ISR[5:4]
INT priority bits 4:3. These bits are enabled when EFR[4] is set to
a logic 1. ISR[4] indicates that matching Xoff character(s) have
been detected. ISR[5] indicates that CTS, RTS have been
generated. Note that once set to a logic 1, the ISR[4] bit will stay a
logic 1 until Xon character(s) are received.
Logic 0 or cleared = default condition.
3:1
ISR[3:1]
INT priority bits 2:0. These bits indicate the source for a pending
interrupt at interrupt priority levels 1, 2, and 3 (see Table 13).
0
ISR[0]
INT status.
Logic 0 or cleared = default condition.
Logic 0 = An interrupt is pending and the ISR contents may be
used as a pointer to the appropriate interrupt service routine.
Logic 1 = No interrupt pending (normal default condition).
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UART with 32-byte FIFOs and IrDA encoder/decoder
7.5 Line Control Register (LCR)
The Line Control Register is used to specify the asynchronous data communication
format. The word length, the number of stop bits, and the parity are selected by
writing the appropriate bits in this register.
Table 15:
Line Control Register bits description
Bit
Symbol
Description
7
LCR[7]
Divisor latch enable. The internal baud rate counter latch and Enhance
Feature mode enable.
Logic 0 = Divisor latch disabled (normal default condition).
Logic 1 = Divisor latch and enhanced feature register enabled.
6
LCR[6]
Set break. When enabled, the Break control bit causes a break condition
to be transmitted (the TX output is forced to a logic 0 state). This
condition exists until disabled by setting LCR[6] to a logic 0.
Logic 0 = no TX break condition (normal default condition).
Logic 1 = forces the transmitter output (TX) to a logic 0 for alerting the
remote receiver to a line break condition.
5
LCR[5]
Set parity. If the parity bit is enabled, LCR[5] selects the forced parity
format. Programs the parity conditions (see Table 16).
Logic 0 = parity is not forced (normal default condition).
LCR[5] = logic 1 and LCR[4] = logic 0: parity bit is forced to a logical 1
for the transmit and receive data.
LCR[5] = logic 1 and LCR[4] = logic 1: parity bit is forced to a logical 0
for the transmit and receive data.
4
LCR[4]
Even parity. If the parity bit is enabled with LCR[3] set to a logic 1,
LCR[4] selects the even or odd parity format.
Logic 0 = ODD Parity is generated by forcing an odd number of
logic 1s in the transmitted data. The receiver must be programmed to
check the same format (normal default condition).
Logic 1 = EVEN Parity is generated by forcing an even number of
logic 1s in the transmitted data. The receiver must be programmed to
check the same format.
3
LCR[3]
Parity enable. Parity or no parity can be selected via this bit.
Logic 0 = no parity (normal default condition).
Logic 1 = a parity bit is generated during the transmission, receiver
checks the data and parity for transmission errors.
2
LCR[2]
Stop bits. The length of stop bit is specified by this bit in conjunction with
the programmed word length (see Table 17).
Logic 0 or cleared = default condition.
1:0
LCR[1:0]
Word length bits 1, 0. These two bits specify the word length to be
transmitted or received (see Table 18).
Logic 0 or cleared = default condition.
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UART with 32-byte FIFOs and IrDA encoder/decoder
Table 16:
LCR[5] parity selection
LCR[5]
LCR[4]
LCR[3]
Parity selection
X
X
0
no parity
0
0
1
ODD parity
0
1
1
EVEN parity
1
0
1
force parity ‘1’
1
1
1
forced parity ‘0’
Table 17:
LCR[2] stop bit length
LCR[2]
Word length
0
5, 6, 7, 8
1
1
5
1-1⁄2
1
6, 7, 8
2
Table 18:
Stop bit length (bit times)
LCR[1:0] word length
LCR[1]
LCR[0]
Word length
0
0
5
0
1
6
1
0
7
1
1
8
7.6 Modem Control Register (MCR)
This register controls the interface with the modem or a peripheral device.
Table 19:
Modem Control Register bits description
Bit
Symbol
Description
7
MCR[7]
Clock select.
Logic 0 = Divide-by-1. The input clock (crystal or external) is
divided by 16 and then presented to the Programmable Baud Rate
Generator (BGR) without further modification, i.e., divide-by-1
(normal default condition).
Logic 1 = Divide-by-4. The divide-by-1 clock described in MCR[7]
equals a logic 0, is further divided by four (see also Section 6.7
“Programmable baud rate generator”).
6
MCR[6]
IR enable.
Logic 0 = Enable the standard modem receive and transmit
input/output interface (normal default condition).
Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs.
While in this mode, the TX/RX output/inputs are routed to the
infrared encoder/decoder. The data input and output levels will
conform to the IrDA infrared interface requirement. As such, while
in this mode, the infrared TX output will be a logic 0 during idle data
conditions.
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UART with 32-byte FIFOs and IrDA encoder/decoder
Table 19:
Modem Control Register bits description…continued
Bit
Symbol
Description
5
MCR[5]
INT typ select.
Logic 0 = Enable active or 3-State interrupt output mode (normal
default condition).
Logic= 1 = Enable open source interrupt output mode. Provides
shared interrupts in the STD mode by producing a wire-OR output
driver capability for interrupts. This output appears at the IRQA/INT
pin. When using this option, an external pull-down resistor of
200 to 500 Ω must be tied from the IRQA/INT pin to ground to
provide and acceptable logic 0 level
4
MCR[4]
Loop-back. Enable the local loop-back mode (diagnostics). In this
mode the transmitter output (TX) and the receiver input (RX), CTS,
DSR, DCD, and RI are disconnected from the SC16C650B I/O pins.
Internally the modem data and control pins are connected into a
loop-back data configuration (see Figure 8). In this mode, the receiver
and transmitter interrupts remain fully operational. The Modem
Control Interrupts are also operational, but the interrupts’ sources are
switched to the lower four bits of the Modem Control. Interrupts
continue to be controlled by the IER register.
Logic 0 = Disable loop-back mode (normal default condition).
Logic 1 = Enable local loop-back mode (diagnostics).
3
MCR[3]
OUT2, INTx enable. Used to control the modem DCD signal in the
loop-back mode.
Logic 0 = Forces INT output to the 3-State mode. In the loop-back
mode, sets OUT2 (DCD) internally to a logic 1.
Logic 1 = Forces the INT output to the active mode. In the
loop-back mode, sets OUT2 (DCD) internally to a logic 0.
2
MCR[2]
OUT1. This bit is used in the Loop-back mode only. In the loop-back
mode, this bit is used to write the state of the modem RI interface
signal via OUT1.
1
MCR[1]
RTS
Logic 0 = Force RTS output to a logic 1 (normal default condition).
Logic 1 = Force RTS output to a logic 0.
0
MCR[0]
DTR
Logic 0 = Force DTR output to a logic 1 (normal default condition).
Logic 1 = Force DTR output to a logic 0.
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UART with 32-byte FIFOs and IrDA encoder/decoder
7.7 Line Status Register (LSR)
This register provides the status of data transfers between the SC16C650B and
the CPU.
Table 20:
Line Status Register bits description
Bit
Symbol
Description
7
LSR[7]
FIFO data error.
Logic 0 = No error (normal default condition).
Logic 1 = At least one parity error, framing error or break indication is in
the current FIFO data. This bit is cleared when LSR register is read.
6
LSR[6]
THR and TSR empty. This bit is the Transmit Empty indicator. This bit is
set to a logic 1 whenever the transmit holding register and the transmit
shift register are both empty. It is reset to logic 0 whenever either the THR
or TSR contains a data character. In the FIFO mode, this bit is set to ‘1’
whenever the transmit FIFO and transmit shift register are both empty.
5
LSR[5]
THR empty. This bit is the Transmit Holding Register Empty indicator.
This bit indicates that the UART is ready to accept a new character for
transmission. In addition, this bit causes the UART to issue an interrupt to
CPU when the THR interrupt enable is set. The THR bit is set to a logic 1
when a character is transferred from the transmit holding register into the
transmitter shift register. The bit is reset to a logic 0 concurrently with the
loading of the transmitter holding register by the CPU. In the FIFO mode,
this bit is set when the transmit FIFO is empty; it is cleared when at least
1 byte is written to the transmit FIFO.
4
LSR[4]
Break interrupt.
Logic 0 = No break condition (normal default condition).
Logic 1 = The receiver received a break signal (RX was a logic 0 for
one character frame time). In the FIFO mode, only one break character
is loaded into the FIFO.
3
LSR[3]
Framing error.
Logic 0 = No framing error (normal default condition).
Logic 1 = Framing error. The receive character did not have a valid stop
bit(s). In the FIFO mode, this error is associated with the character at
the top of the FIFO.
2
LSR[2]
Parity error.
Logic 0 = No parity error (normal default condition).
Logic 1 = Parity error. The receive character does not have correct
parity information and is suspect. In the FIFO mode, this error is
associated with the character at the top of the FIFO.
1
LSR[1]
Overrun error.
Logic 0 = No overrun error (normal default condition).
Logic 1 = Overrun error. A data overrun error occurred in the receive
shift register. This happens when additional data arrives while the FIFO
is full. In this case, the previous data in the shift register is overwritten.
Note that under this condition, the data byte in the receive shift register
is not transferred into the FIFO, therefore the data in the FIFO is not
corrupted by the error.
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UART with 32-byte FIFOs and IrDA encoder/decoder
Table 20:
Line Status Register bits description…continued
Bit
Symbol
Description
0
LSR[0]
Receive data ready.
Logic 0 = No data in receive holding register or FIFO (normal default
condition).
Logic 1 = Data has been received and is saved in the receive holding
register or FIFO.
7.8 Modem Status Register (MSR)
This register provides the current state of the control interface signals from the
modem, or other peripheral device to which the SC16C650B is connected. Four bits
of this register are used to indicate the changed information. These bits are set to a
logic 1 whenever a control input from the modem changes state. These bits are set to
a logic 0 whenever the CPU reads this register.
Table 21:
Modem Status Register bits description
Bit
Symbol
Description
7
MSR[7]
Data Carrier Detect. DCD (Active-HIGH, logical 1). Normally this bit is
the complement of the DCD input. In the loop-back mode this bit is
equivalent to the OUT2 bit in the MCR register.
6
MSR[6]
Ring Indicator. RI (Active-HIGH, logical 1). Normally this bit is the
complement of the RI input. In the loop-back mode this bit is equivalent
to the OUT1 bit in the MCR register.
5
MSR[5]
Data Set Ready. DSR (Active-HIGH, logical 1). Normally this bit is the
complement of the DSR input. In loop-back mode this bit is equivalent to
the DTR bit in the MCR register.
4
MSR[4]
Clear To Send. CTS. CTS functions as hardware flow control signal input
if it is enabled via EFR[7]. Flow control (when enabled) allows starting
and stopping the transmissions based on the external modem CTS
signal. A logic 1 at the CTS pin will stop SC16C650B transmissions as
soon as current character has finished transmission. Normally MSR[4] is
the complement of the CTS input. However, in the loop-back mode, this
bit is equivalent to the RTS bit in the MCR register.
3
MSR[3]
∆DCD [1]
Logic 0 = No DCD change (normal default condition).
Logic 1 = The DCD input to the SC16C650B has changed state since
the last time it was read. A modem Status Interrupt will be generated.
2
MSR[2]
∆RI [1]
Logic 0 = No RI change (normal default condition).
Logic 1 = The RI input to the SC16C650B has changed from a logic 0
to a logic 1. A modem Status Interrupt will be generated.
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UART with 32-byte FIFOs and IrDA encoder/decoder
Table 21:
Modem Status Register bits description…continued
Bit
Symbol
Description
1
MSR[1]
∆DSR [1]
Logic 0 = No DSR change (normal default condition).
Logic 1 = The DSR input to the SC16C650B has changed state since
the last time it was read. A modem Status Interrupt will be generated.
0
MSR[0]
∆CTS [1]
Logic 0 = No CTS change (normal default condition).
Logic 1 = The CTS input to the SC16C650B has changed state since
the last time it was read. A modem Status Interrupt will be generated.
[1]
Whenever any MSR bit 0:3 is set to logic 1, a Modem Status Interrupt will be generated.
7.9 Scratchpad Register (SPR)
The SC16C650B provides a temporary data register to store 8 bits of user
information.
7.10 Enhanced Feature Register (EFR)
Enhanced features are enabled or disabled using this register.
Bits 0 through 4 provide single or dual character software flow control selection.
When the Xon1 and Xon2 and/or Xoff1 and Xoff2 modes are selected, the double
8-bit words are concatenated into two sequential numbers.
Table 22:
Enhanced Feature Register bits description
Bit
Symbol
Description
7
EFR[7]
Automatic CTS flow control.
Logic 0 = Automatic CTS flow control is disabled (normal default
condition).
Logic 1 = Enable Automatic CTS flow control. Transmission will stop
when CTS goes to a logical 1. Transmission will resume when the CTS
pin returns to a logical 0.
6
EFR[6]
Automatic RTS flow control. Automatic RTS may be used for hardware flow
control by enabling EFR[6]. When Auto-RTS is selected, an interrupt will
be generated when the receive FIFO is filled to the programmed trigger
level and RTS will go to a logic 1 at the next trigger level. RTS will return to
a logic 0 when data is unloaded below the next lower trigger level
(programmed trigger level 1). The state of this register bit changes with the
status of the hardware flow control. RTS functions normally when
hardware flow control is disabled.
0 = Automatic RTS flow control is disabled (normal default condition).
1 = Enable Automatic RTS flow control.
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UART with 32-byte FIFOs and IrDA encoder/decoder
Table 22:
Enhanced Feature Register bits description…continued
Bit
Symbol
Description
5
EFR[5]
Special Character Detect.
Logic 0 = Special character detect disabled (normal default condition).
Logic 1 = Special character detect enabled. The SC16C650B compares
each incoming receive character with Xoff2 data. If a match exists, the
received data will be transferred to FIFO and ISR[4] will be set to
indicate detection of special character. Bit-0 in the X-registers
corresponds with the LSB bit for the receive character. When this feature
is enabled, the normal software flow control must be disabled (EFR[3:0]
must be set to a logic 0).
4
EFR[4]
Enhanced function control bit. The content of IER[7:4], ISR[5:4], FCR[5:4],
and MCR[7:5] can be modified and latched. After modifying any bits in the
enhanced registers, EFR[4] can be set to a logic 0 to latch the new values.
This feature prevents existing software from altering or overwriting the
SC16C650B enhanced functions.
Logic 0 = Disable (normal default condition).
Logic 1 = Enable.
3:0
EFR[3:0] Cont-3:0 Tx, Rx control. Logic 0 or cleared is the default condition.
Combinations of software flow control can be selected by programming
these bits. See Table 23.
Software flow control functions[1]
Table 23:
Cont-3
Cont-2
Cont-1
Cont-0
TX, RX software flow controls
0
0
X
X
No transmit flow control
1
0
X
X
Transmit Xon1/Xoff1
0
1
X
X
Transmit Xon2/Xoff2
1
1
X
X
Transmit Xon1 and Xon2/Xoff1 and Xoff2
X
X
0
0
No receive flow control
X
X
1
0
Receiver compares Xon1/Xoff1
X
X
0
1
Receiver compares Xon2/Xoff2
1
0
1
1
Transmit Xon1/Xoff1
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
0
1
1
1
Transmit Xon2/Xoff2
1
1
1
1
Transmit Xon1 and Xon2/Xoff1 and Xoff2
Receiver compares Xon1 and Xon2/Xoff1 and Xoff2
Receiver compares Xon1 and Xon2/Xoff1 and Xoff2
[1]
When using a software flow control the Xon/Xoff characters cannot be used for data transfer.
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SC16C650B
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UART with 32-byte FIFOs and IrDA encoder/decoder
7.11 SC16C650B external reset conditions
Table 24:
Reset state for registers
Register
Reset state
IER
IER[7:0] = 0
ISR
ISR[7:1] = 0; ISR[0] = 1
LCR
LCR[7:0] = 0
MCR
MCR[7:0] = 0
LSR
LSR[7] = 0; LSR[6:5] = 1; LSR[4:0] = 0
MSR
MSR[7:4] = input signals; MSR[3:0] = 0
FCR
FCR[7:0] = 0
EFR
EFR[7:0] = 0
Table 25:
Reset state for outputs
Output
Reset state
TX
HIGH
RTS
HIGH
DTR
HIGH
RXRDY
HIGH (STD mode)
TXRDY
LOW (STD mode)
INT
LOW (STD mode)
8. Limiting values
Table 26: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Min
Max
Unit
VCC
supply voltage
Conditions
-
7
V
Vn
voltage at any pin
GND − 0.3
VCC + 0.3
V
Tamb
operating temperature
−40
+85
°C
Tstg
storage temperature
−65
+150
°C
Ptot(pack)
total power dissipation per
package
-
500
mW
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UART with 32-byte FIFOs and IrDA encoder/decoder
9. Static characteristics
Table 27: DC electrical characteristics
Tamb = −40 °C to +85 °C; VCC = 2.5 V, 3.3 V or 5.0 V ±10%, unless otherwise specified.
Symbol
Parameter
Conditions
2.5 V
3.3 V
5.0 V
Min
Max
Min
Max
Min
Max
Unit
VIL(CK)
LOW-level clock input voltage
−0.3
0.45
−0.3
0.6
−0.5
0.6
V
VIH(CK)
HIGH-level clock input voltage
1.8
VCC
2.4
VCC
3.0
VCC
V
VIL
LOW-level input voltage
−0.3
0.65
−0.3
0.8
−0.5
0.8
V
VIH
HIGH-level input voltage
1.6
-
2.0
-
2.2
VCC
V
VOL
LOW-level output voltage
on all outputs[1]
IOL = 5 mA
(databus)
-
-
-
-
-
0.4
V
IOL = 4 mA
(other outputs)
-
-
-
0.4
-
-
V
IOL = 2 mA
(databus)
-
0.4
-
-
-
-
V
IOL = 1.6 mA
(other outputs)
-
0.4
-
-
-
-
V
IOH = −5 mA
(databus)
-
-
-
-
2.4
-
V
IOH = −1 mA
(other outputs)
-
-
2.0
-
-
-
V
IOH = −800 µA
(databus)
1.85
-
-
-
-
-
V
IOH = −400 µA
(other outputs)
1.85
-
-
-
-
-
V
VOH
HIGH-level output voltage
ILIL
LOW-level input leakage current
-
±10
-
±10
-
±10
µA
ICL
clock leakage
-
±30
-
±30
-
±30
µA
ICC
average power supply current
-
3.5
-
4.5
-
4.5
mA
Ci
input capacitance
-
5
-
5
-
5
pF
500
-
500
-
500
-
kΩ
Rpu(int)
[1]
[2]
internal pull-up
resistance[2]
f = 5 MHz
Except for x2, VOL = 1 V typically.
Refer to Table 2 “Pin description” on page 6 for a listing of pins having internal pull-up resistors.
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UART with 32-byte FIFOs and IrDA encoder/decoder
10. Dynamic characteristics
Table 28: AC electrical characteristics
Tamb = −40 °C to +85 °C; VCC = 2.5 V, 3.3 V or 5 V ±10%, unless otherwise specified.
Symbol
Parameter
Conditions
2.5 V
3.3 V
5.0 V
Unit
Min
Max
Min
Max
Min
Max
15
-
13
-
10
-
ns
-
16
-
32
-
48
MHz
t1w, t2w
clock pulse duration
t3w
oscillator/clock frequency
t4w
address strobe width
45
-
35
-
25
-
ns
t5s
address set-up time
5
-
5
-
1
-
ns
t5h
address hold time
5
-
5
-
5
-
ns
t6s
chip select set-up time to AS
10
-
5
-
0
-
ns
t6h
address hold time
0
-
0
-
0
-
ns
10
-
10
-
5
-
ns
t6s'
address set-up time
[1]
[2]
t6h
chip select hold time
0
-
0
-
0
-
ns
t7d
IOR delay from chip select
10
-
10
-
10
-
ns
t7w
IOR strobe width
77
-
26
-
23
-
ns
t7h
chip select hold time from IOR
0
-
0
-
0
-
ns
5
-
5
-
5
-
ns
10
-
10
-
10
-
ns
25 pF load
[2]
t7h'
address hold time
t8d
IOR delay from address
t9d
read cycle delay
25 pF load
20
-
20
-
20
-
ns
t11d
IOR to DDIS delay
25 pF load
-
100
-
35
-
30
ns
t12d
delay from IOR to data
25 pF load
-
77
-
26
-
23
ns
t12h
data disable time
25 pF load
-
15
-
15
-
15
ns
t13d
IOW delay from chip select
10
-
10
-
10
-
ns
t13w
IOW strobe width
20
-
20
-
15
-
ns
t13h
chip select hold time from IOW
0
-
0
-
0
-
ns
t14d
IOW delay from address
10
-
10
-
10
-
ns
t15d
write cycle delay
25
-
25
-
20
-
ns
t16s
data set-up time
20
-
20
-
15
-
ns
t16h
data hold time
15
-
5
-
5
-
ns
t17d
delay from IOW to output
25 pF load
-
100
-
33
-
29
ns
t18d
delay to set interrupt from Modem
input
25 pF load
-
100
-
24
-
23
ns
t19d
delay to reset interrupt from IOR
25 pF load
-
100
-
24
-
23
ns
t20d
delay from stop to set interrupt
-
1
-
1
-
1
Rclk
t21d
delay from IOR to reset interrupt
-
100
-
29
-
28
ns
t22d
delay from start to set interrupt
-
100
-
45
-
40
ns
t23d
delay from IOW to transmit start
8
24
8
24
8
24
Rclk
t24d
delay from IOW to reset interrupt
-
100
-
45
-
40
ns
t25d
delay from stop to set RXRDY
-
1
-
1
-
1
Rclk
t26d
delay from IOR to reset RXRDY
-
100
-
45
-
40
ns
t27d
delay from IOW to set TXRDY
-
100
-
45
-
40
ns
25 pF load
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9397 750 14451
Product data
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SC16C650B
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UART with 32-byte FIFOs and IrDA encoder/decoder
Table 28: AC electrical characteristics…continued
Tamb = −40 °C to +85 °C; VCC = 2.5 V, 3.3 V or 5 V ±10%, unless otherwise specified.
Symbol
Parameter
Conditions
2.5 V
3.3 V
Unit
Min
Max
Min
Max
Min
Max
8
-
8
Rclk
-
40
-
ns
t28d
delay from start to reset TXRDY
-
8
-
tRESET
Reset pulse width
100
-
40
N
baud rate divisor
1
216 − 1 1
[1]
[2]
5.0 V
216 − 1 1
216 − 1 Rclk
Applies to external clock, crystal oscillator max 24 MHz.
Applicable only when AS is tied LOW.
10.1 Timing diagrams
t4w
AS
t5s
t5h
VALID
ADDRESS
A0–A2
t6s
t6h
CS2
CS1–CS0
VALID
t7d
t7h
t7w
t8d
IOR, IOR
t9d
ACTIVE
t11d
t11d
DDIS
ACTIVE
t12d
D0–D7
t12h
DATA
002aaa331
Fig 9. General read timing when using AS signal.
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UART with 32-byte FIFOs and IrDA encoder/decoder
t4w
AS
t5s
t5h
VALID
ADDRESS
A0–A2
t6s
t6h
CS2
CS1–CS0
VALID
t13d
t13h
t13w
t14d
IOW, IOW
t15d
ACTIVE
t16s
D0–D7
t16h
DATA
002aaa332
Fig 10. General write timing when using AS signal.
VALID
ADDRESS
A0–A2
VALID
ADDRESS
t6s′
CS
t7h′
ACTIVE
t9d
ACTIVE
t12h
t12d
D0–D7
t7h′
t7w
ACTIVE
t7w
IOR
t6s′
t12d
t12h
DATA
002aaa333
Fig 11. General read timing when AS is tied to GND.
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UART with 32-byte FIFOs and IrDA encoder/decoder
VALID
ADDRESS
A0–A2
VALID
ADDRESS
t6s′
t7h′
t7h′
t6s′
ACTIVE
CS
ACTIVE
t13w
IOW
t15d
t13w
ACTIVE
t16s
D0–D7
t16h
t16s
t16h
DATA
002aaa334
Fig 12. General write timing when AS is tied to GND.
IOW
ACTIVE
t17d
RTS
DTR
CHANGE OF STATE
CHANGE OF STATE
DCD
CHANGE OF STATE
CTS
CHANGE OF STATE
DSR
t18d
INT
t18d
ACTIVE
ACTIVE
ACTIVE
t19d
IOR
ACTIVE
ACTIVE
ACTIVE
t18d
RI
CHANGE OF STATE
002aaa351
Fig 13. Modem input/output timing.
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UART with 32-byte FIFOs and IrDA encoder/decoder
t2w
t1w
EXTERNAL
CLOCK
002aaa112
t3w
Fig 14. External clock timing.
start
bit
RX
parity
bit
data bits (0 to 7)
D0
D1
D2
D3
D4
D5
D6
stop
bit
next
data
start
bit
D7
5 data bits
6 data bits
7 data bits
t20d
active
INT
t21d
active
IOR
16 baud rate clock
002aaa113
Fig 15. Receive timing.
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Philips Semiconductors
UART with 32-byte FIFOs and IrDA encoder/decoder
START
BIT
PARITY
BIT
STOP
BIT
NEXT
DATA
START
BIT
DATA BITS (5–8)
RX
D0
D1
D2
D3
D4
D5
D6
D7
t25d
ACTIVE
DATA
READY
RXRDY
t26d
ACTIVE
IOR
002aaa578
Fig 16. Receive ready timing in non-FIFO mode.
START
BIT
PARITY
BIT
STOP
BIT
DATA BITS (5–8)
RX
D0
D1
D2
D3
D4
D5
D6
D7
FIRST BYTE THAT
REACHES THE
TRIGGER LEVEL
t25d
ACTIVE
DATA
READY
RXRDY
t26d
ACTIVE
IOR
002aaa579
Fig 17. Receive ready timing in FIFO mode.
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Product data
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UART with 32-byte FIFOs and IrDA encoder/decoder
start
bit
TX
parity
bit
data bits (0 to 7)
D0
D1
D2
D3
D4
D5
D6
stop
bit
next
data
start
bit
D7
5 data bits
6 data bits
7 data bits
active
transmitter ready
INT
t22d
t24d
t23d
IOW
active
active
16 baud rate clock
002aaa116
Fig 18. Transmit timing.
START
BIT
PARITY
BIT
STOP
BIT
NEXT
DATA
START
BIT
DATA BITS (5-8)
TX
IOW
D0-D7
D0
D1
D2
D3
D4
D5
D6
D7
ACTIVE
BYTE #1
t28d
t27d
ACTIVE
TRANSMITTER READY
TXRDY
TRANSMITTER
NOT READY
002aaa580
Fig 19. Transmit ready timing in non-FIFO mode.
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Product data
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UART with 32-byte FIFOs and IrDA encoder/decoder
START
BIT
PARITY
BIT
STOP
BIT
DATA BITS (5-8)
TX
D0
D1
D2
D3
D4
D5
D6
D7
5 DATA BITS
6 DATA BITS
7 DATA BITS
IOW
ACTIVE
t28d
D0–D7
BYTE #16
t27d
TXRDY
FIFO FULL
002aaa581
Fig 20. Transmit ready timing in FIFO mode (DMA mode ‘1’).
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UART with 32-byte FIFOs and IrDA encoder/decoder
UART frame
start
data bits
0
TX data
1
0
1
0
stop
0
1
1
0
1
IrDA TX data
1/ bit time
2
bit
time
3/ bit time
16
002aaa212
Fig 21. Infrared transmit timing.
IrDA RX data
bit
time
RX data
0 to 1 16× clock delay
0
start
1
0
1
0
0
data bits
1
1
0
1
stop
UART frame
002aaa213
Fig 22. Infrared receive timing.
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Product data
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UART with 32-byte FIFOs and IrDA encoder/decoder
11. Package outline
PLCC44: plastic leaded chip carrier; 44 leads
SOT187-2
eD
eE
y
X
39
A
29
28
40
bp
ZE
b1
w M
44
1
E
HE
pin 1 index
A
A4 A1
e
(A 3)
6
β
18
Lp
k
7
detail X
17
e
v M A
ZD
D
B
HD
v M B
0
5
10 mm
scale
DIMENSIONS (mm dimensions are derived from the original inch dimensions)
A4
A1
e
UNIT A
A3
D(1) E(1)
eD
eE
HD
bp b1
max.
min.
4.57
4.19
mm
inches
0.81
0.66
HE
k
16.66 16.66
16.00 16.00 17.65 17.65 1.22
1.27
16.51 16.51
14.99 14.99 17.40 17.40 1.07
0.51
0.25
3.05
0.53
0.33
0.180
0.02
0.165
0.01
0.12
0.021 0.032 0.656 0.656
0.05
0.013 0.026 0.650 0.650
0.63
0.59
0.63
0.59
Lp
v
w
y
1.44
1.02
0.18
0.18
0.1
ZD(1) ZE(1)
max. max.
2.16
β
2.16
45 o
0.695 0.695 0.048 0.057
0.007 0.007 0.004 0.085 0.085
0.685 0.685 0.042 0.040
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT187-2
112E10
MS-018
EDR-7319
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
01-11-14
Fig 23. PLCC44 (SOT187-2).
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UART with 32-byte FIFOs and IrDA encoder/decoder
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
SOT313-2
c
y
X
36
25
A
37
24
ZE
e
E HE
A A2
(A 3)
A1
w M
θ
bp
pin 1 index
Lp
L
13
48
1
detail X
12
ZD
e
v M A
w M
bp
D
B
HD
v M B
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HD
HE
L
Lp
v
w
y
mm
1.6
0.20
0.05
1.45
1.35
0.25
0.27
0.17
0.18
0.12
7.1
6.9
7.1
6.9
0.5
9.15
8.85
9.15
8.85
1
0.75
0.45
0.2
0.12
0.1
Z D (1) Z E (1)
θ
0.95
0.55
7
o
0
0.95
0.55
o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT313-2
136E05
MS-026
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
00-01-19
03-02-25
Fig 24. LQFP48 (SOT313-2).
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Product data
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UART with 32-byte FIFOs and IrDA encoder/decoder
HVQFN32: plastic thermal enhanced very thin quad flat package; no leads;
32 terminals; body 5 x 5 x 0.85 mm
A
B
D
SOT617-1
terminal 1
index area
A
A1
E
c
detail X
C
e1
e
1/2 e
16
y
y1 C
v M C A B
w M C
b
9
L
17
8
e
e2
Eh
1/2 e
1
terminal 1
index area
24
32
25
X
Dh
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A(1)
max.
A1
b
c
D (1)
Dh
E (1)
Eh
e
e1
e2
L
v
w
y
y1
mm
1
0.05
0.00
0.30
0.18
0.2
5.1
4.9
3.25
2.95
5.1
4.9
3.25
2.95
0.5
3.5
3.5
0.5
0.3
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT617-1
---
MO-220
---
EUROPEAN
PROJECTION
ISSUE DATE
01-08-08
02-10-18
Fig 25. HVQFN32 (SOT617-1).
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UART with 32-byte FIFOs and IrDA encoder/decoder
seating plane
DIP40: plastic dual in-line package; 40 leads (600 mil)
SOT129-1
ME
D
A2
L
A
A1
c
e
Z
w M
b1
(e 1)
b
MH
21
40
pin 1 index
E
1
20
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
min.
A2
max.
b
b1
c
mm
4.7
0.51
4
1.70
1.14
0.53
0.38
0.36
0.23
52.5
51.5
inches
0.19
0.02
0.16
0.067
0.045
0.021
0.015
0.014
0.009
2.067
2.028
D
e
e1
L
ME
MH
w
Z (1)
max.
14.1
13.7
2.54
15.24
3.60
3.05
15.80
15.24
17.42
15.90
0.254
2.25
0.56
0.54
0.1
0.6
0.14
0.12
0.62
0.60
0.69
0.63
0.01
0.089
(1)
E
(1)
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT129-1
051G08
MO-015
SC-511-40
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-13
Fig 26. DIP40 (SOT129-1).
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UART with 32-byte FIFOs and IrDA encoder/decoder
12. Soldering
12.1 Introduction
This text gives a very brief insight to a complex technology. A more in-depth account
of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit
Packages (document order number 9398 652 90011).
There is no soldering method that is ideal for all IC packages. Wave soldering is often
preferred when through-hole and surface mount components are mixed on one
printed-circuit board. Wave soldering can still be used for certain surface mount ICs,
but it is not suitable for fine pitch SMDs. In these situations reflow soldering is
recommended. Driven by legislation and environmental forces the worldwide use of
lead-free solder pastes is increasing.
12.2 Through-hole mount packages
12.2.1
Soldering by dipping or by solder wave
Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 °C or
265 °C, depending on solder material applied, SnPb or Pb-free respectively.
The total contact time of successive solder waves must not exceed 5 seconds.
The device may be mounted up to the seating plane, but the temperature of the
plastic body must not exceed the specified maximum storage temperature (Tstg(max)).
If the printed-circuit board has been pre-heated, forced cooling may be necessary
immediately after soldering to keep the temperature within the permissible limit.
12.2.2
Manual soldering
Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the
seating plane or not more than 2 mm above it. If the temperature of the soldering iron
bit is less than 300 °C it may remain in contact for up to 10 seconds. If the bit
temperature is between 300 and 400 °C, contact may be up to 5 seconds.
12.3 Surface mount packages
12.3.1
Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and
binding agent) to be applied to the printed-circuit board by screen printing, stencilling
or pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example, convection or convection/infrared
heating in a conveyor type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending on heating method.
Typical reflow peak temperatures range from 215 to 270 °C depending on solder
paste material. The top-surface temperature of the packages should preferably be
kept:
• below 225 °C (SnPb process) or below 245 °C (Pb-free process)
– for all the BGA and SSOP-T packages
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UART with 32-byte FIFOs and IrDA encoder/decoder
– for packages with a thickness ≥ 2.5 mm
– for packages with a thickness < 2.5 mm and a volume ≥ 350 mm3 so called
thick/large packages.
• below 240 °C (SnPb process) or below 260 °C (Pb-free process) for packages with
a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages.
Moisture sensitivity precautions, as indicated on packing, must be respected at all
times.
12.3.2
Wave soldering
Conventional single wave soldering is not recommended for surface mount devices
(SMDs) or printed-circuit boards with a high component density, as solder bridging
and non-wetting can present major problems.
To overcome these problems the double-wave soldering method was specifically
developed.
If wave soldering is used the following conditions must be observed for optimal
results:
• Use a double-wave soldering method comprising a turbulent wave with high
upward pressure followed by a smooth laminar wave.
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be
parallel to the transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the
transport direction of the printed-circuit board.
The footprint must incorporate solder thieves at the downstream end.
• For packages with leads on four sides, the footprint must be placed at a 45° angle
to the transport direction of the printed-circuit board. The footprint must
incorporate solder thieves downstream and at the side corners.
During placement and before soldering, the package must be fixed with a droplet of
adhesive. The adhesive can be applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the adhesive is cured.
Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 °C or
265 °C, depending on solder material applied, SnPb or Pb-free respectively.
A mildly-activated flux will eliminate the need for removal of corrosive residues in
most applications.
12.3.3
Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low
voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time
must be limited to 10 seconds at up to 300 °C.
When using a dedicated tool, all other leads can be soldered in one operation within
2 to 5 seconds between 270 and 320 °C.
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9397 750 14451
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SC16C650B
Philips Semiconductors
UART with 32-byte FIFOs and IrDA encoder/decoder
12.4 Package related soldering information
Table 29:
Suitability of IC packages for wave, reflow and dipping soldering methods
Mounting
Package[1]
Wave
Reflow[2]
Dipping
−
suitable
Through-hole
mount
DBS, DIP, HDIP, RDBS,
SDIP, SIL
suitable[3]
Through-holesurface mount
PMFP[4]
not suitable
not
suitable
−
Surface mount
BGA, LBGA, LFBGA,
SQFP, SSOP-T[5],
TFBGA, VFBGA
not suitable
suitable
−
DHVQFN, HBCC, HBGA,
HLQFP, HSQFP, HSOP,
HTQFP, HTSSOP,
HVQFN, HVSON, SMS
not suitable[6]
suitable
−
PLCC[7], SO, SOJ
suitable
suitable
−
suitable
−
suitable
−
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
recommended[7][8]
LQFP, QFP, TQFP
not
SSOP, TSSOP, VSO,
VSSOP
not recommended[9]
For more detailed information on the BGA packages refer to the (LF)BGA Application Note
(AN01026); order a copy from your Philips Semiconductors sales office.
All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the
maximum temperature (with respect to time) and body size of the package, there is a risk that internal
or external package cracks may occur due to vaporization of the moisture in them (the so called
popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated
Circuit Packages; Section: Packing Methods.
For SDIP packages, the longitudinal axis must be parallel to the transport direction of the
printed-circuit board.
Hot bar soldering or manual soldering is suitable for PMFP packages.
These transparent plastic packages are extremely sensitive to reflow soldering conditions and must
on no account be processed through more than one soldering cycle or subjected to infrared reflow
soldering with peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow
oven. The package body peak temperature must be kept as low as possible.
These packages are not suitable for wave soldering. On versions with the heatsink on the bottom
side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with
the heatsink on the top side, the solder might be deposited on the heatsink surface.
If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave
direction. The package footprint must incorporate solder thieves downstream and at the side corners.
Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it
is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than
0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14451
Product data
Soldering method
Rev. 03 — 10 December 2004
48 of 51
SC16C650B
Philips Semiconductors
UART with 32-byte FIFOs and IrDA encoder/decoder
13. Revision history
Table 30:
Revision history
Rev Date
03
20041210
CPCN
Description
-
Product data (9397 750 14451)
Modifications:
•
There is no modification to the data sheet. However, reader is advised to refer to
AN10333 (Rev. 02) “SC16CXXXB baud rate deviation tolerance” (9397 750 14411)
that was released together with this revision.
02
20040603
-
Product data (9397 750 13317)
01
20040330
-
Product data (9397 750 11994)
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14451
Product data
Rev. 03 — 10 December 2004
49 of 51
SC16C650B
Philips Semiconductors
UART with 32-byte FIFOs and IrDA encoder/decoder
14. Data sheet status
Level
Data sheet status[1]
Product status[2][3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1]
Please consult the most recently issued data sheet before initiating or completing a design.
[2]
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
15. Definitions
16. Disclaimers
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Contact information
For additional information, please visit http://www.semiconductors.philips.com.
For sales office addresses, send e-mail to: [email protected].
Product data
Fax: +31 40 27 24825
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
9397 750 14451
Rev. 03 — 10 December 2004
50 of 51
SC16C650B
Philips Semiconductors
UART with 32-byte FIFOs and IrDA encoder/decoder
Contents
1
2
3
4
5
5.1
5.2
6
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
7
7.1
7.2
7.2.1
7.2.2
7.3
7.3.1
7.3.2
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
Functional description . . . . . . . . . . . . . . . . . . 10
Internal registers. . . . . . . . . . . . . . . . . . . . . . . 11
FIFO operation . . . . . . . . . . . . . . . . . . . . . . . . 11
Hardware flow control . . . . . . . . . . . . . . . . . . . 12
Software flow control . . . . . . . . . . . . . . . . . . . 12
Special feature software flow control . . . . . . . 13
Hardware/software and time-out interrupts. . . 13
Programmable baud rate generator . . . . . . . . 14
DMA operation . . . . . . . . . . . . . . . . . . . . . . . . 16
Sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Loop-back mode . . . . . . . . . . . . . . . . . . . . . . . 16
Register descriptions . . . . . . . . . . . . . . . . . . . 18
Transmit (THR) and Receive (RHR)
Holding Registers . . . . . . . . . . . . . . . . . . . . . 19
Interrupt Enable Register (IER) . . . . . . . . . . . 19
IER versus Receive FIFO interrupt
mode operation . . . . . . . . . . . . . . . . . . . . . . . 20
IER versus Receive/Transmit FIFO polled
mode operation . . . . . . . . . . . . . . . . . . . . . . . 20
FIFO Control Register (FCR) . . . . . . . . . . . . . 21
DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Interrupt Status Register (ISR) . . . . . . . . . . . . 23
Line Control Register (LCR) . . . . . . . . . . . . . . 24
Modem Control Register (MCR) . . . . . . . . . . . 25
Line Status Register (LSR) . . . . . . . . . . . . . . . 27
Modem Status Register (MSR). . . . . . . . . . . . 28
Scratchpad Register (SPR) . . . . . . . . . . . . . . 29
Enhanced Feature Register (EFR) . . . . . . . . . 29
SC16C650B external reset conditions . . . . . . 31
© Koninklijke Philips Electronics N.V. 2004.
Printed in the U.S.A.
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner.
The information presented in this document does not form part of any quotation or
contract, is believed to be accurate and reliable and may be changed without notice. No
liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.
Date of release: 10 December 2004
Document order number: 9397 750 14451
8
9
10
10.1
11
12
12.1
12.2
12.2.1
12.2.2
12.3
12.3.1
12.3.2
12.3.3
12.4
13
14
15
16
Limiting values . . . . . . . . . . . . . . . . . . . . . . . .
Static characteristics . . . . . . . . . . . . . . . . . . .
Dynamic characteristics . . . . . . . . . . . . . . . . .
Timing diagrams. . . . . . . . . . . . . . . . . . . . . . .
Package outline . . . . . . . . . . . . . . . . . . . . . . . .
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . .
Through-hole mount packages . . . . . . . . . . .
Soldering by dipping or by solder wave . . . . .
Manual soldering . . . . . . . . . . . . . . . . . . . . . .
Surface mount packages . . . . . . . . . . . . . . . .
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . .
Wave soldering. . . . . . . . . . . . . . . . . . . . . . . .
Manual soldering . . . . . . . . . . . . . . . . . . . . . .
Package related soldering information . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . .
Data sheet status. . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . .
31
32
33
34
42
46
46
46
46
46
46
46
47
47
48
49
50
50
50