PHILIPS SC16C652IB48

SC16C652
Dual UART with 32 bytes of transmit and receive FIFOs
Rev. 04 — 20 June 2003
Product data
1. Description
The SC16C652 is a 2 channel Universal Asynchronous Receiver and Transmitter
(UART) used for serial data communications. Its principal function is to convert
parallel data into serial data and vice versa. The UART can handle serial data rates
up to 5 Mbits/s. The SC16C652 is pin compatible with the SC16C2550. It will
power-up to be functionally equivalent to the 16C2450. The SC16C652 provides
enhanced UART functions with 32-byte FIFOs, modem control interface, DMA mode
data transfer. The DMA mode data transfer is controlled by the FIFO trigger levels
and the TXRDY and RXRDY signals. On-board status registers provide the user with
error indications and operational status. System interrupts and modem control
features may be tailored by software to meet specific user requirements. An internal
loop-back capability allows on-board diagnostics. Independent programmable baud
rate generators are provided to select transmit and receive baud rates.
The SC16C652 operates at 5 V, 3.3 V and 2.5 V and the Industrial temperature
range, and is available in a plastic LQFP48 package.
2. Features
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
2 channel UART
5 V, 3.3 V and 2.5 V operation
Industrial temperature range
Pin and functionally compatible to 16C2450 and software compatible with
SC16C650
Up to 5 Mbits/s data rate at 5 V and 3.3 V, and 3 Mbit/s at 2.5 V
32-byte transmit FIFO to reduce the bandwidth requirement of the external CPU
32-byte receive FIFO with error flags to reduce the bandwidth requirement of the
external CPU
Independent transmit and receive UART control
Four selectable Receive and Transmit FIFO interrupt trigger levels
Automatic software/hardware flow control
Programmable Xon/Xoff characters
Software selectable Baud Rate Generator
Sleep mode
Standard asynchronous error and framing bits (Start, Stop, and Parity Overrun
Break)
Transmit, Receive, Line Status, and Data Set interrupts independently controlled
SC16C652
Philips Semiconductors
Dual UART with 32 bytes of transmit and receive FIFOs
■ Fully programmable character formatting:
◆ 5-, 6-, 7-, or 8-bit characters
◆ Even-, Odd-, or No-Parity formats
◆ 1-, 11⁄2-, or 2-stop bit
◆ Baud generation (DC to 5 Mbit/s)
■ False start-bit detection
■ Complete status reporting capabilities
■ 3-State output TTL drive capabilities for bi-directional data bus and control bus
■ Line Break generation and detection
■ Internal diagnostic capabilities:
◆ Loop-back controls for communications link fault isolation
■ Prioritized interrupt system controls
■ Modem control functions (CTS, RTS, DSR, DTR, RI, CD).
3. Ordering information
Table 1:
Ordering information
Type number
SC16C652IB48
Package
Name
Description
Version
LQFP48
plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm
SOT313-2
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
9397 750 11634
Product data
Rev. 04 — 20 June 2003
2 of 41
SC16C652
Philips Semiconductors
Dual UART with 32 bytes of transmit and receive FIFOs
4. Block diagram
SC16C652
A0–A2
CSA
CSB
TRANSMIT
SHIFT
REGISTER
TXA, TXB
RECEIVE
FIFO
REGISTER
RECEIVE
SHIFT
REGISTER
RXA, RXB
DATA BUS
AND
CONTROL LOGIC
REGISTER
SELECT
LOGIC
INTERCONNECT BUS LINES
AND
CONTROL SIGNALS
D0–D7
IOR
IOW
RESET
TRANSMIT
FIFO
REGISTER
DTRA, DTRB
RTSA, RTSB
OP2A, OP2B
MODEM
CONTROL
LOGIC
INTA, INTB
TXRDYA, TXRDYB
RXRDYA, RXRDYB
INTERRUPT
CONTROL
LOGIC
CTSA, CTSB
RIA, RIB
CDA, CDB
DSRA, DSRB
CLOCK AND
BAUD RATE
GENERATOR
002aaa348
XTAL1
XTAL2
Fig 1. SC16C652 block diagram.
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9397 750 11634
Product data
Rev. 04 — 20 June 2003
3 of 41
SC16C652
Philips Semiconductors
Dual UART with 32 bytes of transmit and receive FIFOs
5. Pinning information
37 N.C.
38 CTSA
39 DSRA
40 CDA
41 RIA
42 VCC
43 TXRDYA
44 D0
45 D1
46 D2
47 D3
48 D4
5.1 Pinning
D5
1
36 RESET
D6
2
35 DTRB
D7
3
34 DTRA
RXB
4
33 RTSA
RXA
5
32 OP2A
TXRDYB
6
31 RXRDYA
SC16C652IB48
26 A2
N.C. 12
25 N.C.
N.C. 24
CSB 11
CTSB 23
27 A1
RTSB 22
CSA 10
RIB 21
28 A0
DSRB 20
9
IOR 19
OP2B
RXRDYB 18
29 INTB
GND 17
8
CDB 16
TXB
IOW 15
30 INTA
XTAL2 14
7
XTAL1 13
TXA
002aaa349
Fig 2. LQFP48 pin configuration.
5.2 Pin description
Table 2:
Pin description
Symbol
Pin
Type
Description
LQFP48
A0
28
I
Address 0 select bit. Internal register address selection.
A1
27
I
Address 1 select bit. Internal register address selection.
A2
26
I
Address 2 select bit. Internal register address selection.
CSA, CSB
10, 11
I
Chip Select A, B (Active-LOW). This function is associated with individual channels, A
through B. These pins enable data transfers between the user CPU and the SC16C652
for the channel(s) addressed. Individual UART sections (A, B) are addressed by providing
a logic 0 on the respective CSA, CSB pin.
D0-D7
44-48, 1-3 I/O
Data bus (bi-directional). These pins are the 8-bit, 3-State data bus for transferring
information to or from the controlling CPU. D0 is the least significant bit and the first data
bit in a transmit or receive serial data stream.
GND
17
Signal and power ground.
I
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9397 750 11634
Product data
Rev. 04 — 20 June 2003
4 of 41
SC16C652
Philips Semiconductors
Dual UART with 32 bytes of transmit and receive FIFOs
Table 2:
Pin description…continued
Symbol
Pin
Type
Description
LQFP48
INTA, INTB
30, 29
O
Interrupt A, B (3-State). This function is associated with individual channel interrupts,
INTA, INTB. INTA, INTB are enabled when MCR bit 3 is set to a logic 1, interrupts are
enabled in the interrupt enable register (IER), and is active when an interrupt condition
exists. Interrupt conditions include: receiver errors, available receiver buffer data, transmit
buffer empty, or when a modem status flag is detected.
IOR
19
I
Read strobe (Active-LOW strobe). A logic 0 transition on this pin will load the contents
of an internal register defined by address bits A0-A2 onto the SC16C652 data bus
(D0-D7) for access by external CPU.
IOW
15
I
Write strobe (Active-LOW strobe). A logic 0 transition on this pin will transfer the
contents of the data bus (D0-D7) from the external CPU to an internal register that is
defined by address bits A0-A2.
OP2A,
OP2B
32, 9
O
Output 2 (user-defined). This function is associated with individual channels, A through
B. The state at these pin(s) are defined by the user and through MCR register bit 3. INTA,
INTB are set to the active mode and OP2 to logic 0 when MCR[3] is set to a logic 1. INTA,
INTB are set to the 3-State mode and OP2 to a logic 1 when MCR[3] is set to a logic 0.
See bit 3, Modem Control Register (MCR[3]). Since these bits control both the INTA,
INTB operation and OP2 outputs, only one function should be used at one time, INT or
OP2.
RESET
36
I
Reset (Active-HIGH). A logic 1 on this pin will reset the internal registers and all the
outputs. The UART transmitter output and the receiver input will be disabled during reset
time. (See Section 7.11 “SC16C652 external reset condition” for initialization details.)
RXRDYA,
RXRDYB
31, 18
O
Receive Ready A, B (Active-LOW). This function provides the RX FIFO/RHR status for
individual receive channels (A-B). RXRDYn is primarily intended for monitoring DMA
mode 1 transfers for the receive data FIFOs. A logic 0 indicates there is a receive data to
read/upload, i.e., receive ready status with one or more RX characters available in the
FIFO/RHR. This pin is a logic 1 when the FIFO/RHR is empty or when the programmed
trigger level has not been reached. This signal can also be used for single mode transfers
(DMA mode 0).
TXRDYA,
TXRDYB
43, 6
O
Transmit Ready A, B (Active-LOW). These outputs provide the TX FIFO/THR status for
individual transmit channels (A-B). TXRDYn is primarily intended for monitoring DMA
mode 1 transfers for the transmit data FIFOs. An individual channel’s TXRDYA, TXRDYB
buffer ready status is indicated by logic 0, i.e., at lease one location is empty and
available in the FIFO or THR. This pin goes to a logic 1 (DMA mode 1) when there are no
more empty locations in the FIFO or THR. This signal can also be used for single mode
transfers (DMA mode 0).
VCC
42
I
Power supply input.
XTAL1
13
I
Crystal or external clock input. Functions as a crystal input or as an external clock
input. A crystal can be connected between this pin and XTAL2 to form an internal
oscillator circuit. This configuration requires an external 1 MΩ resistor between the
XTAL1 and XTAL2 pins. Alternatively, an external clock can be connected to this pin to
provide custom data rates. (See Section 6.8 “Programmable baud rate generator”.)
See Figure 3.
XTAL2
14
O
Output of the crystal oscillator or buffered clock. (See also XTAL1.) Crystal oscillator
output or buffered clock output. Should be left open if an external clock is connected to
XTAL1. For extended frequency operation, this pin should be tied to VCC via a 2 kΩ
resistor.
CDA, CDB
40, 16
I
Carrier Detect (Active-LOW). These inputs are associated with individual UART
channels A through B. A logic 0 on this pin indicates that a carrier has been detected by
the modem for that channel.
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
9397 750 11634
Product data
Rev. 04 — 20 June 2003
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SC16C652
Philips Semiconductors
Dual UART with 32 bytes of transmit and receive FIFOs
Table 2:
Pin description…continued
Symbol
Pin
Type
Description
LQFP48
CTSA,
CTSB
38, 23
I
Clear to Send (Active-LOW). These inputs are associated with individual UART
channels, A through B. A logic 0 on the CTS pin indicates the modem or data set is ready
to accept transmit data from the SC16C652. Status can be tested by reading MSR[4].
This pin has no effect on the UART’s transmit or receive operation.
DSRA,
DSRB
39, 20
I
Data Set Ready (Active-LOW). These inputs are associated with individual UART
channels, A through B. A logic 0 on this pin indicates the modem or data set is
powered-on and is ready for data exchange with the UART. This pin has no effect on the
UART’s transmit or receive operation.
DTRA,
DTRB
34, 35
O
Data Terminal Ready (Active-LOW). These outputs are associated with individual UART
channels, A through B. A logic 0 on this pin indicates that the SC16C652 is powered-on
and ready. This pin can be controlled via the modem control register. Writing a logic 1 to
MCR[0] will set the DTR output to logic 0, enabling the modem. This pin will be a logic 1
after writing a logic 0 to MCR[0], or after a reset. This pin has no effect on the UART’s
transmit or receive operation.
RIA, RIB
41, 21
I
Ring Indicator (Active-LOW). These inputs are associated with individual UART
channels, A through B. A logic 0 on this pin indicates the modem has received a ringing
signal from the telephone line. A logic 1 transition on this input pin will generate an
interrupt.
RTSA,
RTSB
33, 22
O
Request to Send (Active-LOW). These outputs are associated with individual UART
channels, A through B. A logic 0 on the RTS pin indicates the transmitter has data ready
and waiting to send. Writing a logic 1 in the modem control register MCR[1] will set this
pin to a logic 0, indicating data is available. After a reset this pin will be set to a logic 1.
This pin has no effect on the UART’s transmit or receive operation.
RXA, RXB
5, 4
I
Receive data A, B. These inputs are associated with individual serial channel data to the
SC16C652 receive input circuits, A-B. The RX signal will be a logic 1 during reset, idle
(no data), or when the transmitter is disabled. During the local loop-back mode, the RX
input pin is disabled and TX data is connected to the UART RX input, internally.
TXA, TXB
7, 8
O
Transmit data A, B. These outputs are associated with individual serial transmit channel
data from the SC16C652. The TX signal will be a logic 1 during reset, idle (no data), or
when the transmitter is disabled. During the local loop-back mode, the TX output pin is
disabled and TX data is internally connected to the UART RX input.
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
9397 750 11634
Product data
Rev. 04 — 20 June 2003
6 of 41
SC16C652
Philips Semiconductors
Dual UART with 32 bytes of transmit and receive FIFOs
6. Functional description
The SC16C652 provides serial asynchronous receive data synchronization,
parallel-to-serial and serial-to-parallel data conversions for both the transmitter and
receiver sections. These functions are necessary for converting the serial data
stream into parallel data that is required with digital data systems. Synchronization for
the serial data stream is accomplished by adding start and stop bits to the transmit
data to form a data character (character orientated protocol). Data integrity is insured
by attaching a parity bit to the data character. The parity bit is checked by the receiver
for any transmission bit errors. The electronic circuitry to provide all these functions is
fairly complex, especially when manufactured on a single integrated silicon chip. The
SC16C652 represents such an integration with greatly enhanced features. The
SC16C652 is fabricated with an advanced CMOS process.
The SC16C652 is an upward solution that provides a dual UART capability with
32 bytes of transmit and receive FIFO memory, instead of 16 bytes for the 16C2550
and none in the 16C2450. The SC16C652 is designed to work with high speed
modems and shared network environments that require fast data processing time.
Increased performance is realized in the SC16C652 by the transmit and receive
FIFOs. This allows the external processor to handle more networking tasks within a
given time. In addition, the four selectable receive and transmit FIFO trigger interrupt
levels are uniquely provided for maximum data throughput performance especially
when operating in a multi-channel environment. The FIFO memory greatly reduces
the bandwidth requirement of the external controlling CPU, increases performance,
and reduces power consumption.
The SC16C652 is capable of operation up to 5 Mbits/s with a 24 MHz clock. With a
crystal or external clock input of 7.3728 MHz, the user can select data rates up to
460.8 kbits/s.
The rich feature set of the SC16C652 is available through internal registers.
Selectable receive and transmit FIFO trigger levels, selectable TX and RX baud rates,
and modem interface controls are all standard features. Following a power-on reset or
an external reset, the SC16C652 is software compatible with the previous generation,
SC16C2550 and ST16C2450.
6.1 UART A-B functions
The UART provides the user with the capability to bi-directionally transfer information
between an external CPU, the SC16C652 package, and an external serial device. A
logic 0 on chip select pins CSA and/or CSB allows the user to configure, send data,
and/or receive data via UART channels A-B. Individual channel select functions are
shown in Table 3.
Table 3:
Serial port selection
Chip Select
Function
CSA-CSB = 1
none
CSA = 0
UART channel A
CSB = 0
UART channel B
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9397 750 11634
Product data
Rev. 04 — 20 June 2003
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SC16C652
Philips Semiconductors
Dual UART with 32 bytes of transmit and receive FIFOs
6.2 Internal registers
The SC16C652 provides two sets of internal registers (A and B) consisting of
12 registers each for monitoring and controlling the functions of each channel of the
UART. These registers are shown in Table 4. The UART registers function as data
holding registers (THR/RHR), interrupt status and control registers (IER/ISR), a FIFO
control register (FCR), line status and control registers (LCR/LSR), modem status
and control registers (MCR/MSR), programmable data rate (clock) control registers
(DLL/DLM), and a user accessible scratchpad register (SPR).
Table 4:
A2
Internal registers decoding
A1
A0
READ mode
WRITE mode
General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LSR, SPR)[1]
0
0
0
Receive Holding Register
Transmit Holding Register
0
0
1
0
1
0
0
1
1
Line Control Register
1
0
0
Modem Control Register
1
0
1
Line Status Register
n/a
1
1
0
Modem Status Register
n/a
1
1
1
Scratchpad Register
Scratchpad Register
Interrupt Enable Register
Interrupt Status Register
FIFO Control Register
Baud rate register set
(DLL/DLM)[2]
0
0
0
LSB of Divisor Latch
LSB of Divisor Latch
0
0
1
MSB of Divisor Latch
MSB of Divisor Latch
Enhanced register set (EFR, Xon/off
1-2)[3]
0
1
0
Enhanced Feature Register
Enhanced Feature Register
1
0
0
Xon1 word
Xon1 word
1
0
1
Xon2 word
Xon2 word
1
1
0
Xoff1 word
Xoff1 word
1
1
1
Xoff2 word
Xoff2 word
[1]
[2]
[3]
These registers are accessible only when LCR[7] is a logic 0.
These registers are accessible only when LCR[7] is a logic 1.
Enhanced Feature Register, Xon1, 2 and Xoff1, 2 are accessible only when the LCR is set to
‘BF(HEX)’.
6.3 FIFO operation
The 32-byte transmit and receive data FIFOs are enabled by the FIFO Control
Register bit-0 (FCR[0]). With 16C2550 devices, the user can set the receive trigger
level, but not the transmit trigger level. The SC16C652 provides independent trigger
levels for both receiver and transmitter. To remain compatible with SC16C2550, the
transmit interrupt trigger level is set to 16 following a reset. It should be noted that the
user can set the transmit trigger levels by writing to the FCR register, but activation
will not take place until EFR[4] is set to a logic 1. The receiver FIFO section includes
a time-out function to ensure data is delivered to the external CPU. An interrupt is
generated whenever the Receive Holding Register (RHR) has not been read
following the loading of a character or the receive trigger level has not been reached.
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9397 750 11634
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SC16C652
Philips Semiconductors
Dual UART with 32 bytes of transmit and receive FIFOs
Table 5:
Flow control mechanism
Selected trigger level
(characters)
INT pin activation
Negate RTS or
send Xoff
Assert RTS or
send Xon
8
8
16
0
16
16
24
7
24
24
28
15
28
28
28
23
6.4 Hardware flow control
When automatic hardware flow control is enabled, the SC16C652 monitors the CTS
pin for a remote buffer overflow indication and controls the RTS pin for local buffer
overflows. Automatic hardware flow control is selected by setting EFR[6] (RTS) and
EFR[7] (CTS) to a logic 1. If CTS transitions from a logic 0 to a logic 1 indicating a
flow control request, ISR[5] will be set to a logic 1 (if enabled via IER[6,7]), and the
SC16C652 will suspend TX transmissions as soon as the stop bit of the character in
process is shifted out. Transmission is resumed after the CTS input returns to a
logic 0, indicating more data may be sent.
With the Auto-RTS function enabled, an interrupt is generated when the receive FIFO
reaches the programmed trigger level. The RTS pin will not be forced to a logic 1
(RTS off), until the receive FIFO reaches the next trigger level. However, the RTS pin
will return to a logic 0 after the data buffer (FIFO) is unloaded to the next trigger level
below the programmed trigger level. However, under the above described conditions,
the SC16C652 will continue to accept data until the receive FIFO is full.
6.5 Software flow control
When software flow control is enabled, the SC16C652 compares one or two
sequential receive data characters with the programmed Xon or Xoff character
value(s). If received character(s) match the programmed Xoff values, the SC16C652
will halt transmission (TX) as soon as the current character(s) has completed
transmission. When a match occurs, the receive ready (if enabled via Xoff IER[5])
flags will be set and the interrupt output pin (if receive interrupt is enabled) will be
activated. Following a suspension due to a match of the Xoff characters’ values, the
SC16C652 will monitor the receive data stream for a match to the Xon1,2 character
value(s). If a match is found, the SC16C652 will resume operation and clear the flags
(ISR[4]).
Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic 0.
Following reset, the user can write any Xon/Xoff value desired for software flow
control. Different conditions can be set to detect Xon/Xoff characters and
suspend/resume transmissions. When double 8-bit Xon/Xoff characters are selected,
the SC16C652 compares two consecutive receive characters with two software flow
control 8-bit values (Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions
accordingly. Under the above described flow control mechanisms, flow control
characters are not placed (stacked) in the user accessible RX data buffer or FIFO.
When using a software flow control the Xon/Xoff characters cannot be used for data
transfer.
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
9397 750 11634
Product data
Rev. 04 — 20 June 2003
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SC16C652
Philips Semiconductors
Dual UART with 32 bytes of transmit and receive FIFOs
In the event that the receive buffer is overfilling and flow control needs to be executed,
the SC16C652 automatically sends an Xoff message (when enabled) via the serial
TX output to the remote modem. The SC16C652 sends the Xoff1,2 characters as
soon as received data passes the programmed trigger level. To clear this condition,
the SC16C652 will transmit the programmed Xon1,2 characters as soon as receive
data drops below the programmed trigger level.
6.6 Special feature software flow control
A special feature is provided to detect an 8-bit character when EFR[5] is set. When
8-bit character is detected, it will be placed on the user-accessible data stack along
with normal incoming RX data. This condition is selected in conjunction with
EFR[0-3]. Note that software flow control should be turned off when using this special
mode by setting EFR[0-3] to a logic 0.
The SC16C652 compares each incoming receive character with Xoff2 data. If a
match exists, the received data will be transferred to the FIFO, and ISR[4] will be set
to indicate detection of a special character. Although the Internal Register Table
(Table 9) shows each X-Register with eight bits of character information, the actual
number of bits is dependent on the programmed word length. Line Control Register
bits LCR[0-1] define the number of character bits, i.e., either 5 bits, 6 bits, 7 bits or
8 bits. The word length selected by LCR[0-1] also determine the number of bits that
will be used for the special character comparison. Bit 0 in the X-registers corresponds
with the LSB bit for the receive character.
6.7 Hardware/software and time-out interrupts
The interrupts are enabled by IER[0-3]. Care must be taken when handling these
interrupts. Following a reset, if Interrupt Enable Register (IER) bit 1 = 1, the
SC16C652 will issue a Transmit Holding Register interrupt. This interrupt must be
serviced prior to continuing operations. The LSR register provides the current
singular highest priority interrupt only. It could be noted that CTS and RTS interrupts
have lowest interrupt priority. A condition can exist where a higher priority interrupt
may mask the lower priority CTS/RTS interrupt(s). Only after servicing the higher
pending interrupt will the lower priority CTS/RTS interrupt(s) be reflected in the status
register. Servicing the interrupt without investigating further interrupt conditions can
result in data errors.
When two interrupt conditions have the same priority, it is important to service these
interrupts correctly. Receive Data Ready and Receive Time Out have the same
interrupt priority (when enabled by IER[3]). The receiver issues an interrupt after the
number of characters have reached the programmed trigger level. In this case, the
SC16C652 FIFO may hold more characters than the programmed trigger level.
Following the removal of a data byte, the user should re-check LSR[0] for additional
characters. A Receive Time Out will not occur if the receive FIFO is empty. The
time-out counter is reset at the center of each stop bit received or each time the
receive holding register (RHR) is read. The actual time-out value is 4 character time,
including data information length, start bit, parity bit, and the size of stop bit, i.e., 1×,
1.5×, or 2× bit times.
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9397 750 11634
Product data
Rev. 04 — 20 June 2003
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SC16C652
Philips Semiconductors
Dual UART with 32 bytes of transmit and receive FIFOs
6.8 Programmable baud rate generator
The SC16C652 supports high speed modem technologies that have increased input
data rates by employing data compression schemes. For example, a 33.6 kbit/s
modem that employs data compression may require a 115.2 kbit/s input data rate.
A 128.0 kbit/s ISDN modem that supports data compression may need an input
data rate of 460.8 kbit/s. The SC16C652 can support a standard data rate of
921.6 kbit/s.
A single baud rate generator is provided for the transmitter and receiver, allowing
independent TX/RX channel control. The programmable Baud Rate Generator is
capable of operating with a frequency of up to 80 MHz. To obtain maximum data rate,
it is necessary to use full rail swing on the clock input. The SC16C652 can be
configured for internal or external clock operation. For internal clock oscillator
operation, an industry standard microprocessor crystal is connected externally
between the XTAL1 and XTAL2 pins. Alternatively, an external clock can be
connected to the XTAL1 pin to clock the internal baud rate generator for standard or
custom rates (see Table 6).
The generator divides the input 16× clock by any divisor from 1 to 216 − 1. The
SC16C652 divides the basic external clock by 16. The basic 16× clock provides table
rates to support standard and custom applications using the same system design.
The rate table is configured via the DLL and DLM internal register functions.
Customized Baud Rates can be achieved by selecting the proper divisor values for
the MSB and LSB sections of baud rate generator.
X1
1.8432 MHz
C1
47 pF
XTAL2
XTAL1
XTAL2
XTAL1
Programming the Baud Rate Generator Registers DLM (MSB) and DLL (LSB)
provides a user capability for selecting the desired final baud rate. The example in
Table 6 shows the selectable baud rate table available when using a 1.8432 MHz
external clock input.
X1
1.8432 MHz
C2
100 pF
C1
22 pF
1.5 kΩ
C2
47 pF
002aaa169
Fig 3. Crystal oscillator connection.
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
9397 750 11634
Product data
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SC16C652
Philips Semiconductors
Dual UART with 32 bytes of transmit and receive FIFOs
Table 6:
Baud rate generator programming table using a 1.8432 MHz clock
Output
baud rate
Output
16× clock divisor
(decimal)
Output
16× clock divisor
(HEX)
DLM
program value
(HEX)
DLL
program value
(HEX)
50
2304
900
09
00
75
1536
600
06
00
110
1047
417
04
17
150
768
300
03
00
300
384
180
01
80
600
192
C0
00
C0
1200
96
60
00
60
2400
48
30
00
30
3600
32
20
00
20
4800
24
18
00
18
7200
16
10
00
10
9600
12
0C
00
0C
19.2 k
6
06
00
06
38.4 k
3
03
00
03
57.6 k
2
02
00
02
115.2 k
1
01
00
01
6.9 DMA operation
The SC16C652 FIFO trigger level provides additional flexibility to the user for block
mode operation. The user can optionally operate the transmit and receive FIFOs in
the DMA mode (FCR[3]). The DMA mode affects the state of the RXRDY and TXRDY
output pins. Tables 7 and 8 show this.
Table 7:
Effect of DMA mode on state of RXRDY pin
Non-DMA mode
DMA mode
1 = FIFO empty
0-to-1 transition when FIFO empties
0 = at least 1 byte in FIFO
1-to-0 transition when FIFO reaches trigger level,
or time-out occurs
Table 8:
Effect of DMA mode on state of TXRDY pin
Non-DMA mode
DMA mode
1 = at least 1 byte in FIFO
0-to-1 transition when FIFO becomes full
0 = FIFO empty
1-to-0 transition when FIFO goes below trigger level
6.10 Loop-back mode
The internal loop-back capability allows on-board diagnostics. In the loop-back mode,
the normal modem interface pins are disconnected and reconfigured for loop-back
internally (see Figure 4). MCR[0-3] register bits are used for controlling loop-back
diagnostic testing. In the loop-back mode, the transmitter output (TX) and the receiver
input (RX) are disconnected from their associated interface pins, and instead are
connected together internally. The CTS, DSR, CD, and RI are disconnected from
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SC16C652
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Dual UART with 32 bytes of transmit and receive FIFOs
their normal modem control inputs pins, and instead are connected internally to RTS,
DTR, MCR[3] (OP2) and MCR[2] (OP1). Loop-back test data is entered into the
transmit holding register via the user data bus interface, D0-D7. The transmit UART
serializes the data and passes the serial data to the receive UART via the internal
loop-back connection. The receive UART converts the serial data back into parallel
data that is then made available at the user data interface D0-D7. The user optionally
compares the received data to the initial transmitted data for verifying error-free
operation of the UART TX/RX circuits.
In this mode, the receiver and transmitter interrupts are fully operational. The Modem
Control Interrupts are also operational.
SC16C652
TRANSMIT
FIFO
REGISTER
D0–D7
IOR
IOW
RESET
TRANSMIT
SHIFT
REGISTER
TXA, TXB
DATA BUS
AND
CONTROL LOGIC
A0–A2
CSA, CSB
REGISTER
SELECT
LOGIC
INTERCONNECT BUS LINES
AND
CONTROL SIGNALS
MCR[4] = 1
RECEIVE
FIFO
REGISTER
RECEIVE
SHIFT
REGISTER
RXA, RXB
RTSA, RTSB
CTSA, CTSB
DTRA, DTRB
MODEM
CONTROL
LOGIC
DSRA, DSRB
(OP1A, OP1B)
INTA, INTB
TXRDYA, TXRDYB
RXRDYA, RXRDYB
INTERRUPT
CONTROL
LOGIC
RIA, RIB
CLOCK AND
BAUD RATE
GENERATOR
(OP2A, OP2B)
CDA, CDB
002aaa350
XTAL1
XTAL2
Fig 4. Internal loop-back mode diagram.
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Dual UART with 32 bytes of transmit and receive FIFOs
7. Register descriptions
Table 9 details the assigned bit functions for the SC16C652 internal registers. The
assigned bit functions are more fully defined in Section 7.1 through Section 7.11.
Table 9:
SC16C652 internal registers
Shaded bits are only accessible when EFR[4] is set.
A2
A1
A0
Register Default[1] Bit 7
General Register
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Set[2]
0
0
0
RHR
XX
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0
0
0
THR
XX
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0
0
1
IER
00
CTS
interrupt
RTS
interrupt
Xoff
interrupt
Sleep
mode
modem
status
interrupt
Rx
receive
line
status
interrupt
transmit
holding
register
interrupt
receive
holding
register
0
1
0
FCR
00
RCVR
trigger
(MSB)
RCVR
trigger
(LSB)
TX
trigger
(MSB)
TX
trigger
(LSB)
DMA
mode
select
XMIT
FIFO
reset
RCVR
FIFO
reset
FIFOs
enable
0
1
0
ISR
01
FIFOs
enabled
FIFOs
enabled
INT
priority
bit 4
INT
priority
bit 3
INT
priority
bit 2
INT
priority
bit 1
INT
priority
bit 0
INT
status
0
1
1
LCR
00
divisor
latch
enable
set break set parity even
parity
parity
enable
stop bits word
length
bit 1
1
0
0
MCR
00
clock
select
0
1
0
1
LSR
60
FIFO
data
error
1
1
0
MSR
X0
1
1
1
SPR
Special Register
0
word
length
bit 0
loop back OP2/INT (OP1)
enable
RTS
DTR
THR and THR
TSR
empty
empty
break
interrupt
framing
error
parity
error
overrun
error
receive
data
ready
CD
RI
DSR
CTS
∆CD
∆RI
∆DSR
∆CTS
FF
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
XX
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
XX
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Set[3]
0
0
0
DLL
0
0
1
DLM
Enhanced Register
Set[4]
0
1
0
EFR
00
Auto
CTS
Auto
RTS
Special
char.
select
Enable
Cont-3
IER[4-7], Tx, Rx
ISR[4,5], Control
FCR[4,5],
MCR[5-7]
Cont-2
Tx, Rx
Control
Cont-1
Tx, Rx
Control
Cont-0
Tx, Rx
Control
1
0
0
Xon-1
00
bit 7
bit 6
bit 5
bit 4
bit 2
bit 1
bit 0
1
0
1
Xon-2
00
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
1
1
0
Xoff-1
00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
1
1
1
Xoff-2
00
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
[1]
[2]
[3]
[4]
bit 3
The value shown in represents the register’s initialized HEX value; X = n/a.
Accessible only when LCR[7] is logic 0.
Baud rate registers accessible only when LCR[7] is logic 1.
Enhanced Feature Register, Xon-1,2 and Xoff-1,2 are accessible only when LCR is set to ‘BFHex’.
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Dual UART with 32 bytes of transmit and receive FIFOs
7.1 Transmit (THR) and Receive (RHR) Holding Registers
The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and
Transmit Shift Register (TSR). The status of the THR is provided in the Line Status
Register (LSR). Writing to the THR transfers the contents of the data bus (D7-D0) to
the TSR and UART via the THR, providing that the THR is empty. The THR empty
flag in the LSR register will be set to a logic 1 when the transmitter is empty or when
data is transferred to the TSR. Note that a write operation can be performed when the
THR empty flag is set (logic 0 = at least one byte in FIFO/THR, logic 1 = FIFO/THR
empty).
The serial receive section also contains an 8-bit Receive Holding Register (RHR) and
a Receive Serial Shift Register (RSR). Receive data is removed from the SC16C652
and receive FIFO by reading the RHR register. The receive section provides a
mechanism to prevent false starts. On the falling edge of a start or false start bit, an
internal receiver counter starts counting clocks at the 16× clock rate. After 7-1⁄2
clocks, the start bit time should be shifted to the center of the start bit. At this time the
start bit is sampled, and if it is still a logic 0 it is validated. Evaluating the start bit in
this manner prevents the receiver from assembling a false character. Receiver status
codes will be posted in the LSR.
7.2 Interrupt Enable Register (IER)
The Interrupt Enable Register (IER) masks the interrupts from receiver ready,
transmitter empty, line status and modem status registers. These interrupts would
normally be seen on the INTA, INTB output pins.
Table 10:
Interrupt Enable Register bits description
Bit
Symbol
Description
7
IER[7]
CTS interrupt.
Logic 0 = Disable the CTS interrupt (normal default condition).
Logic 1 = Enable the CTS interrupt. The SC16C652 issues an
interrupt when the CTS pin transitions from a logic 0 to a logic 1.
6
IER[6]
RTS interrupt.
Logic 0 = Disable the RTS interrupt (normal default condition).
Logic 1 = Enable the RTS interrupt. The SC16C652 issues an
interrupt when the RTS pin transitions from a logic 0 to a logic 1.
5
IER[5]
Xoff interrupt.
Logic 0 = Disable the software flow control, receive Xoff interrupt
(normal default condition).
Logic 1 = Enable the software flow control, receive Xoff
interrupt.
4
IER[4]
Sleep mode.
Logic 0 = Disable sleep mode (normal default condition).
Logic 1 = Enable sleep mode.
3
IER[3]
Modem Status Interrupt. This interrupt will be issued whenever
there is a modem status change as reflected in MSR[0-3].
Logic 0 = Disable the modem status register interrupt (normal
default condition).
Logic 1 = Enable the modem status register interrupt.
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Dual UART with 32 bytes of transmit and receive FIFOs
Table 10:
Interrupt Enable Register bits description…continued
Bit
Symbol
Description
2
IER[2]
Receive Line Status interrupt. This interrupt will be issued
whenever a receive data error condition exists as reflected in
LSR[1-4].
Logic 0 = Disable the receiver line status interrupt (normal
default condition).
Logic 1 = Enable the receiver line status interrupt.
1
IER[1]
Transmit Holding Register interrupt. In the 16C450 mode, this
interrupt will be issued whenever the THR is empty, and is
associated with LSR[5]. In the FIFO modes, this interrupt will be
issued whenever the FIFO is empty.
Logic 0 = Disable the Transmit Holding Register Empty (TXRDY)
interrupt (normal default condition).
Logic 1 = Enable the TXRDY (ISR level 3) interrupt.
0
IER[0]
Receive Holding Register. In the 16C450 mode, this interrupt will
be issued when the RHR has data, or is cleared when the RHR is
empty. In the FIFO mode, this interrupt will be issued when the
FIFO has reached the programmed trigger level or is cleared when
the FIFO drops below the trigger level.
Logic 0 = Disable the receiver ready (ISR level 2, RXRDY)
interrupt (normal default condition).
Logic 1 = Enable the RXRDY (ISR level 2) interrupt.
7.2.1
IER versus Transmit/Receive FIFO interrupt mode operation
When the receive FIFO (FCR[0] = logic 1), and receive interrupts (IER[0] = logic 1)
are enabled, the receive interrupts and register status will reflect the following:
• The receive RXRDY interrupt (Level 2 ISR interrupt) is issued to the external CPU
when the receive FIFO has reached the programmed trigger level. It will be cleared
when the receive FIFO drops below the programmed trigger level.
• Receive FIFO status will also be reflected in the user accessible ISR register when
the receive FIFO trigger level is reached. Both the ISR register receive status bit
and the interrupt will be cleared when the FIFO drops below the trigger level.
• The receive data ready bit (LSR[0]) is set as soon as a character is transferred
from the shift register (RSR) to the receive FIFO. It is reset when the FIFO is
empty.
• When the Transmit FIFO and interrupts are enabled, an interrupt is generated
when the transmit FIFO is empty due to the unloading of the data by the TSR and
UART for transmission via the transmission media. The interrupt is cleared either
by reading the ISR register, or by loading the THR with new data characters.
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Dual UART with 32 bytes of transmit and receive FIFOs
7.2.2
IER versus Receive/Transmit FIFO polled mode operation
When FCR[0] = logic 1, resetting IER[0-3] enables the SC16C652 in the FIFO polled
mode of operation. In this mode, interrupts are not generated and the user must poll
the LSR register for TX and/or RX data status. Since the receiver and transmitter
have separate bits in the LSR either or both can be used in the polled mode by
selecting respective transmit or receive control bit(s).
•
•
•
•
LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO.
LSR[1-4] will provide the type of receive errors, or a receive break, if encountered.
LSR[5] will indicate when the transmit FIFO is empty.
LSR[6] will indicate when both the transmit FIFO and transmit shift register are
empty.
• LSR[7] will show if any FIFO data errors occurred.
7.3 FIFO Control Register (FCR)
This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO
trigger levels, and select the DMA mode.
7.3.1
DMA mode
Mode 0 (FCR bit 3 = 0): Set and enable the interrupt for each single transmit or
receive operation, and is similar to the 16C450 mode. Transmit Ready (TXRDY) will
go to a logic 0 whenever the FIFO (THR, if FIFO is not enabled) is empty. Receive
Ready (RXRDY) will go to a logic 0 whenever the Receive Holding Register (RHR) is
loaded with a character.
Mode 1 (FCR bit 3 = 1): Set and enable the interrupt in a block mode operation. The
transmit interrupt is set when the transmit FIFO is below the programmed trigger
level. The receive interrupt is set when the receive FIFO fills to the programmed
trigger level. However, the FIFO continues to fill regardless of the programmed level
until the FIFO is full. RXRDY remains a logic 0 as long as the FIFO fill level is above
the programmed trigger level.
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Dual UART with 32 bytes of transmit and receive FIFOs
7.3.2
FIFO mode
Table 11:
FIFO Control Register bits description
Bit
Symbol
Description
7-6
FCR[7]
(MSB),
FCR[6]
(LSB)
RCVR trigger. These bits are used to set the trigger level for the receive
FIFO interrupt.
FCR[5]
(MSB),
FCR[4]
(LSB)
Logic 0 or cleared is the default condition; TX trigger level = 16.
FCR[3]
DMA mode select.
5-4
3
An interrupt is generated when the number of characters in the FIFO
equals the programmed trigger level. However, the FIFO will continue to
be loaded until it is full. Refer to Table 12.
These bits are used to set the trigger level for the transmit FIFO
interrupt. The SC16C652 will issue a transmit empty interrupt when the
number of characters in FIFO drops below the selected trigger level.
Refer to Table 13.
Logic 0 = Set DMA mode ‘0’ (normal default condition).
Logic 1 = Set DMA mode ‘1’
Transmit operation in mode ‘0’: When the SC16C652 is in the 16C450
mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO mode (FIFOs
enabled; FCR[0] = logic 1; FCR[3] = logic 0), and when there are no
characters in the transmit FIFO or transmit holding register, the TXRDY
pin will be a logic 0. Once active, the TXRDY pin will go to a logic 1 after
the first character is loaded into the transmit holding register.
Receive operation in mode ‘0’: When the SC16C652 is in 16C450
mode, or in the FIFO mode (FCR[0] = logic 1; FCR[3] = logic 0) and
there is at least one character in the receive FIFO, the RXRDY pin will
be a logic 0. Once active, the RXRDY pin will go to a logic 1 when there
are no more characters in the receiver.
Transmit operation in mode ‘1’: When the SC16C652 is in FIFO mode
(FCR[0] = logic 1; FCR[3] = logic 1), the TXRDY pin will be a logic 1
when the transmit FIFO is completely full. It will be a logic 0 when the
trigger level has been reached.
Receive operation in mode ‘1’: When the SC16C652 is in FIFO mode
(FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has been
reached, or a Receive Time-Out has occurred, the RXRDY pin will go to
a logic 0. Once activated, it will go to a logic 1 after there are no more
characters in the FIFO.
2
FCR[2]
XMIT FIFO reset.
Logic 0 = No FIFO transmit reset (normal default condition).
Logic 1 = Clears the contents of the transmit FIFO and resets the
FIFO counter logic (the transmit shift register is not cleared or
altered). This bit will return to a logic 0 after clearing the FIFO.
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Dual UART with 32 bytes of transmit and receive FIFOs
Table 11:
FIFO Control Register bits description…continued
Bit
Symbol
Description
1
FCR[1]
RCVR FIFO reset.
Logic 0 = No FIFO receive reset (normal default condition).
Logic 1 = Clears the contents of the receive FIFO and resets the FIFO
counter logic (the receive shift register is not cleared or altered). This
bit will return to a logic 0 after clearing the FIFO.
0
FCR[0]
FIFO enable.
Logic 0 = Disable the transmit and receive FIFO (normal default
condition).
Logic 1 = Enable the transmit and receive FIFO. This bit must be a
‘1’ when other FCR bits are written to, or they will not be
programmed.
Table 12:
RCVR trigger levels
FCR[7]
FCR[6]
RX FIFO trigger level (bytes)
0
0
8
0
1
16
1
0
24
1
1
28
Table 13:
TX FIFO trigger levels
FCR[5]
FCR[4]
TX FIFO trigger level (bytes)
0
0
16
0
1
8
1
0
24
1
1
30
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Dual UART with 32 bytes of transmit and receive FIFOs
7.4 Interrupt Status Register (ISR)
The SC16C652 provides six levels of prioritized interrupts to minimize external
software interaction. The Interrupt Status Register (ISR) provides the user with four
interrupt status bits. Performing a read cycle on the ISR will provide the user with the
highest pending interrupt level to be serviced. No other interrupts are acknowledged
until the pending interrupt is serviced. A lower level interrupt may be seen after
servicing the higher level interrupt and re-reading the interrupt status bits. Table 14
“Interrupt source” shows the data values (bits 0-3) for the four prioritized interrupt
levels and the interrupt sources associated with each of these interrupt levels.
Table 14:
Interrupt source
Priority
level
ISR[5]
ISR[4]
ISR[3]
ISR[2]
ISR[1]
ISR[0]
Source of the interrupt
1
0
0
0
1
1
0
LSR (Receiver Line Status
Register)
2
0
0
0
1
0
0
RXRDY (Received Data
Ready)
2
0
0
1
1
0
0
RXRDY (Receive Data
time-out)
3
0
0
0
0
1
0
TXRDY (Transmitter
Holding Register Empty)
4
0
0
0
0
0
0
MSR (Modem Status
Register)
5
0
1
0
0
0
0
RXRDY (Received Xoff
signal) / Special character
6
1
0
0
0
0
0
CTS, RTS change of state
Table 15:
Interrupt Status Register bits description
Bit
Symbol
Description
7-6
ISR[7-6]
FIFOs enabled. These bits are set to a logic 0 when the FIFOs are
not being used in the 16C450 mode. They are set to a logic 1
when the FIFOs are enabled in the SC16C652 mode.
Logic 0 or cleared = default condition.
5-4
ISR[5-4]
INT priority bits 4-3. These bits are enabled when EFR[4] is set to
a logic 1. ISR[4] indicates that matching Xoff character(s) have
been detected. ISR[5] indicates that CTS, RTS have been
generated. Note that once set to a logic 1, the ISR[4] bit will stay a
logic 1 until Xon character(s) are received.
Logic 0 or cleared = default condition.
3-1
ISR[3-1]
INT priority bits 2-0. These bits indicate the source for a pending
interrupt at interrupt priority levels 1, 2, and 3 (see Table 14).
Logic 0 or cleared = default condition.
0
ISR[0]
INT status.
Logic 0 = An interrupt is pending and the ISR contents may be
used as a pointer to the appropriate interrupt service routine.
Logic 1 = No interrupt pending (normal default condition).
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Dual UART with 32 bytes of transmit and receive FIFOs
7.5 Line Control Register (LCR)
The Line Control Register is used to specify the asynchronous data communication
format. The word length, the number of stop bits, and the parity are selected by
writing the appropriate bits in this register.
Table 16:
Line Control Register bits description
Bit
Symbol
Description
7
LCR[7]
Divisor latch enable. The internal baud rate counter latch and
Enhance Feature mode enable.
Logic 0 = Divisor latch disabled (normal default condition).
Logic 1 = Divisor latch enabled.
6
LCR[6]
Set break. When enabled, the Break control bit causes a break
condition to be transmitted (the TX output is forced to a logic 0
state). This condition exists until disabled by setting LCR[6] to a
logic 0.
Logic 0 = no TX break condition (normal default condition)
Logic 1 = forces the transmitter output (TX) to a logic 0 for
alerting the remote receiver to a line break condition.
5-3
LCR[5-3]
Programs the parity conditions (see Table 17).
2
LCR[2]
Stop bits. The length of stop bit is specified by this bit in
conjunction with the programmed word length (see Table 18).
Logic 0 or cleared = default condition.
1-0
LCR[1-0]
Word length bits 1, 0. These two bits specify the word length to be
transmitted or received (see Table 19).
Logic 0 or cleared = default condition.
Table 17:
LCR[5-3] parity selection
LCR[5]
LCR[4]
LCR[3]
Parity selection
X
X
0
no parity
X
0
1
ODD parity
0
1
1
EVEN parity
0
0
1
forced parity ‘1’
1
1
1
forced parity ‘0’
Table 18:
LCR[2] stop bit length
LCR[2]
Word length
Stop bit length (bit times)
0
5, 6, 7, 8
1
1
5
1-1⁄2
1
6, 7, 8
2
Table 19:
LCR[1-0] word length
LCR[1]
LCR[0]
Word length
0
0
5
0
1
6
1
0
7
1
1
8
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Dual UART with 32 bytes of transmit and receive FIFOs
7.6 Modem Control Register (MCR)
This register controls the interface with the modem or a peripheral device.
Table 20:
Modem Control Register bits description
Bit
Symbol
Description
7
MCR[7]
Clock select
Logic 0 = Divide by 1 clock input.
Logic 1 = Divide by 4 clock input.
6
MCR[6]
Reserved; set to ‘0’.
5
MCR[5]
Reserved; set to ‘0’.
4
MCR[4]
Loop-back. Enable the local loop-back mode (diagnostics). In this
mode the transmitter output (TX) and the receiver input (RX), CTS,
DSR, CD, and RI are disconnected from the SC16C652 I/O pins.
Internally the modem data and control pins are connected into a
loop-back data configuration (see Figure 4). In this mode, the receiver
and transmitter interrupts remain fully operational. The Modem
Control Interrupts are also operational, but the interrupts’ sources are
switched to the lower four bits of the Modem Control. Interrupts
continue to be controlled by the IER register.
Logic 0 = Disable loop-back mode (normal default condition).
Logic 1 = Enable local loop-back mode (diagnostics).
3
MCR[3]
OP2/INT enable
Logic 0 = Forces INT (A-B) outputs to the 3-State mode and sets
OP2 to a logic 1 (normal default condition).
Logic 1 = Forces the INT (A-B outputs to the active mode and sets
OP2 to a logic 0.
2
MCR[2]
(OP1). OP1A/OP1B are not available as an external signal in the
SC16C652. This bit is instead used in the Loop-back mode only. In
the loop-back mode, this bit is used to write the state of the modem RI
interface signal.
1
MCR[1]
RTS
Logic 0 = Force RTS output to a logic 1 (normal default condition).
Logic 1 = Force RTS output to a logic 0.
0
MCR[0]
DTR
Logic 0 = Force DTR output to a logic 1 (normal default condition).
Logic 1 = Force DTR output to a logic 0.
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9397 750 11634
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SC16C652
Philips Semiconductors
Dual UART with 32 bytes of transmit and receive FIFOs
7.7 Line Status Register (LSR)
This register provides the status of data transfers between the SC16C652 and
the CPU.
Table 21:
Line Status Register bits description
Bit
Symbol
Description
7
LSR[7]
FIFO data error.
Logic 0 = No error (normal default condition).
Logic 1 = At least one parity error, framing error or break
indication is in the current FIFO data. This bit is cleared when
there are no remaining error flags associated with the remaining
data in the FIFO.
6
LSR[6]
THR and TSR empty. This bit is the Transmit Empty indicator. This
bit is set to a logic 1 whenever the transmit holding register and the
transmit shift register are both empty. It is reset to logic 0 whenever
either the THR or TSR contains a data character. In the FIFO
mode, this bit is set to ‘1’ whenever the transmit FIFO and transmit
shift register are both empty.
5
LSR[5]
THR empty. This bit is the Transmit Holding Register Empty
indicator. This bit indicates that the UART is ready to accept a new
character for transmission. In addition, this bit causes the UART to
issue an interrupt to CPU when the THR interrupt enable is set.
The THR bit is set to a logic 1 when a character is transferred from
the transmit holding register into the transmitter shift register. The
bit is reset to a logic 0 concurrently with the loading of the
transmitter holding register by the CPU. In the FIFO mode, this bit
is set when the transmit FIFO is empty; it is cleared when at least
1 byte is written to the transmit FIFO.
4
LSR[4]
Break interrupt.
Logic 0 = No break condition (normal default condition).
Logic 1 = The receiver received a break signal (RX was a logic 0
for one character frame time). In the FIFO mode, only one break
character is loaded into the FIFO.
3
LSR[3]
Framing error.
Logic 0 = No framing error (normal default condition).
Logic 1 = Framing error. The receive character did not have a
valid stop bit(s). In the FIFO mode, this error is associated with
the character at the top of the FIFO.
2
LSR[2]
Parity error.
Logic 0 = No parity error (normal default condition.
Logic 1 = Parity error. The receive character does not have
correct parity information and is suspect. In the FIFO mode, this
error is associated with the character at the top of the FIFO.
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9397 750 11634
Product data
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SC16C652
Philips Semiconductors
Dual UART with 32 bytes of transmit and receive FIFOs
Table 21:
Line Status Register bits description…continued
Bit
Symbol
Description
1
LSR[1]
Overrun error.
Logic 0 = No overrun error (normal default condition).
Logic 1 = Overrun error. A data overrun error occurred in the
receive shift register. This happens when additional data arrives
while the FIFO is full. In this case, the previous data in the shift
register is overwritten. Note that under this condition, the data
byte in the receive shift register is not transferred into the FIFO,
therefore the data in the FIFO is not corrupted by the error.
0
LSR[0]
Receive data ready.
Logic 0 = No data in receive holding register or FIFO (normal
default condition).
Logic 1 = Data has been received and is saved in the receive
holding register or FIFO.
7.8 Modem Status Register (MSR)
This register provides the current state of the control interface signals from the
modem, or other peripheral device to which the SC16C652 is connected. Four bits of
this register are used to indicate the changed information. These bits are set to a
logic 1 whenever a control input from the modem changes state. These bits are set to
a logic 0 whenever the CPU reads this register.
Table 22:
Modem Status Register bits description
Bit
Symbol
Description
7
MSR[7]
CD. During normal operation, this bit is the complement of the CD
input. Reading this bit in the loop-back mode produces the state of
MCR[3] (OP2).
6
MSR[6]
RI. During normal operation, this bit is the complement of the RI
input. Reading this bit in the loop-back mode produces the state of
MCR[2] (OP1).
5
MSR[5]
DSR. During normal operation, this bit is the complement of the
DSR input. During the loop-back mode, this bit is equivalent to
MCR[0] (DTR).
4
MSR[4]
CTS. During normal operation, this bit is the complement of the
CTS input. During the loop-back mode, this bit is equivalent to
MCR[1] (RTS).
3
MSR[3]
∆CD [1]
Logic 0 = No CD change (normal default condition).
Logic 1 = The CD input to the SC16C652 has changed state
since the last time it was read. A modem Status Interrupt will be
generated.
2
MSR[2]
∆RI [1]
Logic 0 = No RI change (normal default condition).
Logic 1 = The RI input to the SC16C652 has changed from a
logic 0 to a logic 1. A modem Status Interrupt will be generated.
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9397 750 11634
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SC16C652
Philips Semiconductors
Dual UART with 32 bytes of transmit and receive FIFOs
Table 22:
Modem Status Register bits description…continued
Bit
Symbol
Description
1
MSR[1]
∆DSR [1]
Logic 0 = No DSR change (normal default condition).
Logic 1 = The DSR input to the SC16C652 has changed state
since the last time it was read. A modem Status Interrupt will be
generated.
0
MSR[0]
∆CTS [1]
Logic 0 = No CTS change (normal default condition).
Logic 1 = The CTS input to the SC16C652 has changed state
since the last time it was read. A modem Status Interrupt will be
generated.
[1]
Whenever any MSR bit 0-3 is set to logic 1, a Modem Status Interrupt will be generated.
7.9 Scratchpad Register (SPR)
The SC16C652 provides a temporary data register to store 8 bits of user information.
7.10 Enhanced Feature Register (EFR)
Enhanced features are enabled or disabled using this register.
Bits 0 through 4 provide single or dual character software flow control selection.
When the Xon1 and Xon2 and/or Xoff1 and Xoff2 modes are selected, the double
8-bit words are concatenated into two sequential numbers.
Table 23:
Enhanced Feature Register bits description
Bit
Symbol
Description
7
EFR[7]
Automatic CTS flow control.
Logic 0 = Automatic CTS flow control is disabled (normal default
condition).
Logic 1 = Enable Automatic CTS flow control. Transmission will stop
when CTS goes to a logical 1. Transmission will resume when the CTS
pin returns to a logical 0.
6
EFR[6]
Automatic RTS flow control. Automatic RTS may be used for hardware flow
control by enabling EFR[6]. When Auto-RTS is selected, an interrupt will
be generated when the receive FIFO is filled to the programmed trigger
level and RTS will go to a logic 1 at the next trigger level. RTS will return to
a logic 0 when data is unloaded below the next lower trigger level
(programmed trigger level 1). The state of this register bit changes with the
status of the hardware flow control. RTS functions normally when
hardware flow control is disabled.
0 = Automatic RTS flow control is disabled (normal default condition).
1 = Enable Automatic RTS flow control.
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SC16C652
Philips Semiconductors
Dual UART with 32 bytes of transmit and receive FIFOs
Table 23:
Enhanced Feature Register bits description…continued
Bit
Symbol
Description
5
EFR[5]
Special Character Detect.
Logic 0 = Special character detect disabled (normal default condition).
Logic 1 = Special character detect enabled. The SC16C652 compares
each incoming receive character with Xoff2 data. If a match exists, the
received data will be transferred to FIFO and ISR[4] will be set to
indicate detection of special character. Bit-0 in the X-registers
corresponds with the LSB bit for the receive character. When this feature
is enabled, the normal software flow control must be disabled (EFR[3-0]
must be set to a logic 0).
4
EFR[4]
Enhanced function control bit. The content of IER[7-4], ISR[5-4], FCR[5-4],
and MCR[7-5] can be modified and latched. After modifying any bits in the
enhanced registers, EFR[4] can be set to a logic 0 to latch the new values.
This feature prevents existing software from altering or overwriting the
SC16C652 enhanced functions.
Logic 0 = disable/latch enhanced features. IER[7-4], ISR[5-4], FCR[5-4],
and MCR[7-5] are saved to retain the user settings, then IER[7-4]
ISR[5-4], FCR[5-4], and MCR[7-5] are set to a logic 0 to be compatible
with SC16C554 mode. (Normal default condition.)
Logic 1 = Enables the enhanced functions. When this bit is set to a
logic 1, all enhanced features of the SC16C652 are enabled and user
settings stored during a reset will be restored.
3-0
EFR[3-0] Cont-3-0 Tx, Rx control. Logic 0 or cleared is the default condition.
Combinations of software flow control can be selected by programming
these bits. See Table 24.
Software flow control functions[1]
Table 24:
Cont-3
Cont-2
Cont-1
Cont-0
TX, RX software flow controls
0
0
X
X
No transmit flow control
1
0
X
X
Transmit Xon1/Xoff1
0
1
X
X
Transmit Xon2/Xoff2
1
1
X
X
Transmit Xon1 and Xon2/Xoff1 and Xoff2
X
X
0
0
No receive flow control
X
X
1
0
Receiver compares Xon1/Xoff1
X
X
0
1
Receiver compares Xon2/Xoff2
1
0
1
1
Transmit Xon1/Xoff1
0
1
1
1
Transmit Xon2/Xoff2
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
Receiver compares Xon1 and Xon2/Xoff1 and Xoff2
1
1
1
1
Transmit Xon1 and Xon2/Xoff1 and Xoff2
Receiver compares Xon1 and Xon2/Xoff1 and Xoff2
[1]
When using a software flow control the Xon/Xoff characters cannot be used for data transfer.
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9397 750 11634
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SC16C652
Philips Semiconductors
Dual UART with 32 bytes of transmit and receive FIFOs
7.11 SC16C652 external reset condition
Table 25:
Reset state for registers
Register
Reset state
IER
IER[7-0] = 0
FCR
FCR[7-0] = 0
ISR
ISR[7-1] = 0; ISR[0] = 1
LCR
LCR[7-0] = 0
MCR
MCR[7-0] = 0
LSR
LSR[7] = 0; LSR[6-5] = 1; LSR[4-0] = 0
MSR
MSR[7-4] = input signals; MSR[3-0] = 0
SPR
SFR[7-0] = 1
DLL
DLL[7-0] = X
DLM
DLM[7-0] = X
Table 26:
Reset state for outputs
Output
Reset state
TXA, TXB
Logic 1
OP2A, OP2B
Logic 1
RTSA, RTSB
Logic 1
DTRA, DTRB
Logic 1
INTA, INTB
3-State condition
8. Limiting values
Table 27: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VCC
Conditions
Min
Max
Unit
supply voltage
-
7
V
Vn
voltage at any pin
GND − 0.3
VCC + 0.3
V
Tamb
operating temperature
−40
+85
°C
Tstg
storage temperature
−65
+150
°C
Ptot(pack)
total power dissipation
per package
-
500
mW
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9397 750 11634
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SC16C652
Philips Semiconductors
Dual UART with 32 bytes of transmit and receive FIFOs
9. Static characteristics
Table 28: DC electrical characteristics
Tamb = −40 °C to +85 °C; VCC = 2.5 V, 3.3 V or 5.0 V ±10%, unless otherwise specified.
Symbol
Parameter
Conditions
2.5 V
Min
Max
3.3 V
Min
Max
5.0 V
Min
Unit
Max
VIL(CK)
LOW-level clock input voltage
−0.3
0.45
−0.3
0.6
−0.5
0.6
V
VIH(CK)
HIGH-level clock input voltage
1.8
VCC
2.4
VCC
3.0
VCC
V
VIL
LOW-level input voltage
(except X1 clock)
−0.3
0.65
−0.3
0.8
−0.5
0.8
V
VIH
HIGH-level input voltage
(except X1 clock)
1.6
-
2.0
-
2.2
-
V
VOL
LOW-level output voltage
on all outputs[1]
IOL = 5 mA
(databus)
-
-
-
-
-
0.4
V
IOL = 4 mA
(other outputs)
-
-
-
0.4
-
-
V
IOL = 2 mA
(databus)
-
0.4
-
-
-
-
V
IOL = 1.6 mA
(other outputs)
-
0.4
-
-
-
-
V
IOH = −5 mA
(databus)
-
-
-
-
2.4
-
V
IOH = −1 mA
(other outputs)
-
-
2.0
-
-
-
V
IOH = −800 µA
(data bus)
1.85
-
-
-
-
-
V
IOH = −400 µA
(other outputs)
1.85
-
-
-
-
-
V
VOH
HIGH-level output voltage
ILIL
LOW-level input leakage
current
-
±10
-
±10
-
±10
µA
ICL
clock leakage
-
±30
-
±30
-
±30
µA
ICC
supply current
Ci
input capacitance
[1]
f = 5 MHz
-
3.5
-
4.5
-
4.5
mA
-
5
-
5
-
5
pF
Except x2, VOL = 1 V typical.
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9397 750 11634
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SC16C652
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Dual UART with 32 bytes of transmit and receive FIFOs
10. Dynamic characteristics
Table 29: AC electrical characteristics
Tamb = −40 °C to +85 °C; VCC = 2.5 V, 3.3 V or 5.0 V ±10%, unless otherwise specified.
Symbol
Parameter
Conditions
2.5 V
Min
t1w, t2w
clock pulse duration
t3w
oscillator/clock frequency
t6s
Max
3.3 V
Min
Max
Min
6
10
-
6
-
-
48
-
80
address set-up time
0
-
0
-
t6h
address hold time
0
-
0
t7d
IOR delay from chip select
10
-
t7w
IOR strobe width
77
-
t7h
chip select hold time from IOR
0
t9d
read cycle delay
25 pF load
[1]
25 pF load
5.0 V
Unit
Max
-
ns
80
MHz
0
-
ns
-
0
-
ns
10
-
10
-
ns
26
-
23
-
ns
-
0
-
0
-
ns
20
-
20
-
20
-
ns
t12d
delay from IOR to data
25 pF load
-
77
-
26
-
23
ns
t12h
data disable time
25 pF load
-
15
-
15
-
15
ns
t13d
IOW delay from chip select
10
-
10
-
10
-
ns
20
-[2]
20
-[2]
15
-[2]
ns
0
-
0
-
0
-
ns
25
-
25
-
20
-
ns
t13w
IOW strobe width
t13h
chip select hold time from IOW
t15d
write cycle delay
t16s
data set-up time
20
-
20
-
15
-
ns
t16h
data hold time
15
-
5
-
5
-
ns
t17d
delay from IOW to output
25 pF load
-
100
-
33
-
29
ns
t18d
delay to set interrupt from Modem input 25 pF load
-
100
-
24
-
23
ns
t19d
delay to reset interrupt from IOR
-
100
-
24
-
23
ns
t20d
delay from stop to set interrupt
-
1
-
1
-
1
Rclk
[3]
25 pF load
t21d
delay from IOR to reset interrupt
-
100
-
29
-
28
ns
t22d
delay from start to set interrupt
25 pF load
-
100
-
45
-
40
ns
t23d
delay from IOW to transmit start
8
24
8
24
8
24
Rclk
t24d
delay from IOW to reset interrupt
-
100
-
45
-
40
ns
t25d
delay from stop to set RXRDY
-
1
-
1
-
1
Rclk
t26d
delay from IOR to reset RXRDY
-
100
-
45
-
40
ns
t27d
delay from IOW to set TXRDY
-
100
-
45
-
40
ns
t28d
delay from start to reset TXRDY
-
8
-
8
-
8
Rclk
40
-
40
-
ns
tRESET
Reset pulse width
200
-
N
baud rate divisor
1
216 − 1 1
[1]
Applies to external clock, crystal oscillator max 24 MHz.
[2]
1
IOWstrobe max = -------------------------------------2 ( Baudrate max )
216 − 1 1
216 − 1 Rclk
= 333 ns (for Baudratemax = 1.5 Mbits/s)
= 1 µs (for Baudratemax = 460.8 kbits/s)
= 4 µs (for Baudratemax = 115.2 kbits/s)
[3]
When in both DMA mode 0 and FIFO enable mode, the write cycle delay should be larger than one x1, clock cycle.
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9397 750 11634
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SC16C652
Philips Semiconductors
Dual UART with 32 bytes of transmit and receive FIFOs
10.1 Timing diagrams
t6h
VALID
ADDRESS
A0–A2
t6s
t13h
ACTIVE
CSx
t13d
t15d
t13w
IOW
ACTIVE
t16h
t16s
D0–D7
DATA
002aaa109
Fig 5. General write timing.
t6h
VALID
ADDRESS
A0–A2
t6s
t7h
ACTIVE
CSx
t7d
t9d
t7w
IOR
ACTIVE
t12h
t12d
D0–D7
DATA
002aaa110
Fig 6. General read timing.
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SC16C652
Philips Semiconductors
Dual UART with 32 bytes of transmit and receive FIFOs
IOW
ACTIVE
t17d
RTS
DTR
CHANGE OF STATE
CHANGE OF STATE
CD
CHANGE OF STATE
CTS
CHANGE OF STATE
DSR
t18d
INT
t18d
ACTIVE
ACTIVE
ACTIVE
t19d
IOR
ACTIVE
ACTIVE
ACTIVE
t18d
RI
CHANGE OF STATE
002aaa352
Fig 7. Modem input/output timing.
t 2w
t 1w
EXTERNAL
CLOCK
002aaa112
t 3w
Fig 8. External clock timing.
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SC16C652
Philips Semiconductors
Dual UART with 32 bytes of transmit and receive FIFOs
PARITY
BIT
START
BIT
STOP
BIT
NEXT
DATA
START
BIT
DATA BITS (5-8)
RX
D0
D1
D2
D3
D4
D5
D6
D7
5 DATA BITS
6 DATA BITS
t20d
7 DATA BITS
ACTIVE
INT
t21d
ACTIVE
IOR
16 BAUD RATE CLOCK
002aaa113
Fig 9. Receive timing.
PARITY
BIT
START
BIT
STOP
BIT
NEXT
DATA
START
BIT
DATA BITS (5–8)
RX
D0
D1
D2
D3
D4
D5
D6
D7
t25d
ACTIVE
DATA
READY
RXRDY
t26d
ACTIVE
IOR
002aaa114
Fig 10. Receive ready timing in non-FIFO mode.
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9397 750 11634
Product data
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SC16C652
Philips Semiconductors
Dual UART with 32 bytes of transmit and receive FIFOs
START
BIT
PARITY
BIT
STOP
BIT
DATA BITS (5–8)
RX
D0
D1
D2
D3
D4
D5
D6
D7
FIRST BYTE THAT
REACHES THE
TRIGGER LEVEL
t25d
ACTIVE
DATA
READY
RXRDY
t26d
ACTIVE
IOR
002aaa115
Fig 11. Receive ready timing in FIFO mode.
PARITY
BIT
START
BIT
STOP
BIT
NEXT
DATA
START
BIT
DATA BITS (5–8)
TX
D0
D1
D2
D3
D4
D5
D6
D7
5 DATA BITS
6 DATA BITS
7 DATA BITS
ACTIVE TX READY
INT
t22d
t24d
t23d
IOW
ACTIVE
ACTIVE
16 BAUD RATE CLOCK
002aaa116
Fig 12. Transmit timing.
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9397 750 11634
Product data
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SC16C652
Philips Semiconductors
Dual UART with 32 bytes of transmit and receive FIFOs
START
BIT
PARITY
BIT
STOP
BIT
NEXT
DATA
START
BIT
DATA BITS (5-8)
TX
D0
IOW
ACTIVE
D0–D7
BYTE #1
D1
D2
D3
D4
D5
D6
D7
t27d
ACTIVE
TRANSMITTER READY
TXRDY
TRANSMITTER
NOT READY
002aaa117
Fig 13. Transmit ready timing in non-FIFO mode.
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9397 750 11634
Product data
Rev. 04 — 20 June 2003
34 of 41
SC16C652
Philips Semiconductors
Dual UART with 32 bytes of transmit and receive FIFOs
START
BIT
PARITY
BIT
STOP
BIT
DATA BITS (5-8)
TX
D0
D1
D2
D3
D4
D5
D6
D7
5 DATA BITS
6 DATA BITS
7 DATA BITS
IOW
ACTIVE
t28d
D0–D7
BYTE #32
t27d
TXRDY
FIFO FULL
002aaa365
Fig 14. Transmit ready timing in FIFO mode (DMA mode ‘1’).
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9397 750 11634
Product data
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SC16C652
Philips Semiconductors
Dual UART with 32 bytes of transmit and receive FIFOs
11. Package outline
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
SOT313-2
c
y
X
36
25
A
37
24
ZE
e
E HE
A A2
(A 3)
A1
w M
θ
bp
pin 1 index
Lp
L
13
48
detail X
12
1
ZD
e
v M A
w M
bp
D
B
HD
v M B
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HD
HE
L
Lp
v
w
y
mm
1.6
0.20
0.05
1.45
1.35
0.25
0.27
0.17
0.18
0.12
7.1
6.9
7.1
6.9
0.5
9.15
8.85
9.15
8.85
1
0.75
0.45
0.2
0.12
0.1
Z D (1) Z E (1)
θ
0.95
0.55
7
0o
0.95
0.55
o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT313-2
136E05
MS-026
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
00-01-19
03-02-25
Fig 15. LQFP48 package outline (SOT313-2).
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
9397 750 11634
Product data
Rev. 04 — 20 June 2003
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Philips Semiconductors
Dual UART with 32 bytes of transmit and receive FIFOs
12. Soldering
12.1 Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account
of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit
Packages (document order number 9398 652 90011).
There is no soldering method that is ideal for all IC packages. Wave soldering can still
be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In
these situations reflow soldering is recommended. In these situations reflow
soldering is recommended.
12.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and
binding agent) to be applied to the printed-circuit board by screen printing, stencilling
or pressure-syringe dispensing before package placement. Driven by legislation and
environmental forces the worldwide use of lead-free solder pastes is increasing.
Several methods exist for reflowing; for example, convection or convection/infrared
heating in a conveyor type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending on heating method.
Typical reflow peak temperatures range from 215 to 270 °C depending on solder
paste material. The top-surface temperature of the packages should preferably be
kept:
• below 220 °C (SnPb process) or below 245 °C (Pb-free process)
– for all BGA and SSOP-T packages
– for packages with a thickness ≥ 2.5 mm
– for packages with a thickness < 2.5 mm and a volume ≥ 350 mm3 so called
thick/large packages.
• below 235 °C (SnPb process) or below 260 °C (Pb-free process) for packages with
a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages.
Moisture sensitivity precautions, as indicated on packing, must be respected at all
times.
12.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices
(SMDs) or printed-circuit boards with a high component density, as solder bridging
and non-wetting can present major problems.
To overcome these problems the double-wave soldering method was specifically
developed.
If wave soldering is used the following conditions must be observed for optimal
results:
• Use a double-wave soldering method comprising a turbulent wave with high
upward pressure followed by a smooth laminar wave.
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
9397 750 11634
Product data
Rev. 04 — 20 June 2003
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Dual UART with 32 bytes of transmit and receive FIFOs
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be
parallel to the transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the
transport direction of the printed-circuit board.
The footprint must incorporate solder thieves at the downstream end.
• For packages with leads on four sides, the footprint must be placed at a 45° angle
to the transport direction of the printed-circuit board. The footprint must
incorporate solder thieves downstream and at the side corners.
During placement and before soldering, the package must be fixed with a droplet of
adhesive. The adhesive can be applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the adhesive is cured.
Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 °C or
265 °C, depending on solder material applied, SnPb or Pb-free respectively.
A mildly-activated flux will eliminate the need for removal of corrosive residues in
most applications.
12.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low
voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time
must be limited to 10 seconds at up to 300 °C.
When using a dedicated tool, all other leads can be soldered in one operation within
2 to 5 seconds between 270 and 320 °C.
12.5 Package related soldering information
Table 30:
Suitability of surface mount IC packages for wave and reflow soldering
methods
Package[1]
Soldering method
Wave
Reflow[2]
BGA, LBGA, LFBGA, SQFP, SSOP-T[3],
TFBGA, VFBGA
not suitable
suitable
DHVQFN, HBCC, HBGA, HLQFP, HSQFP,
HSOP, HTQFP, HTSSOP, HVQFN, HVSON,
SMS
not suitable[4]
suitable
PLCC[5], SO, SOJ
suitable
suitable
LQFP, QFP, TQFP
not recommended[5][6]
suitable
SSOP, TSSOP, VSO, VSSOP
[1]
[2]
suitable
For more detailed information on the BGA packages refer to the (LF)BGA Application Note
(AN01026); order a copy from your Philips Semiconductors sales office.
All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the
maximum temperature (with respect to time) and body size of the package, there is a risk that internal
or external package cracks may occur due to vaporization of the moisture in them (the so called
popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated
Circuit Packages; Section: Packing Methods.
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
9397 750 11634
Product data
not
recommended[7]
Rev. 04 — 20 June 2003
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Dual UART with 32 bytes of transmit and receive FIFOs
[3]
These transparent plastic packages are extremely sensitive to reflow soldering conditions and must
on no account be processed through more than one soldering cycle or subjected to infrared reflow
soldering with peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow
oven. The package body peak temperature must be kept as low as possible.
These packages are not suitable for wave soldering. On versions with the heatsink on the bottom
side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with
the heatsink on the top side, the solder might be deposited on the heatsink surface.
If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave
direction. The package footprint must incorporate solder thieves downstream and at the side corners.
Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it
is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than
0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
[4]
[5]
[6]
[7]
13. Revision history
Table 31:
Revision history
Rev Date
04
20030620
CPCN
Description
-
Product data (9397 750 11634); ECN 853-2382 30032 of 16 June 2003.
Modifications:
•
Figure 3 “Crystal oscillator connection.” on page 11: changed capacitors’ values and
added connection with resistor.
03
20030314
-
Product data (9397 750 11195); ECN 853-2382 29621 of 07 March 2003.
02
20021217
-
Product data (9397 750 10816); ECN 853-2382 29261 of 06 December 2002.
01
20020916
-
Product data (9397 750 10335); ECN 853-2382 28948 of 16 September 2002.
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
9397 750 11634
Product data
Rev. 04 — 20 June 2003
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Dual UART with 32 bytes of transmit and receive FIFOs
14. Data sheet status
Level
Data sheet status[1]
Product status[2][3]
Definition
I
Objective data
Development
This data sheet contains data from the objective specification for product development. Philips
Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Qualification
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
Product data
Production
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1]
Please consult the most recently issued data sheet before initiating or completing a design.
[2]
The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at
URL http://www.semiconductors.philips.com.
[3]
For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
15. Definitions
16. Disclaimers
Short-form specification — The data in a short-form specification is
extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Life support — These products are not designed for use in life support
appliances, devices, or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so
at their own risk and agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition — Limiting values given are in accordance with
the Absolute Maximum Rating System (IEC 60134). Stress above one or
more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any
other conditions above those given in the Characteristics sections of the
specification is not implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information — Applications that are described herein for any
of these products are for illustrative purposes only. Philips Semiconductors
make no representation or warranty that such applications will be suitable for
the specified use without further testing or modification.
Right to make changes — Philips Semiconductors reserves the right to
make changes in the products - including circuits, standard cells, and/or
software - described or contained herein in order to improve design and/or
performance. When the product is in full production (status ‘Production’),
relevant changes will be communicated via a Customer Product/Process
Change Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no
licence or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are
free from patent, copyright, or mask work right infringement, unless otherwise
specified.
Contact information
For additional information, please visit http://www.semiconductors.philips.com.
For sales office addresses, send e-mail to: [email protected].
Product data
Fax: +31 40 27 24825
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
9397 750 11634
Rev. 04 — 20 June 2003
40 of 41
SC16C652
Philips Semiconductors
Dual UART with 32 bytes of transmit and receive FIFOs
Contents
1
2
3
4
5
5.1
5.2
6
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
7
7.1
7.2
7.2.1
7.2.2
7.3
7.3.1
7.3.2
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 7
UART A-B functions . . . . . . . . . . . . . . . . . . . . . 7
Internal registers. . . . . . . . . . . . . . . . . . . . . . . . 8
FIFO operation . . . . . . . . . . . . . . . . . . . . . . . . . 8
Hardware flow control . . . . . . . . . . . . . . . . . . . . 9
Software flow control . . . . . . . . . . . . . . . . . . . . 9
Special feature software flow control . . . . . . . 10
Hardware/software and time-out interrupts. . . 10
Programmable baud rate generator . . . . . . . . 11
DMA operation . . . . . . . . . . . . . . . . . . . . . . . . 12
Loop-back mode . . . . . . . . . . . . . . . . . . . . . . . 12
Register descriptions . . . . . . . . . . . . . . . . . . . 14
Transmit (THR) and Receive (RHR)
Holding Registers . . . . . . . . . . . . . . . . . . . . . 15
Interrupt Enable Register (IER) . . . . . . . . . . . 15
IER versus Transmit/Receive FIFO interrupt
mode operation . . . . . . . . . . . . . . . . . . . . . . . 16
IER versus Receive/Transmit FIFO polled
mode operation . . . . . . . . . . . . . . . . . . . . . . . 17
FIFO Control Register (FCR) . . . . . . . . . . . . . 17
DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
FIFO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Interrupt Status Register (ISR) . . . . . . . . . . . . 20
Line Control Register (LCR) . . . . . . . . . . . . . . 21
Modem Control Register (MCR) . . . . . . . . . . . 22
Line Status Register (LSR) . . . . . . . . . . . . . . . 23
Modem Status Register (MSR). . . . . . . . . . . . 24
Scratchpad Register (SPR) . . . . . . . . . . . . . . 25
Enhanced Feature Register (EFR) . . . . . . . . . 25
SC16C652 external reset condition . . . . . . . . 27
© Koninklijke Philips Electronics N.V. 2003.
Printed in the U.S.A
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner.
The information presented in this document does not form part of any quotation or
contract, is believed to be accurate and reliable and may be changed without notice. No
liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.
Date of release: 20 June 2003
Document order number: 9397 750 11634
8
9
10
10.1
11
12
12.1
12.2
12.3
12.4
12.5
13
14
15
16
Limiting values . . . . . . . . . . . . . . . . . . . . . . . .
Static characteristics . . . . . . . . . . . . . . . . . . .
Dynamic characteristics . . . . . . . . . . . . . . . . .
Timing diagrams. . . . . . . . . . . . . . . . . . . . . . .
Package outline . . . . . . . . . . . . . . . . . . . . . . . .
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction to soldering surface mount
packages . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reflow soldering. . . . . . . . . . . . . . . . . . . . . . .
Wave soldering. . . . . . . . . . . . . . . . . . . . . . . .
Manual soldering . . . . . . . . . . . . . . . . . . . . . .
Package related soldering information . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . .
Data sheet status. . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . .
27
28
29
30
36
37
37
37
37
38
38
39
40
40
40