74AUP2G17 Low-power dual Schmitt trigger Rev. 02 — 10 January 2008 Product data sheet 1. General description The 74AUP2G17 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. The 74AUP2G17 provides two Schmitt trigger buffers. It is capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. The inputs switch at different points for positive and negative-going signals. The difference between the positive voltage VT+ and the negative voltage VT− is defined as the input hysteresis voltage VH. 2. Features ■ Wide supply voltage range from 0.8 V to 3.6 V ■ High noise immunity ■ Complies with JEDEC standards: ◆ JESD8-12 (0.8 V to 1.3 V) ◆ JESD8-11 (0.9 V to 1.65 V) ◆ JESD8-7 (1.2 V to 1.95 V) ◆ JESD8-5 (1.8 V to 2.7 V) ◆ JESD8-B (2.7 V to 3.6 V) ■ ESD protection: ◆ HBM JESD22-A114E Class 3A exceeds 5000 V ◆ MM JESD22-A115-A exceeds 200 V ◆ CDM JESD22-C101-C exceeds 1000 V ■ Low static power consumption; ICC = 0.9 µA (maximum) ■ Latch-up performance exceeds 100 mA per JESD 78 Class II ■ Inputs accept voltages up to 3.6 V ■ Low noise overshoot and undershoot < 10 % of VCC ■ IOFF circuitry provides partial Power-down mode operation ■ Multiple package options ■ Specified from −40 °C to +85 °C and −40 °C to +125 °C 74AUP2G17 NXP Semiconductors Low-power dual Schmitt trigger 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP2G17GW −40 °C to +125 °C SC-88 plastic surface-mounted package; 6 leads SOT363 74AUP2G17GM −40 °C to +125 °C XSON6 plastic extremely thin small outline package; no leads; SOT886 6 terminals; body 1 × 1.45 × 0.5 mm 74AUP2G17GF −40 °C to +125 °C XSON6 plastic extremely thin small outline package; no leads; SOT891 6 terminals; body 1 × 1 × 0.5 mm 4. Marking Table 2. Marking Type number Marking code 74AUP2G17GW pV 74AUP2G17GM pV 74AUP2G17GF pV 5. Functional diagram 1 1A 1Y 6 3 2A 2Y 4 1 6 3 4 mnb067 mnb066 Fig 1. Logic symbol Fig 2. IEC logic symbol 1A 1Y 2A 2Y mnb068 Fig 3. Logic diagram 74AUP2G17_2 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 02 — 10 January 2008 2 of 18 74AUP2G17 NXP Semiconductors Low-power dual Schmitt trigger 6. Pinning information 6.1 Pinning 74AUP2G17 74AUP2G17 74AUP2G17 1A 1A 1 6 1Y GND 2 5 VCC 2A 3 4 2Y 1 6 1Y GND 2 5 VCC 2A 3 4 2Y 001aab675 001aab674 Fig 4. Pin configuration SOT363 (SC-88) Fig 5. Pin configuration SOT886 (XSON6) 1A 1 6 1Y GND 2 5 VCC 2A 3 4 2Y 001aae790 Transparent top view Fig 6. Pin configuration SOT891 (XSON6) 6.2 Pin description Table 3. Pin description Symbol Pin Description 1A 1 data input GND 2 ground (0 V) 2A 3 data input 2Y 4 data output VCC 5 supply voltage 1Y 6 data output 7. Functional description Table 4. Function table[1] Input Output nA nY L L H H [1] H = HIGH voltage level; L = LOW voltage level. 74AUP2G17_2 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 02 — 10 January 2008 3 of 18 74AUP2G17 NXP Semiconductors Low-power dual Schmitt trigger 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current Conditions VI < 0 V [1] VO > VCC or VO < 0 V [1] Min Max Unit −0.5 +4.6 V - −50 mA −0.5 +4.6 V - ±50 mA −0.5 +4.6 V VO output voltage Active mode and Power-down mode IO output current VO = 0 V to VCC - ±20 mA ICC supply current - 50 mA IGND ground current - −50 mA Tstg storage temperature −65 +150 °C - 250 mW Tamb = −40 °C to +125 °C total power dissipation Ptot [2] [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For SC-88 packages: above 87.5 °C the value of Ptot derates linearly with 4.0 mW/K. For XSON6 packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K. 9. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter VCC supply voltage VI input voltage VO output voltage Conditions Max Unit 0.8 3.6 V 0 3.6 V Active mode 0 VCC V Power-down mode; VCC = 0 V 0 3.6 V −40 +125 °C ambient temperature Tamb Min 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit IO = −20 µA; VCC = 0.8 V to 3.6 V VCC − 0.1 - - V Tamb = 25 °C VOH HIGH-level output voltage VI = VIH or VIL IO = −1.1 mA; VCC = 1.1 V 0.75 × VCC - - V IO = −1.7 mA; VCC = 1.4 V 1.11 - - V IO = −1.9 mA; VCC = 1.65 V 1.32 - - V IO = −2.3 mA; VCC = 2.3 V 2.05 - - V IO = −3.1 mA; VCC = 2.3 V 1.9 - - V IO = −2.7 mA; VCC = 3.0 V 2.72 - - V IO = −4.0 mA; VCC = 3.0 V 2.6 - - V 74AUP2G17_2 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 02 — 10 January 2008 4 of 18 74AUP2G17 NXP Semiconductors Low-power dual Schmitt trigger Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions VOL VI = VIH or VIL LOW-level output voltage Min Typ Max Unit IO = 20 µA; VCC = 0.8 V to 3.6 V - - 0.1 V IO = 1.1 mA; VCC = 1.1 V - - 0.3 × VCC V IO = 1.7 mA; VCC = 1.4 V - - 0.31 V IO = 1.9 mA; VCC = 1.65 V - - 0.31 V IO = 2.3 mA; VCC = 2.3 V - - 0.31 V IO = 3.1 mA; VCC = 2.3 V - - 0.44 V IO = 2.7 mA; VCC = 3.0 V - - 0.31 V IO = 4.0 mA; VCC = 3.0 V - - 0.44 V ±0.1 µA II input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - VI or VO = 0 V to 3.6 V; VCC = 0 V IOFF power-off leakage current - - ±0.2 µA ∆IOFF additional power-off leakage VI or VO = 0 V to 3.6 V; current VCC = 0 V to 0.2 V - - ±0.2 µA ICC supply current VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V - - 0.5 µA ∆ICC additional supply current VI = VCC − 0.6 V; IO = 0 A; VCC = 3.3 V - - 40 µA CI input capacitance VI = GND or VCC; VCC = 0 V to 3.6 V - 1.1 - pF CO output capacitance VO = GND; VCC = 0 V - 1.8 - pF IO = −20 µA; VCC = 0.8 V to 3.6 V VCC − 0.1 - - V Tamb = −40 °C to +85 °C VOH VOL HIGH-level output voltage LOW-level output voltage VI = VIH or VIL IO = −1.1 mA; VCC = 1.1 V 0.7 × VCC - - V IO = −1.7 mA; VCC = 1.4 V 1.03 - - V IO = −1.9 mA; VCC = 1.65 V 1.30 - - V IO = −2.3 mA; VCC = 2.3 V 1.97 - - V IO = −3.1 mA; VCC = 2.3 V 1.85 - - V IO = −2.7 mA; VCC = 3.0 V 2.67 - - V IO = −4.0 mA; VCC = 3.0 V 2.55 - - V VI = VIH or VIL IO = 20 µA; VCC = 0.8 V to 3.6 V - - 0.1 V IO = 1.1 mA; VCC = 1.1 V - - 0.3 × VCC V IO = 1.7 mA; VCC = 1.4 V - - 0.37 V IO = 1.9 mA; VCC = 1.65 V - - 0.35 V IO = 2.3 mA; VCC = 2.3 V - - 0.33 V IO = 3.1 mA; VCC = 2.3 V - - 0.45 V IO = 2.7 mA; VCC = 3.0 V - - 0.33 V IO = 4.0 mA; VCC = 3.0 V - - 0.45 V II input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - ±0.5 µA IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - ±0.5 µA 74AUP2G17_2 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 02 — 10 January 2008 5 of 18 74AUP2G17 NXP Semiconductors Low-power dual Schmitt trigger Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit ∆IOFF additional power-off leakage VI or VO = 0 V to 3.6 V; current VCC = 0 V to 0.2 V - - ±0.6 µA ICC supply current VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V - - 0.9 µA ∆ICC additional supply current VI = VCC − 0.6 V; IO = 0 A; VCC = 3.3 V - - 50 µA Tamb = −40 °C to +125 °C VOH VOL HIGH-level output voltage LOW-level output voltage VI = VIH or VIL IO = −20 µA; VCC = 0.8 V to 3.6 V VCC − 0.11 - - V IO = −1.1 mA; VCC = 1.1 V 0.6 × VCC - - V IO = −1.7 mA; VCC = 1.4 V 0.93 - - V IO = −1.9 mA; VCC = 1.65 V 1.17 - - V IO = −2.3 mA; VCC = 2.3 V 1.77 - - V IO = −3.1 mA; VCC = 2.3 V 1.67 - - V IO = −2.7 mA; VCC = 3.0 V 2.40 - - V IO = −4.0 mA; VCC = 3.0 V 2.30 - - V IO = 20 µA; VCC = 0.8 V to 3.6 V - - 0.11 V IO = 1.1 mA; VCC = 1.1 V - - 0.33 × VCC V IO = 1.7 mA; VCC = 1.4 V - - 0.41 V IO = 1.9 mA; VCC = 1.65 V - - 0.39 V IO = 2.3 mA; VCC = 2.3 V - - 0.36 V IO = 3.1 mA; VCC = 2.3 V - - 0.50 V IO = 2.7 mA; VCC = 3.0 V - - 0.36 V IO = 4.0 mA; VCC = 3.0 V - - 0.50 V ±0.75 µA VI = VIH or VIL II input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - VI or VO = 0 V to 3.6 V; VCC = 0 V IOFF power-off leakage current - - ±0.75 µA ∆IOFF additional power-off leakage VI or VO = 0 V to 3.6 V; current VCC = 0 V to 0.2 V - - ±0.75 µA ICC supply current VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V - - 1.4 µA ∆ICC additional supply current VI = VCC − 0.6 V; IO = 0 A; VCC = 3.3 V - - 75 µA 74AUP2G17_2 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 02 — 10 January 2008 6 of 18 74AUP2G17 NXP Semiconductors Low-power dual Schmitt trigger 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8 Symbol Parameter 25 °C Conditions −40 °C to +125 °C Unit Min Typ[1] Max Min Max (85 °C) Max (125 °C) - 19.0 - - - - ns VCC = 1.1 V to 1.3 V 2.6 5.7 10.6 2.5 10.9 11.1 ns VCC = 1.4 V to 1.6 V 2.4 4.2 6.5 2.3 7.1 7.4 ns VCC = 1.65 V to 1.95 V 2.0 3.6 5.5 1.9 6.1 6.3 ns VCC = 2.3 V to 2.7 V 1.9 3.0 4.2 1.8 4.6 4.8 ns VCC = 3.0 V to 3.6 V 1.8 2.7 3.6 1.5 3.8 4.0 ns - 22.5 - - - - ns VCC = 1.1 V to 1.3 V 2.9 6.6 12.4 2.7 12.9 13.0 ns VCC = 1.4 V to 1.6 V 2.6 4.8 7.8 2.4 8.3 8.7 ns VCC = 1.65 V to 1.95 V 2.5 4.2 6.3 2.4 6.8 7.1 ns VCC = 2.3 V to 2.7 V 2.3 3.5 4.8 2.1 5.3 5.6 ns VCC = 3.0 V to 3.6 V 2.1 3.3 4.4 2.0 4.6 4.8 ns - 26.0 - - - - ns VCC = 1.1 V to 1.3 V 3.2 7.4 14.1 3.1 14.7 14.9 ns VCC = 1.4 V to 1.6 V 3.1 5.4 8.7 2.8 9.5 9.9 ns VCC = 1.65 V to 1.95 V 2.7 4.7 7.1 2.7 7.8 8.2 ns VCC = 2.3 V to 2.7 V 2.6 4.0 5.6 2.5 6.0 6.3 ns VCC = 3.0 V to 3.6 V 2.5 3.7 4.9 2.2 5.2 5.5 ns - 36.3 - - - - ns VCC = 1.1 V to 1.3 V 3.9 9.7 19.0 3.7 19.8 20.1 ns VCC = 1.4 V to 1.6 V 3.5 7.0 11.2 3.6 12.4 13.0 ns VCC = 1.65 V to 1.95 V 3.5 6.0 9.2 3.4 10.1 10.7 ns VCC = 2.3 V to 2.7 V 3.4 5.1 7.0 3.2 7.5 7.9 ns VCC = 3.0 V to 3.6 V 3.3 4.8 6.2 3.1 7.1 7.5 ns CL = 5 pF tpd propagation delay nA to nY; see Figure 7 [2] VCC = 0.8 V CL = 10 pF tpd propagation delay nA to nY; see Figure 7 [2] VCC = 0.8 V CL = 15 pF tpd propagation delay nA to nY; see Figure 7 [2] VCC = 0.8 V CL = 30 pF tpd propagation delay nA to nY; see Figure 7 VCC = 0.8 V [2] 74AUP2G17_2 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 02 — 10 January 2008 7 of 18 74AUP2G17 NXP Semiconductors Low-power dual Schmitt trigger Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8 Symbol Parameter 25 °C Conditions −40 °C to +125 °C Unit Min Typ[1] Max Min Max (85 °C) Max (125 °C) VCC = 0.8 V - 2.9 - - - - pF VCC = 1.1 V to 1.3 V - 3.0 - - - - pF CL = 5 pF, 10 pF, 15 pF and 30 pF power dissipation capacitance CPD fi = 1 MHz; VI = GND to VCC [3] VCC = 1.4 V to 1.6 V - 3.2 - - - - pF VCC = 1.65 V to 1.95 V - 3.4 - - - - pF VCC = 2.3 V to 2.7 V - 4.0 - - - - pF VCC = 3.0 V to 3.6 V - 4.5 - - - - pF [1] All typical values are measured at nominal VCC. [2] tpd is the same as tPLH and tPHL [3] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of the outputs. 12. Waveforms VI nA input VM VM GND tPLH tPHL VOH VM nY output VM VOL mnb072 Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage drop that occur with the output load. Fig 7. The data input (nA) to output (nY) propagation delays Table 9. Measurement points Supply voltage Output Input VCC VM VM VI tr = tf 0.8 V to 3.6 V 0.5 × VCC 0.5 × VCC VCC ≤ 3.0 ns 74AUP2G17_2 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 02 — 10 January 2008 8 of 18 74AUP2G17 NXP Semiconductors Low-power dual Schmitt trigger VCC VEXT 5 kΩ G VI VO DUT RT CL RL 001aac521 Test data is given in Table 10. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 8. Load circuitry for switching times Table 10. Test data Supply voltage Load VEXT RL[1] VCC CL 0.8 V to 3.6 V 5 pF, 10 pF, 15 pF and 30 pF 5 kΩ or 1 MΩ [1] tPLH, tPHL tPZH, tPHZ tPZL, tPLZ open GND 2 × VCC For measuring enable and disable times RL = 5 kΩ, for measuring propagation delays, setup and hold times and pulse width RL = 1 MΩ. 13. Transfer characteristics Table 11. Transfer characteristics Voltages are referenced to GND (ground = 0 V; for test circuit see Figure 8. Symbol Parameter VT+ VT− positive-going threshold voltage negative-going threshold voltage 25 °C Conditions Typ Max Min Max (85 °C) Max (125 °C) Unit see Figure 9 and Figure 10 VCC = 0.8 V 0.30 - 0.60 0.30 0.60 0.62 V VCC = 1.1 V 0.53 - 0.90 0.53 0.90 0.92 V VCC = 1.4 V 0.74 - 1.11 0.74 1.11 1.13 V VCC = 1.65 V 0.91 - 1.29 0.91 1.29 1.31 V VCC = 2.3 V 1.37 - 1.77 1.37 1.77 1.80 V VCC = 3.0 V 1.88 - 2.29 1.88 2.29 2.32 V VCC = 0.8 V 0.10 - 0.60 0.10 0.60 0.60 V VCC = 1.1 V 0.26 - 0.65 0.26 0.65 0.65 V VCC = 1.4 V 0.39 - 0.75 0.39 0.75 0.75 V VCC = 1.65 V 0.47 - 0.84 0.47 0.84 0.84 V VCC = 2.3 V 0.69 - 1.04 0.69 1.04 1.04 V VCC = 3.0 V 0.88 - 1.24 0.88 1.24 1.24 V see Figure 9 and Figure 10 74AUP2G17_2 Product data sheet −40 °C to +125 °C Min © NXP B.V. 2008. All rights reserved. Rev. 02 — 10 January 2008 9 of 18 74AUP2G17 NXP Semiconductors Low-power dual Schmitt trigger Table 11. Transfer characteristics …continued Voltages are referenced to GND (ground = 0 V; for test circuit see Figure 8. Symbol Parameter VH 25 °C Conditions −40 °C to +125 °C Unit Min Typ Max Min Max (85 °C) Max (125 °C) VCC = 0.8 V 0.07 - 0.50 0.07 0.50 0.50 V VCC = 1.1 V 0.08 - 0.46 0.08 0.46 0.46 V VCC = 1.4 V 0.18 - 0.56 0.18 0.56 0.56 V VCC = 1.65 V 0.27 - 0.66 0.27 0.66 0.66 V VCC = 2.3 V 0.53 - 0.92 0.53 0.92 0.92 V VCC = 3.0 V 0.79 - 1.31 0.79 1.31 1.31 V hysteresis voltage (VT+ − VT−); see Figure 9, Figure 10, Figure 11 and Figure 12 14. Waveforms transfer characteristics VO VI VT+ VH VT− VO VI VH VT− VT+ Fig 9. Transfer characteristic mnb154 mnb155 VT+ and VT− limits at 70 % and 20 %. Fig 10. Definition of VT+, VT− and VH 74AUP2G17_2 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 02 — 10 January 2008 10 of 18 74AUP2G17 NXP Semiconductors Low-power dual Schmitt trigger 001aad691 240 ICC (µA) 160 80 0 0 0.4 0.8 1.2 1.6 2.0 VI (V) Fig 11. Typical transfer characteristics; VCC = 1.8 V 001aad692 1200 ICC (µA) 800 400 0 0 1.0 2.0 3.0 VI (V) Fig 12. Typical transfer characteristics; VCC = 3.0 V 74AUP2G17_2 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 02 — 10 January 2008 11 of 18 74AUP2G17 NXP Semiconductors Low-power dual Schmitt trigger 15. Application information The slow input rise and fall times cause additional power dissipation, this can be calculated using the following formula: Padd = fi × (tr × ∆ICC(AV) + tf × ∆ICC(AV)) × VCC where: Padd = additional power dissipation (µW); fi = input frequency (MHz); tr = input rise time (ns); 10 % to 90 %; tf = input fall time (ns); 90 % to 10 %; ∆ICC(AV) = average additional supply current (µA). Average ∆ICC(AV) differs with positive or negative input transitions, as shown in Figure 13. 001aad027 0.3 ∆ICC(AV) (mA) (1) 0.2 (2) 0.1 0 0.8 1.8 2.8 3.8 VCC (V) (1) Positive-going edge. (2) Negative-going edge. Linear change of VI between 0.8 V and 2.0 V. All values given are typical, unless otherwise specified. Fig 13. Average ICC as a function of VCC 74AUP2G17_2 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 02 — 10 January 2008 12 of 18 74AUP2G17 NXP Semiconductors Low-power dual Schmitt trigger 16. Package outline Plastic surface-mounted package; 6 leads SOT363 D E B y X A HE 6 5 v M A 4 Q pin 1 index A A1 1 2 e1 3 c bp Lp w M B e detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 max bp c D E e e1 HE Lp Q v w y mm 1.1 0.8 0.1 0.30 0.20 0.25 0.10 2.2 1.8 1.35 1.15 1.3 0.65 2.2 2.0 0.45 0.15 0.25 0.15 0.2 0.2 0.1 OUTLINE VERSION REFERENCES IEC SOT363 JEDEC JEITA SC-88 EUROPEAN PROJECTION ISSUE DATE 04-11-08 06-03-16 Fig 14. Package outline SOT363 (SC-88) 74AUP2G17_2 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 02 — 10 January 2008 13 of 18 74AUP2G17 NXP Semiconductors Low-power dual Schmitt trigger XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm SOT886 b 1 2 3 4× (2) L L1 e 6 5 4 e1 e1 6× A (2) A1 D E terminal 1 index area 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A (1) max A1 max b D E e e1 L L1 mm 0.5 0.04 0.25 0.17 1.5 1.4 1.05 0.95 0.6 0.5 0.35 0.27 0.40 0.32 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION SOT886 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 04-07-15 04-07-22 MO-252 Fig 15. Package outline SOT886 (XSON6) 74AUP2G17_2 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 02 — 10 January 2008 14 of 18 74AUP2G17 NXP Semiconductors Low-power dual Schmitt trigger XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm 1 SOT891 b 3 2 4× (1) L L1 e 6 5 4 e1 e1 6× A (1) A1 D E terminal 1 index area 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max A1 max b D E e e1 L L1 mm 0.5 0.04 0.20 0.12 1.05 0.95 1.05 0.95 0.55 0.35 0.35 0.27 0.40 0.32 Note 1. Can be visible in some manufacturing processes. OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 05-04-06 07-05-15 SOT891 Fig 16. Package outline SOT891 (XSON6) 74AUP2G17_2 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 02 — 10 January 2008 15 of 18 74AUP2G17 NXP Semiconductors Low-power dual Schmitt trigger 17. Abbreviations Table 12. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 18. Revision history Table 13. Revision history Document ID Release date Data sheet status Change notice Supersedes 74AUP2G17_2 20080110 Product data sheet - 74AUP2G17_1 - - Modifications: 74AUP2G17_1 • ESD HBM value modified in Section 2 20061107 Product data sheet 74AUP2G17_2 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 02 — 10 January 2008 16 of 18 74AUP2G17 NXP Semiconductors Low-power dual Schmitt trigger 19. Legal information 19.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. 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Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 19.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 20. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: [email protected] 74AUP2G17_2 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 02 — 10 January 2008 17 of 18 74AUP2G17 NXP Semiconductors Low-power dual Schmitt trigger 21. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 17 18 19 19.1 19.2 19.3 19.4 20 21 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Transfer characteristics. . . . . . . . . . . . . . . . . . . 9 Waveforms transfer characteristics . . . . . . . . 10 Application information. . . . . . . . . . . . . . . . . . 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Contact information. . . . . . . . . . . . . . . . . . . . . 17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 10 January 2008 Document identifier: 74AUP2G17_2