Philips Semiconductors Programmable Logic Devices Product specification CMOS programmable multi-function PLD (42 × 105 × 12) DESCRIPTION FEATURES The new PLC42VA12 CMOS PLD from Philips Semiconductors exhibits a unique combination of the two architectural concepts that revolutionized the PLD marketplace. • High-speed EPROM-based CMOS The Philips Semiconductors unique Output Macro Cell (OMC) embodies all the advantages and none of the disadvantages associated with the “V” type Output Macro Cell devices. This new design, combined with added functionality of two programmable arrays, represents a significant advancement in the configurability and efficiency of multi-function PLDs. • Two fully programmable arrays eliminate The most significant improvement in the Output Macro Cell structure is the implementation of the register bypass function. Any of the 10 J-K/D registers can be individually bypassed, thus creating a combinatorial I/O path from the AND array to the output pin. Unlike other “V” type devices, the register in the PLC42VA12 Macro Cell remains fully functional as a buried register. Both the combinatorial I/O and buried register have separate input paths (from the AND array). In most V-type architectures, the register is lost as a resource when the cell is configured as a combinatorial I/O. This feature provides the capability to operate the buried register independently from the combinatorial I/O. The PLC42VA12 is an EPROM-based CMOS device. Designs can be generated using Philips Semiconductors SNAP PLD design software packages or one of several other commercially available JEDEC standard PLD design software packages. PLC42VA12 PIN CONFIGURATIONS FA and N Packages Multi-Function PLD – Super set of 22V10, 32VX10 and 20RA10 PAL ICs I0/CLK 1 24 VCC I1 2 23 M9 I2 3 22 M8 I3 4 21 M7 I4 5 20 M6 I5 6 19 M5 I6 7 18 M4 I7 8 17 M3 I8 9 16 M2 “P-term Depletion” – Up to 64 P-terms per OR function • Improved Output Macro Cell Structure – Individually programmable as: * Registered Output with feedback * Registered Input * Combinatorial I/O with Buried Register * Dedicated I/O with feedback * Dedicated Input (combinatorial) – Bypassed Registers are 100% functional with separate input and feedback paths – Individual Output Enable control functions * From pin or AND array • Reprogrammable – 100% tested for B0 10 15 M1 B1 11 14 M0 GND 12 13 I9/OE N = Plastic DIP (300mil-wide) FA = Ceramic DIP with Quartz Window (300mil-wide) programmability • Eleven clock sources • Register Preload and Diagnostic Test Mode A Package Features • Security fuse APPLICATIONS • Mealy or Moore State Machines – Synchronous – Asynchronous • Multiple, independent State Machines • 10-bit ripple cascade • Sequence recognition • Bus Protocol generation • Industrial control • A/D Scanning I2 I0/ I1 CLK N/C VCC M9 M8 4 3 2 1 28 27 26 I3 5 25 M7 I4 6 24 M6 I5 7 23 M5 N/C 8 22 N/C I6 9 21 M4 I7 10 20 M3 I8 11 19 M2 12 13 14 15 16 17 18 B0 B1 GND N/C I9/ M0 M1 OE A = Plastic Leaded Chip Carrier (450mil-square) ORDERING INFORMATION DESCRIPTION ORDER CODE DRAWING NUMBER 24-Pin Ceramic Dual In-Line with window, Reprogrammable (300mil-wide) PLC42VA12FA 1478A 24-Pin Plastic Dual In-Line, One Time Programmable (300mil-wide) PLC42VA12N 0410D 28-Pin Plastic Leaded Chip Carrier, One Time Programmable (450mil-wide) PLC42VA12A 0401F PAL is a registered trademark of Advanced Micro Devices, Inc. October 22, 1993 73 853–1414 11164 Philips Semiconductors Programmable Logic Devices Product specification CMOS programmable multi-function PLD (42 × 105 × 12) PLC42VA12 LOGIC DIAGRAM 63 I1 I2 I3 I4 I5 I6 I7 I8 56 55 48 47 40 39 32 31 24 23 16 15 8 7 0 FC RRRR C P MMMM K A8 7 6 5 8 2 3 4 5 6 7 8 9 PR J CK KQ PR J CK KQ PR J CK KQ PR J CK KQ NOTE: Programmable Connection October 22, 1993 74 Philips Semiconductors Programmable Logic Devices Product specification CMOS programmable multi-function PLD (42 × 105 × 12) PLC42VA12 LOGIC DIAGRAM (Continued) RRRR C P MMMM K B4 3 2 1 4 CCC KKK L 765 A CCC KKK L 321 B PRPR C MMMM K 9900 9 C L L DDDD DDDD K M MMMMM MMMM 0 9 01234 5678 DD MM 09 DD 10 13 I9/OE I0/CLK 1 CK 22 M8 CK 21 M7 CK 20 M6 CK 19 M5 PR J CK KQ CK PR J CK KQ CK PR J CK KQ CK 18 M4 17 M3 16 M2 PR J CK KQ CK 15 M1 PR J CK KQ CK 23 M9 PR J CK KQ CK 14 M0 11 B1 10 B0 October 22, 1993 75 Philips Semiconductors Programmable Logic Devices Product specification CMOS programmable multi-function PLD (42 × 105 × 12) PLC42VA12 FUNCTIONAL DIAGRAM P63 P0 FC Ln Pn Rn CKn LMn PMn RMn CKn DMn DMn DBn I9/OE I1 – I8 X8 I0/CLK X2 X1 X2 X8 X8 X2 X2 X2 X2 X8 X2 X2 CLK CONTROL P J X8 R CK X8 X8 K En (X2) OEn Q X8 OMC CONFIG. POLARITY X8 M1 – M8 CLK CONTROL X2 P J X2 K R CK X2 En (X2) OEn Q OMC CONFIG. X2 M0, M9 POLARITY X2 POLARITY X2 B0 – B1 October 22, 1993 76 Philips Semiconductors Programmable Logic Devices Product specification CMOS programmable multi-function PLD (42 × 105 × 12) PLC42VA12 ABSOLUTE MAXIMUM RATINGS1 SYMBOL THERMAL RATINGS PARAMETER TEMPERATURE RATINGS UNIT –0.5 to +7 VDC Maximum junction 150°C 75°C VCC Supply voltage VIN Input voltage –0.5 to VCC +0.5 VDC Maximum ambient VOUT Output voltage –0.5 to VCC +0.5 VDC IIN Input currents –10 to +10 mA Allowable thermal rise ambient to junction IOUT Output currents +24 mA Tamb Operating temperature range 0 to +75 °C Tstg Storage temperature range –65 to +150 °C 75°C NOTE: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied. AC TEST CONDITIONS VOLTAGE WAVEFORMS VCC +5V +3.0V S1 90% C1 C2 R1 In INPUTS In BM 5ns R2 DUT tF 5ns +3.0V 90% GND MZ 0V OUTPUTS 5ns 5ns MEASUREMENTS: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified. NOTE: C1 and C2 are to bypass VCC to GND. Test Load Circuit October 22, 1993 CL tR 10% BM CK 10% 0V OE MZ Input Pulses 77 Philips Semiconductors Programmable Logic Devices Product specification CMOS programmable multi-function PLD (42 × 105 × 12) PLC42VA12 DC ELECTRICAL CHARACTERISTICS 0°C ≤ Tamb ≤ +75°C, 4.75V ≤ VCC ≤ 5.25V LIMITS SYMBOL PARAMETER TEST CONDITION MIN TYP1 MAX UNIT Input voltage2 VIL Low VCC = MIN –0.3 0.8 V VIH High VCC = MAX 2.0 VCC + 0.3 V 0.5 V Output voltage2 VOL Low VCC = MIN; IOL = 16mA VOH High VCC = MIN; IOH = –3.2mA 0.3 2.4 4.3 V Input current IIL Low VIN = GND –1 –10 µA IIH High VIN = VCC +1 10 µA VOUT = VCC VOUT = GND 1 –1 10 –10 µA µA Output current IO(OFF) Hi-Z state IOS Short-circuit3,7 –130 mA ICC1 VCC supply current (Active)4 IOUT = 0mA, f = 15MHz6, VCC = MAX 90 120 mA ICC2 VCC supply current (Active)5 IOUT = 0mA, f = 15MHz6, VCC = MAX 70 100 mA VCC = 5V; VIN = 2.0V 12 pF 15 pF VOUT = GND Capacitance CI Input CB I/O VB = 2.0V NOTES: 1. All typical values are at VCC = 5V. Tamb = +25°C. 2. All voltage values are with respect to network ground terminal. 3. Duration of short–circuit should not exceed one second. Test one at a time. 4. Tested with VIL = 0.45V, VIH = 2.4V. 5. Tested with VIL = 0V, VIH = VCC. 6. Refer to Figure 1, ∆ICC vs Frequency (worst case). (Referenced from 15MHz) The ICC increases by 1.5mA per MHz for the frequency range of 16MHz up to 25MHz. The ICC remains at a worst case for the frequency range of 26MHz up to 37MHz. The ICC decreases by 1.0mA per MHz for the frequency range of 14MHz down to 1MHz. The worst case ICC is calculated as follows: – All dedicated inputs are switching. – All OMCs are configured as JK flip-flops in the toggle mode. . .all are toggling. – All 12 outputs are disabled. – The number of product terms connected does not impact the ICC. 7. Refer to Figure 2 for ∆tPD vs output capacitance loading. +30 6 +25 5 4 +15 t PD(ns) I CC(mA) +20 +10 +5 3 2 1 0 –5 0 –10 –1 –15 –2 1 5 10 15 20 f(MHz) 25 30 35 40 20 40 60 80 100 120 140 160 180 200 OUTPUT CAPACITANCE LOADING (pF) Figure 1. ∆ICC vs Frequency (Worst Case) (Referenced from 15MHz) October 22, 1993 0 Figure 2. ∆tPD vs Output Capacitance Loading (Typical) 78 Philips Semiconductors Programmable Logic Devices Product specification CMOS programmable multi-function PLD (42 × 105 × 12) PLC42VA12 AC ELECTRICAL CHARACTERISTICS 0°C ≤ Tamb ≤ +75°C, 4.75V ≤ VCC ≤ 5.25V; R1 = 238Ω, R2 = 170Ω TEST2 SYMBOL PARAMETER FROM PLC42VA12 TO CONDITION (CL (pF)) MIN TYP1 MAX UNIT Set-up Time tIS1 Input; dedicated clock (I, B, M) +/– CK+ 50 23 16 ns tIS2 Input; P-term clock (I, B, M) +/– (I, B, M) +/– 50 20 13 ns tIS3 3 Preload; dedicated clock (M) +/– CK+ 50 10 3.5 ns tIS43 Preload; P-term clock (M) +/– (I, B, M) +/– 50 2 –1.0 ns tIS53 Input through complement array; dedicated clock (I, B, M) +/– CK+ 50 50 34 ns tIS63 Input through complement array; P-term clock (I, B, M) +/– (I, B, M) +/– 50 40 30 ns (I, B, M) +/– (I, B, M) +/– 50 20 35 ns (I, B,) +/– (I, B, M) +/– 50 36 55 ns Propagation Delay tPD1 Propagation Delay tPD2 Propagation Delay with complement array (2 passes) tCKO1 Clock to Output; Dedicated clock CK+ (M) +/– 50 13 17 ns tCKO2 Clock to output; P-term clock (I, B, M) +/– (M) +/– 50 18 27 ns tRP1 Registered operating period; Dedicated clock (tIS1 + tCKO1) (I, B, M) +/– (M) +/– 50 29 40 ns tRP2 Registered operating period; P-term clock (tIS2 + tCKO2) (I, B, M) +/– (M) +/– 50 31 47 ns tRP33 Register preload operating period; Dedicated clock (tIS3 + tCKO1) (M) +/– (M) +/– 50 16.5 27 ns tRP43 Register preload operating period; P-term clock (tIS4 + tCKO2) (M) +/– (M) +/– 50 17 29 ns tRP53 Registered operating period with complement array; dedicated clock (tIS5 + tCKO1) (I, B, M) +/– (M) +/– 50 47 67 ns tRP63 Registered operating period with complement array; P-term clock (tIS6 + tCKO2) (I, B, M) +/– (M) +/– 50 48 67 ns tOE1 Output Enable; from /OE pin4 /OE – (M) +/– 50 10 20 ns tOE2 Output Enable; from P-term4 (I, B, M) +/– (B, M) +/– 50 12.5 25 ns 5 10 20 ns tOD1 Output Disable; from /OE pin4 /OE + Outputs disabled tOD2 Output Disable; from P-term4 (I, B, M) +/– Outputs disabled 5 14.5 25 ns tPRO3 Preset to Output (I, B, M) +/– (M) +/– 50 25 35 ns tPPR3 Power-on Reset (Mn = 1) VCC + (M) +/– 50 15 ns Hold Time tIH1 Input (Dedicated clock) tIH2 Input (P-term clock) tIH33 Input; from Mn (Dedicated clock) tIH4 3 Input; from Mn (P-term clock) CK+ (I, B, M) +/– 50 0 –13 ns (I, B, M) +/– (I, B, M) +/– 50 5 –7.5 ns CK+ (M) +/– 50 5 –1.5 ns (I, B, M) +/– (M) +/– 50 10 3.5 ns CK+ CK– 50 10 5 ns Pulse Width tCKH1 Clock High; Dedicated clock tCKL1 Clock Low; Dedicated clock CK– CK+ 50 10 5 ns tCKH2 Clock High; P-term clock CK+ CK– 50 15 7 ns tCKL2 Clock Low; P-term clock CK– CK+ 50 15 7 ns (I, B, M) +/– (I, B, M) +/– 50 30 7 ns tPRH3 Width of preset/reset input pulse Notes on page 80. October 22, 1993 79 Philips Semiconductors Programmable Logic Devices Product specification CMOS programmable multi-function PLD (42 × 105 × 12) PLC42VA12 AC ELECTRICAL CHARACTERISTICS (Continued) 0°C ≤ Tamb ≤ +75°C, 4.75V ≤ VCC ≤ 5.25V; R1 = 238Ω, R2 = 170Ω TEST2 SYMBOL PARAMETER PLC42VA12 FROM TO CONDITION (CL (pF)) MIN TYP1 MAX UNIT Frequency of Operation fCK1 Dedicated clock frequency C+ C+ 50 50 100 MHz fCK2 P-term clock frequency C+ C+ 50 33 71.4 MHz fMAX1 Registered operating frequency; Dedicated clock (tIS1 + tCKO1) (I, B, M) +/– (M) +/– 50 25 34.5 MHz fMAX2 Registered operating frequency; P-term clock (tIS2 + tCKO2) (I, B, M) +/– (M) +/– 50 21.3 32.3 MHz fMAX33 Register preload operating frequency; Dedicated clock (tIS3 + tCKO1) (M) +/– (M) +/– 50 37 60.6 MHz fMAX43 Register preload operating frequency; P-term clock (tIS4 + tCKO2) (M) +/– (M) +/– 50 34.5 58.8 MHz fMAX53 Registered operating frequency with complement array; Dedicated clock (tIS5 + tCKO1) (I, B, M) +/– (M) +/– 50 14.9 21.3 MHz fMAX63 Registered operating frequency with complement array; P-term clock (tIS6 + tCKO2) (I, B, M) +/– (M) +/– 50 14.9 20.8 MHz NOTES: 1. All typical values are at VCC = 5V, Tamb = +25°C. These limits are not tested/guaranteed. 2. Refer also to AC Test Conditions (Test Load Circuit). 3. These limits are not tested, but are characterized periodically and are guaranteed by design. 4. For 3-State output; output enable times are tested with CL = 50pF to the 1.5V level, and S1 is open for high-impedance to High tests and closed for high-impedance to Low tests. Output disable times are tested with CL = 5pF. High-to-High impedance tests are made to an output voltage of VT = (VOH – 0.5V) with S1 open, and Low-to-High impedance tests are made to the VT = (VOL + 0.5V) level with S1 closed. BLOCK DIAGRAM 65 X 105 PROGRAMMABLE AND ARRAY I1 64 LOGIC TERMS 41 CONTROL TERMS I8 CK J P COMPLEMENT MUX JK/D R L D OMC (10) 64 X 32 PROGRAMMABLE OR ARRAY K BYPASS MUX I0/CLK I9/OE OE Q Q MUX M0 – M9 B0 – B1 October 22, 1993 80 Philips Semiconductors Programmable Logic Devices Product specification CMOS programmable multi-function PLD (42 × 105 × 12) PLC42VA12 OUTPUT MACRO CELL (OMC) FROM AND ARRAY FC CONTROL FROM OR ARRAY LOAD PRESET RESET P J CLOCK 0 SELECT MUX 1 R CK JK/D MUX FROM OR ARRAY K Q 1 O E OE 0 1 OUTPUT ENABLE SELECT MUX M CLK M OUTPUT SELECT MUX TO AND ARRAY FROM OR ARRAY CK (REGISTER BYPASS) TO AND ARRAY Output Macro Cell Configuration Philips Semiconductors unique Output Macro Cell design represents a significant advancement in the configurability of multi-function Programmable Logic Devices. The PLC42VA12 has 10 programmable Output Macro Cells. Each can be individually programmed in any of 5 basic configurations: • Dedicated I/O (combinatorial) with feedback to AND array • • • • Dedicated Input Combinatorial I/O with feedback and Buried Register with feedback (register bypass) Registered Input Registered Output with feedback Each of the registered options can be further customized as J-K type or D-type, with either an internally derived clock (from the AND array) or clocked from an external source. With these additional programmable options, it is possible to program each Output Macro Cell in any one of 14 different configurations. October 22, 1993 These 14 configurations, combined with the fully programmable OR array, make the PLC42VA12 the most versatile and silicon efficient of all the Output Macro Cell-type PLDs. source – make it possible to design synchronous state machine functions, event-driven state machine functions and combinatorial (asynchronous) functions all on the same chip. The most significant Output Macro Cell (OMC) feature is the implementation of the register bypass function. Any of the 10 J-K/D registers can be individually bypassed, thus creating a combinatorial I/O path from the AND array to the output pin. Unlike other Output Macro Cell-type devices, the register in the OMC is fully functional as a buried register. Furthermore, both the combinatorial I/O and the buried register have separate input paths (from the AND array) and separate feedback paths (to the AND array). This feature provides the capability to operate the buried register independently from the combinatorial I/O. Sophisticated control functions support individual OE control and Reset functions from the AND array. OE control is also available from the I9/OE pin. Register Preset and Load functions are controlled from the AND array, in 2 banks of 4 for OMCs M1 – M8. Output Macro Cells M0 and M9 have individual Preset and Load Control terms. The PLC42VA12 is ideally suited for both synchronous and asynchronous logic functions. Eleven clock sources – 10 driven from the AND array and one from an external 81 Output Polarity for the combinatorial I/O paths is configurable via 12 programmable EX-OR gates. The output of each register can be configured as inverting (active Low) or non-inverting (active High) via manipulation of the logic equations. The output of each buried register can also be configured as inverting or non-inverting via the input buffer which feeds back to the AND array. Philips Semiconductors Programmable Logic Devices Product specification CMOS programmable multi-function PLD (42 × 105 × 12) PLC42VA12 OUTPUT MACRO CELL PROGRAMMABLE OPTIONS OMC Programmable Options For purposes of programming, the Output Macro Cell should be considered to be partitioned into five separate blocks. As shown in the drawing titled “Output Macro Cell Programmable Options”, the programmable blocks are: Register Select Options, Polarity Options, Clock Options, OMC Configuration Options and Output Enable Control Options. OUTPUT MACRO CELL REGISTER SELECT OPTIONS CLOCK OPTIONS OMC CONFIGURATION OPTIONS OUTPUT ENABLE CONTROL OPTIONS POLARITY OPTIONS OUTPUT M There is one programmable location associated with each block except the Output Enable Control block which has two programmable fuse locations per OMC. The following drawings detail the options associated with each programmable block. The associated programming codes are also included. The table titled “Output Macro Cell Configurations” (page 87) lists all the possible combinations of the five programmable options. ARCHITECTURAL OPTIONS REGISTER SELECT OPTIONS FROM OR ARRAY P R P R CK D Q Register Select Options Each OMC Register can be configured either as a dedicated D-type or a J-K flip-flop. The Flip-Flop Control term, Fc, provides the option to control each Register dynamically—switching from D-type to J-K type, based on the Fc control signal. CLOCK OPTIONS OMC CONFIG. OPTIONS OUTPUT CONTROL OPTIONS FROM AND ARRAY REGISTER MODE (D or JK) CODE D-TYPE A FC CONTROL P-TERM L P R P R CK J CLOCK OPTIONS FROM OR ARRAY K Q OMC CONFIG. OPTIONS OUTPUT CONTROL OPTIONS FROM AND ARRAY REGISTER MODE (D or JK) CODE JK-TYPE • FC CONTROL P-TERM – Notes on page 87. October 22, 1993 82 Register Preset and Reset are controlled from the AND array. Each OMC has an individual Reset Control term (RMn). The Register Preset function is controlled in two banks of 4 for OMCs M1 – M3 and M4 – M8 (via the control terms PA and PB). OMCs M0 and M9 have individual control terms (PM0 and PM9 respectively). Philips Semiconductors Programmable Logic Devices Product specification CMOS programmable multi-function PLD (42 × 105 × 12) PLC42VA12 REGISTER SELECT OPTIONS (Continued) P R P R P R CK FC P FROM OR ARRAY R CK CLOCK OPTIONS D J CLOCK OPTIONS FROM OR ARRAY OMC CONFIG. OPTIONS Q OUTPUT CONTROL OPTIONS K Q OMC CONFIG. OPTIONS OUTPUT CONTROL OPTIONS FROM AND ARRAY FROM AND ARRAY REGISTER MODE (D or JK) FC = LOW FC = HIGH POLARITY OPTIONS (for Combinatorial I/O Configurations Only1) FROM OR ARRAY OMC CONFIG. OPTIONS OUTPUT SELECT OPTIONS POLARITY CODE ACTIVE-HIGH (NON-INVERTING) H4 FROM OR ARRAY OMC CONFIG. OPTIONS POLARITY CODE ACTIVE-LOW (INVERTING) L4 L or H Polarity Options If an OMC is configured as a Registered Output, /Q is propagated to the output pin. Note that either Q or /Q can be fedback to the AND array by manipulating the feedback logic equations. (TRUE or COMPLEMENT). M CLOCK OPTIONS Clock Options REGISTER SELECT OPTIONS D (OR J) CK CLK OPTIONS CODE EXTERNAL CLOCK (FROM PIN 1) A CLK FROM OR ARRAY (K) Q OMC CONFIG. OPTIONS REGISTER SELECT OPTIONS CK CLK OPTIONS CODE P-TERM CLOCK • D (OR J) CK FROM OR ARRAY (K) Q OMC CONFIG. OPTIONS In the unprogrammed state, all Output Macro Cell clock sources are connected to the External Clock pin (I0/CLK pin 1). Each OMC can be individually programmed such that its P-term Clock (CKn) is enabled, thus disabling it from the External Clock and providing event-driven clocking capability. This feature supports multiple state machines, clocked at several different rates, all on one chip, or the ability to collect large amounts of random logic, including 10 separately clocked flip-flops. OUTPUT CONTROL OPTIONS TO AND ARRAY OUTPUT CONTROL OPTIONS TO AND ARRAY Notes on page 87. October 22, 1993 A FC CONTROL P-TERM When an OMC is configured as a Combinatorial I/O with Buried Register, the polarity of the combinatorial path can be programmed as Active-High or Active-Low. A configurable EX-OR gate provides polarity control. M OUTPUT CONTROL OPTIONS CODE DYNAMICALLY CONTROLLABLE 83 Philips Semiconductors Programmable Logic Devices Product specification CMOS programmable multi-function PLD (42 × 105 × 12) PLC42VA12 OUTPUT MACRO CELL CONFIGURATION OPTIONS REGISTER SELECT OPTIONS CLOCK OPTIONS D (OR J) CK REGISTER SELECT OPTIONS FROM OR ARRAY CLOCK OPTIONS D (OR J) CK (K) TO AND ARRAY FROM OR ARRAY OMC CONFIG. OPTIONS Q (K) M COMBINATORIAL OPTIONS TO AND ARRAY FROM OR ARRAY REGISTERED OUTPUT (D or JK) A OMC CONFIGURATION CODE COMBINATORIAL OUTPUT WITH BURIED REGISTER (D or JK) • M OMC Configuration Options L M CK CLOCK OPTIONS Q OUTPUT CONTROL OPTIONS TO AND ARRAY OMC CONFIGURATION REGISTERED INPUT LOAD CONTROL P-TERM CODE A or •5 H6 Each OMC can be configured as a Registered Output with feedback, a Registered Input or a Combinatorial I/O with Buried Register. Dedicated Input and dedicated I/O configurations are also possible. When the Combinatorial I/O option is selected, (the Register Bypass option), the Buried Register remains 100% functional, with its own inputs from the AND array and a separate feedback path. This unique feature is ideal for designing any type of state machine; synchronous Mealy-types that require both Buried and Output Registers, or asynchronous Mealy-types that require buried registers and combinatorial output functions. Both synchronous and asynchronous Moore-type state machines can also be easily accommodated with the flexible OMC structure. Notes on page 87. October 22, 1993 OUTPUT CONTROL OPTIONS CODE OMC CONFIGURATION D Q 84 Note that an OMC can be configured as either a Combinatorial I/O (with Buried Register) or a Registered Output with feedback and it can still be used as a Registered Input. By disabling the outputs via any OE control function, the M pin can be used as an input. When the Load Control P-term is asserted HIGH, the register is preloaded from the M pin(s). When the LC P-term is Active-Low and the output is enabled, the OMC will again function as configured (either a combinatorial I/O or a registered output with feedback). This feature is suited for synchronizing input signals prior to commencing a state sequence. Philips Semiconductors Programmable Logic Devices Product specification CMOS programmable multi-function PLD (42 × 105 × 12) PLC42VA12 OUTPUT CONTROL OPTIONS Output Enable Control Options Similar to the Clock Options, the Output Enable Control for each OMC can be connected either to an external source (I9/OE, pin 13) or controlled from the AND array (P-terms DMn). Each Output can also be permanently enabled. OE OMC CONFIG. OPTIONS M Output Enable control for the two bi-directional I/O (B pins 10 and 11) is from the AND array only (P-terms DB0 and DB1 respectively). TO AND ARRAY OE CONTROL FUSE CODE En FUSE CODE FROM OE PIN A FROM OE PIN A DM OMC CONFIG. OPTIONS OMC CONFIG. OPTIONS M M TO AND ARRAY TO AND ARRAY OE FUSE CODE FROM P-TERM CONTROL • En FUSE CODE OE CONTROL FUSE CODE En FUSE CODE FROM P-TERM CONTROL A or 0 ALWAYS ENABLED A ALWAYS ENABLED 0 COMPLEMENT ARRAY DETAIL P63 P62 P61 Complement Array Detail P1 P0 FC LMn PMn RMn The complement array is a special sequencer feature that is often used for detecting illegal states. It is also ideal for generating IF-THEN-ELSE logic statements with a minimum number of product terms. The concept is deceptively simple. If you subscribe to the theory that the expressions (/A * /B * /C) and (A + B + C) are equivalent, you will begin to see the value of this single term NOR array. C0 A B D E C0 TO OR ARRAY TO OMCs AND BIDIRECTIONAL I/O Notes on page 87. October 22, 1993 85 The complement array is a single OR gate with inputs from the AND array. The output of the complement array is inverted and fedback to the AND array (NOR function). The output of the array will be LOW if any one or more of the AND terms connected to it are active (HIGH). If, however, all the connected terms are inactive (LOW), which is a classic unknown state, the output of the complement array will be HIGH. Consider the product terms A, B and D that represent defined states. They are also connected to the input of the complement array. When the condition (not A and not B and not D) exists, the Complement Array will detect this and propagate an Active-High signal to the AND array. This signal can be connected to product term E, which could be used in turn to preset the state machine to known state. Without the complement array, one would have to generate product terms for all unknown or illegal states. With very complex state machines, such an approach can be prohibitive, both in terms of time and wasted resources. Philips Semiconductors Programmable Logic Devices Product specification CMOS programmable multi-function PLD (42 × 105 × 12) LOGIC PROGRAMMING The PLC42VA12 is fully supported by industry standard (JEDEC compatible) PLD CAD tools, including Philips Semiconductors SNAP design software package. ABEL and CUPL design software packages also support the PLC42VA12 architecture. All packages allow Boolean and state equation entry formats. SNAP, ABEL and CUPL also accept, as input, schematic capture format. PLC42VA12 configuration have been previously defined in the Architectural Options section. PLC42VA12 logic designs can also be generated using the program table entry format, which is detailed on the following pages. This program table entry format is supported by SNAP only. PROGRAMMING AND SOFTWARE SUPPORT To implement the desired logic functions, the state of each logic variable from logic equations (I, B, O, P, etc.) is assigned a symbol. The symbols for TRUE, COMPLEMENT, INACTIVE, PRESET, etc., are defined below. Symbols for OMC Refer to Section 9 (Development Software) and Section 10 (Third-party Programmer/ Software Support) of this data handbook for additional information. LOGIC IMPLEMENTATION “AND” ARRAY – (I), (B), (Qp) I, B, Q I, B, Q I, B, Q I, B, Q I, B, Q I, B, Q I, B, Q (T, FC, L, P, R, D)n I, B, Q I, B, Q I, B, Q I, B, Q (T, FC, L, P, R, D)n I, B, Q (T, FC, L, P, R, D)n (T, FC, L, P, R, D)n STATE CODE STATE CODE STATE CODE STATE CODE INACTIVE1 O I, B, Q H I, B, Q L DON’T CARE – “COMPLEMENT” ARRAY – (C) C C C C C C C C (Tn, FC) (Tn, FC) (Tn, FC) (Tn, FC) ACTION CODE ACTION CODE ACTION CODE ACTION CODE INACTIVE1, 3 O GENERATE A PROPAGATE • TRANSPARENT – “OR” ARRAY – (J-K Type) Tn Tn J J Q M = DISABLED Tn Tn Q J M = DISABLED K K J Q M = DISABLED Q M = DISABLED K K ACTION CODE ACTION CODE ACTION CODE ACTION CODE TOGGLE O SET H RESET L HOLD – “OR” ARRAY “OR” ARRAY – (D-Type) Tn Tn Tn Tn J P, R, L (OR B) P, R, L (OR B) Q M = ENABLED J K Tn STATUS CODE Tn STATUS ACTIVE1 A INACTIVE CODE • Notes on page 87. ABEL is a trademark of Data I/O Corp. CUPL is a trademark of Logical Devices, Inc. October 22, 1993 86 Q M = ENABLED K Tn STATUS CODE Tn STATUS ACTIVE (SET) A INACTIVE (RESET) CODE • Philips Semiconductors Programmable Logic Devices Product specification CMOS programmable multi-function PLD (42 × 105 × 12) PLC42VA12 LOGIC IMPLEMENTATION (Continued) OUTPUT MACRO CELL CONFIGURATIONS PROGRAMMING CODES OUTPUT MACRO CELL CONFIGURATION REGISTER SELECT FUSE OMC CONFIGURATION FUSE POLARITY FUSE CLOCK FUSE H or L A H or L • H or L A H or L • Combinatorial I/O with Buried D-type register External clock source A P-term clock source A • • • • • • External clock source A A N/A A P-term clock source A A N/A • A N/A A A N/A • A or •5 Optional5 A A or Optional5 • Combinatorial I/O with Buried J-K type register External clock source P-term clock source Registered Output (D-type) with feedback Registered Output (J-K type) with feedback External clock source P-term clock source • • Registered Input (Clocked Preload) with feedback External clock source P-term clock source A A •5 OUTPUT CONTROL FUSES OUTPUT ENABLE CONTROL8 CONFIGURATION OMC controlled by /OE pin Output Enabled Output Disabled OMC controlled by P-term Output Enabled Output Disabled Output always Enabled OE CONTROL FUSE En FUSES A A CONTROL SIGNAL Low High • A or 0 High Low A 0 Not Applicable NOTES: 1. This is the initial (unprogrammed) state of the device. 2. Any gate will be unconditionally inhibited if both the TRUE and COMPLEMENT fuses are left intact. 3. To prevent oscillations, this state is not allowed for Complement Array fuse pairs that are coupled to active product terms. 4. The OMC Configuration fuse must be programmed as Combinatorial I/O in order to make use of the Polarity Option. 5. Regardless of the programmed state of the OMC Configuration fuse, an OMC can be used as a Registered Input. Note that the Load Control P-term must be asserted Active-High. 6. Output must be disabled. 7. Program code definitions: A = Active (unprogrammed fuse) 0, • = Inactive (programmed fuse) – = Don’t Care (both TRUE and COMPLEMENT fuses unprogrammed) H = Active-High connection L = Active-Low connection 8. OE control for B0 and B1 (Pins 10 and 11) is from the AND array only. October 22, 1993 87 Philips Semiconductors Programmable Logic Devices Product specification CMOS programmable multi-function PLD (42 × 105 × 12) PLC42VA12 TIMING DIAGRAMS TIMING DEFINITIONS SYMBOL PARAMETER +3V I, B, M (INPUTS) 1.5V fCK1 fCK2 1.5V 0V tCKH1 tIS2,6 tIH2 +3V P-TERM CK (I, B, M) 1.5V 1.5V tCKH2 1.5V 0V tIS2,6 tCKH2 tCKL1 tCKL2 VOH M (OUTPUTS) VT 1.5V tCKO2 I, B, M, OE TERM OR OE PIN (OUTPUT ENABLE) VOL tOD1,2 tRP2,6 tCKL2 tCKO1 +3V 1.5V tCKO2 Delay between the Positive Transition of P-term Clock and when M Outputs become valid. tRP1 Delay between beginning of Valid Input and when the M outputs become Valid when using External Clock. tRP2 Delay between beginning of Valid Input and when the M outputs become Valid when using P-term Clock. tRP3 Delay between beginning of Valid Input and when the M outputs become Valid when using Preload Inputs (from M pins) and External Clock. tRP4 Delay between beginning of Valid Input and when the M outputs become valid when using Preload inputs (from M pins) and P-term Clock. tRP5 Delay between beginning of Valid Input and when the M outputs become Valid when using Complement Array and External clock. tRP6 Delay between beginning of Valid Input and when the M outputs become Valid when using Complement Array and P-term Clock. 1.5V 0V tOE1,2 Flip-Flop Outputs with P-term Clock +3V I, B, M (INPUTS) 1.5V 1.5V 0V tIS1,5 tIH1 +3V 1.5V EXTERNAL CK 1.5V 1.5V 0V tIS1,5 tCKH1 tCKL1 VOH M (OUTPUTS) VT 1.5V tCKO1 tRP1,5 I, B, M, OE TERM OR OE PIN (OUTPUT ENABLE) VOL tOD1,2 +3V 1.5V 1.5V 0V tOE1,2 Flip-Flop Outputs with External Clock fMAX1 fMAX2 I, B (INPUTS) 1.5V ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ +3V fMAX3 0V tPD B, M (COMBINATORIAL OUTPUTS) VOH 1.5V tOE2 I, B, M, OE TERM OR OE PIN (OUTPUT ENABLE) tOD2 +1.5V fMAX5 Minimum guaranteed Operating Frequency using Complement Array; Dedicated Clock fMAX6 Minimum Operating Frequency using Complement Array; P-term Clock tIH1 Required delay between positive transition of External Clock and end of valid input data. 0V Gated Outputs October 22, 1993 Minimum guaranteed Operating Frequency using Preload; P-term Clock (M pin to M pin) +3V +1.5V 88 Minimum guaranteed Operating Frequency; Dedicated Clock Minimum guaranteed Operating Frequency; P-term Clock Minimum guaranteed Operating Frequency using Preload; Dedicated Clock (M pin to M pin) fMAX4 VT VOL Clock Frequency; External Clock Clock Frequency; P-term Clock Width of Input Clock Pulse; External Clock Width of Input Clock Pulse; P-term Clock Interval between Clock pulses; External Clock Interval between Clock Pulses; P-term Clock Delay between the Positive Transition of External Clock and when M Outputs become valid. Philips Semiconductors Programmable Logic Devices Product specification CMOS programmable multi-function PLD (42 × 105 × 12) PLC42VA12 TIMING DIAGRAMS (Continued) I, B (LOAD SELECT) TIMING DEFINITIONS (Continued) +3V 1.5V 0V I, B, OE TERM OR OE PIN (OUTPUT ENABLE) SYMBOL PARAMETER 1.5V tIH2 Required delay between positive transition of P-term Clock and end of valid input data. tIH3 Required delay between positive transition of External Clock and end of valid input data when using Preload Inputs (from M pins). tIH4 Required delay between positive transition of P-term Clock and end of valid input data when using Preload Inputs (from M pins). tIS1 Required delay between beginning of valid input and positive transition of External Clock. tIS2 Required delay between beginning of valid input and positive transition of P-term Clock input. tIS3 Required delay between beginning of valid Preload input (from M pins) and positive transition of External Clock. tIS4 Required delay between beginning of valid Preload input (from M pins) and positive transition of P-term Clock input. tIS5 Required delay between beginning of valid input through Complement Array and positive transition of External Clock. tIS6 Required delay between beginning of valid input through Complement Array and positive transition of P-term Clock input. tOE1 Delay between beginning of Output Enable signal (Low) from /OE pin and when Outputs become valid. tOE2 Delay between beginning of Output Enable signal (High or Low) from OE P-term and when Outputs become valid. tOD1 Delay between beginning of Output Enable signal (HIGH) from /OE pin and when Outputs become disabled. tOD2 Delay between beginning of Output Enable signal (High or Low) from OE P-term and when Outputs become disabled. tPD Delay between beginning of valid input and when the Outputs become valid (Combinatorial Path). tPRH Width of Preset/Reset Pulse. tPRO Delay between beginning of valid Preset/Reset Input and when the registered Outputs become Preset (“1”) or Reset (“0”). tPPR Delay between VCC (after power-up) and when flip-flops become Reset to “0”. Note: Signal at Output (M pin) will be inverted. +3V 1.5V 1.5V 0V tOE1,2 L +3V M (INPUT) 1.5V (FORCED DIN) VT ÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇ tOD1,2 tIS3,4 tIH3,4 0V tCKL P-TERM OR EXTERNAL CK 0V tCKH tIH3,4 Q +3V (DIN) Flip-Flop Input Mode (Preload) I, B, M (INPUTS) ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ +3V 1.5V P-TERM OR EXTERNAL CK 0V +3V 1.5V tIS* PRESET/RESET (I, B, M INPUTS) tIS 1.5V 0V tCKO +3V 1.5V 0V tPRH (PRESET) (RESET) Q tPRO M (OUTPUTS) (RESET) (PRESET) 1.5V 1.5V VOH VOL *Preset and Reset functions override Clock. However, M outputs may glitch with the first positive Clock Edge if tIS cannot be guaranteed by the user. Asynchronous Preset/Reset ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ +5V 4.5V VCC 0V tPPR M (OUTPUTS) I, B, M (INPUTS) 1.5V VOH 1.5V VOL tCKO1,2 +3V 1.5V 1.5V 0V tIH tIS +3V 1.5V P-TERM OR EXTERNAL CK tIS 1.5V tCKH 1.5V 0V tCKL tCK1,2 Power-On Reset October 22, 1993 89 Philips Semiconductors Programmable Logic Devices Product specification CMOS programmable multi-function PLD (42 × 105 × 12) LOGIC FUNCTION Q3 Q2 Q1 Q0 1 0 1 0 PLC42VA12 UNPROGRAMMED STATE PRESENT STATE SR ⋅ ⋅ ⋅ A B C ... STATE REGISTER A factory shipped unprogrammed device is configured such that all cells are in a conductive state. The following are: 0 0 0 1 Sn + 1 NEXT STATE ⋅ ⋅ ACTIVE: – OR array logic terms – Output Macro Cells M1 – M8; ⋅ ⋅ ⋅ SET Q0: J0 = (Q2 Q1 Q0) A B C . . . K0 = 0 RESET Q1: J1 = 0 K1 = (Q3 Q2 Q1 Q0) A B C . . . ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ ⋅ HOLD Q2: J2 = 0 K2 = 0 RESET Q3: J3 = (Q3 Q2 Q1 Q0) A B C . . . K3 = (Q3 Q2 Q1 Q0) A B C . . . NOTE: Similar logic functions are applicable for D mode flip-flops. • D-type registered outputs (D = 0) – External clock path – Inputs: B0, B1, M0, M9 INACTIVE: – AND array logic and control terms (except flip-flop mode control term, FC) – Bidirectional I/O (B0, B1); • • Inputs are active. Outputs are 3-Stated via the OE P-terms, D0 and D1. D-type registers (D = 0). – Output Macro Cells M0 and M9; • FLIP-FLOP TRUTH TABLE OE Ln CKn Pn Rn J K Q L X X X X X X L H L X X H L X X H L L X X L H X X L H L L ↑ L L L L Q Q L L ↑ L L L H L H L L ↑ L L H L H L L L ↑ L L H H Q Q H H ↑ L L L H L H* H H ↑ L L H L H L* +10V X ↑ X X L H L H** H M Hi-Z Bidirectional I/O, 3-Stated via the OE P-terms, DM0 and DM9. The inputs are active. – P-term clocks – Complement Array – J-K Flip-Flop mode PROGRAMMING AND SOFTWARE SUPPORT Refer to Section 9 (Development Software) and Section 10 (Third-party Programmer/ Software Support) in this data handbook for additional information. ERASURE CHARACTERISTICS (For Quartz Window Packages Only) The erasure characteristics of the PLC42VA12 devices are such that erasure begins to occur upon exposure to light with wavelength shorter than approximately 4000 Angstroms (Å). It should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000 – 4000Å range. Data shows that constant exposure to room level fluorescent lighting could erase a typical PLC42VA12 in approximately three years, while it would take approximately one week to cause erasure when exposed to direct sunlight. If the PLC42VA12 is to be exposed to these types of lighting conditions for extended periods of time, opaque labels should be placed over the window to prevent unintentional erasure. The recommended erasure procedure for the PLC42VA12 is exposure to shortwave ultraviolet light which has a wavelength of 2537 Angstroms (Å). The integrated dose (i.e., UV intensity × exposure time) for erasure should be a minimum of 15Wsec/cm2. The erasure time with this dosage is approximately 30 to 35 minutes using an ultraviolet lamp with a 12,000µW/cm2 power rating. The device should be placed within one inch of the lamp tubes during erasure. The maximum integrated dose a CMOS EPLD can be exposed to without damage is 7258Wsec/cm2 (1 week @ 12000µW/cm2). Exposure of these CMOS EPLDs to high intensity UV light for longer periods may cause permanent damage. The maximum number of guaranteed erase/write cycles is 50. Data retentions exceeds 20 years. X ↑ X X H L H L** NOTES: 1. Positive Logic: J-K = T0 + T1 + T2 + ... + T31 Tn = C ⋅ (I0 ⋅ I1 ⋅ I2...) ⋅ (Q0 ⋅ Q1...) ⋅ (B0 ⋅ B1...) 2. ↑ denotes transition for Low to High level. 3. X = Don’t care 4. * = Forced at Mn pin for loading the J-K flip-flop in the Input mode. The load control term, Ln must be enabled (HIGH) and the p-terms that are connected to the associated flip-flop must be forced LOW (disabled) during Preload. 5. At P = R = H, Q = H. The final state of Q depends on which is released first. 6. ** = Forced at Fn pin to load J/K flip-flop (Diagnostic mode). October 22, 1993 PLC42VA12 90 Philips Semiconductors Programmable Logic Devices Product specification CMOS programmable multi-function PLD (42 × 105 × 12) PROGRAM TABLE October 22, 1993 91 PLC42VA12 Philips Semiconductors Programmable Logic Devices Product specification CMOS programmable multi-function PLD (42 × 105 × 12) PLC42VA12 SNAP RESOURCE SUMMARY DESIGNATIONS P63 P0 FC Ln Pn Rn CKn LMn PMn RMn CKn DMn DMn DBn I9/OE I1 – I8 DIN42 NIN42 X8 I0/CK NOR AND ANDFC CAND X2 X1 X2 X8 X8 X2 X2 X2 X2 X8 X2 X2 NTIM42 CLK CONTROL DTIM42 OR P J X8 R CK CK42 X8 X8 K OR En (X2) JKFFPR42 POLARITY OEn Q OMC CONFIG. OEBUFF X8 OENAND X8 EXOR42 M1 – M8 TNOO42 CLK CONTROL OR P J X2 R CK CK42 X2 X2 K OR En (X2) OEn Q JKFFPR42 OMC CONFIG. X2 OENAND OEBUFF M0, M9 POLARITY X2 EXOR42 TNOU42 B0 – B1 POLARITY X2 EXOR42 October 22, 1993 92 TNOU42