Philips Semiconductors Programmable Logic Devices Product specification PAL devices 16L8, 16R8, 16R6, 16R4 PLUS16R8D/-7 SERIES FEATURES DESCRIPTION • Ultra high-speed The Philips Semiconductors PLUS16XX family consists of ultra high-speed 7.5ns and 10ns versions of Series 20 PAL devices. – tPD = 7.5ns and fMAX = 74MHz for the PLUS16R8-7 Series The PLUS16XX family is 100% functional and pin-compatible with the 16L8, 16R8, 16R6, and 16R4 Series devices. – tPD = 10ns and fMAX = 60 MHz for the PLUS16R8D Series • 100% functionally and pin-for-pin The sum of products (AND-OR) architecture is comprised of 64 programmable AND gates and 8 fixed OR gates. Multiple bidirectional pins provide variable input/output pin ratios. Individual 3-State control of all outputs and registers with feedback (R8, R6, R4) is also provided. Proprietary designs can be protected by programming the security fuse. compatible with industry standard 20-pin PAL ICs • Power-up reset function to enhance state machine design and testability • Design support provided via SNAP and other CAD tools for Series 20 PAL devices • Field-programmable on industry standard The PLUS16R8, R6, and R4 have D-type flip-flops which are loaded on the Low-to-High transition of the clock input. programmers • Security fuse • Individual 3-State control of all outputs DEVICE NUMBER In order to facilitate state machine design and testing, a power-up reset function has been incorporated into these devices to reset all internal registers to Active-Low after a specific period of time. The Philips Semiconductors State-of-the-Art oxide isolation Bipolar fabrication process is employed to achieve high-performance operation. The PLUS16XX family of devices are field programmable, enabling the user to quickly generate custom patterns using standard programming equipment. See the programmer chart for qualified programmers. The SNAP software package from Philips Semiconductors supports easy design entry for the PLUS16XX series as well as other PLD devices from Philips Semiconductors. The PLUS16XX series are also supported by other standard CAD tools for PAL-type devices. Order codes are listed in the Ordering Information table. DEDICATED INPUTS COMBINATORIAL OUTPUTS REGISTERED OUTPUTS PLUS16L8 10 8 (6 I/O) 0 PLUS16R8 8 0 8 PLUS16R6 8 2 I/O 6 PLUS16R4 8 4 I/O 4 ORDERING INFORMATION DESCRIPTION ORDER CODE DRAWING NUMBER 20-Pin Plastic Dual-In-Line 300mil-wide PLUS16R8DN PLUS16R6DN PLUS16R4DN PLUS16L8DN PLUS16R8–7N PLUS16R6–7N PLUS16R4–7N PLUS16L8–7N 0408B 20-Pin Plastic Leaded Chip Carrier (PLCC) PLUS16R8DA PLUS16R6DA PLUS16R4DA PLUS16L8DA PLUS16R8–7A PLUS16R6–7A PLUS16R4–7A PLUS16L8–7A 0400E NOTE: The PLUS16XX series of devices are also processed to military requirements for operation over the military temperature range. For specifications and ordering information, consult the Philips Semiconductors Military Data Book. PAL is a registered trademark of Advanced Micro Devices, Inc. September 10, 1993 36 853–1358 10777 Philips Semiconductors Programmable Logic Devices Product specification PAL devices 16L8, 16R8, 16R6, 16R4 PLUS16R8D/-7 SERIES PIN CONFIGURATIONS PLUS16L8 PLUS16R8 I0 1 20 VCC CLK 1 20 VCC I1 2 19 O7 I0 2 DQ Q 19 Q7 I2 3 18 B6 I1 3 DQ Q 18 Q6 I3 4 17 B5 I2 4 DQ Q 17 Q5 I4 5 16 B4 I3 5 DQ Q 16 Q4 I5 6 15 B3 I4 6 DQ Q 15 Q3 I6 7 14 B2 I5 7 DQ Q 14 Q2 I7 8 13 B1 I6 8 DQ Q 13 Q1 I8 9 12 O0 I7 9 DQ Q 12 Q0 10 11 I9 11 OE GND AND OR ARRAY AND OR ARRAY GND 10 PLUS16L8 I3 4 I4 5 I5 6 I6 I7 I2 I1 3 2 PLUS16R8 I0 VCC O7 1 20 19 18 B6 I2 4 17 B5 I1 I0 3 2 CLK VCC Q7 1 20 19 18 Q6 I3 5 16 B4 I4 6 7 15 B3 I5 7 15 Q3 8 14 B2 I6 8 14 Q2 AND OR ARRAY 9 10 OUTPUTS AND OR ARRAY 11 12 13 9 I8 GND I9 O0 B1 I7 17 Q5 OUTPUTS 11 12 13 GND OE Q0 Q1 10 16 Q4 SYMBOL I O Q B CLK OE DESCRIPTION Dedicated Input Dedicated combinatorial Output Registered output Bidirectional (input/output) Clock input Output Enable SYMBOL I O Q B CLK OE DESCRIPTION Dedicated Input Dedicated combinatorial Output Registered output Bidirectional (input/output) Clock input Output Enable VCC GND Supply Voltage Ground VCC GND Supply Voltage Ground September 10, 1993 37 Philips Semiconductors Programmable Logic Devices Product specification PAL devices 16L8, 16R8, 16R6, 16R4 PLUS16R8D/-7 SERIES PIN CONFIGURATIONS PLUS16R6 PLUS16R4 CLK 1 20 VCC I0 2 19 I1 3 DQ Q I2 4 I3 5 I4 CLK 1 20 VCC B7 I0 2 19 B7 18 Q6 I1 3 18 B6 DQ Q 17 Q5 I2 4 D Q Q 17 Q5 DQ Q 16 Q4 I3 5 D Q Q 16 Q4 6 DQ Q 15 Q3 I4 6 D Q Q 15 Q3 I5 7 DQ Q 14 Q2 I5 7 D Q Q 14 Q2 I6 8 DQ Q 13 Q1 I6 8 13 B1 I7 9 12 B0 I7 9 12 B0 11 OE 11 OE AND OR ARRAY GND 10 AND OR ARRAY GND 10 PLUS16R4 PLUS16R6 I2 4 I3 5 I4 6 I5 I6 I1 I0 3 2 CLK VCC B7 1 20 19 18 Q6 I2 4 17 Q5 I1 I0 3 2 CLK VCC B7 1 20 19 18 B6 I3 5 16 Q4 I4 6 7 15 Q3 I5 7 15 Q3 8 14 Q2 I6 8 14 Q2 AND OR ARRAY 9 I7 OUTPUTS AND OR ARRAY 11 12 13 9 GND OE B0 Q1 I7 10 17 Q5 OUTPUTS 11 12 13 GND OE B0 B1 10 16 Q4 SYMBOL I O Q B CLK OE DESCRIPTION Dedicated Input Dedicated combinatorial Output Registered output Bidirectional (input/output) Clock input Output Enable SYMBOL I O Q B CLK OE DESCRIPTION Dedicated Input Dedicated combinatorial Output Registered output Bidirectional (input/output) Clock input Output Enable VCC GND Supply Voltage Ground VCC GND Supply Voltage Ground September 10, 1993 38 Philips Semiconductors Programmable Logic Devices Product specification PAL devices 16L8, 16R8, 16R6, 16R4 PLUS16R8D/-7 SERIES LOGIC DIAGRAM I0 PLUS16L8 1 0 19 O7 18 B6 17 B5 16 B4 15 B3 14 B2 13 B1 12 O0 11 I9 7 I1 2 8 15 I2 3 16 23 I3 4 PRODUCT TERMS (0–63) 24 31 I4 5 32 39 I5 6 40 47 I6 7 48 55 I7 8 56 63 I8 9 0 31 INPUTS (0–31) NOTES: 1. All unprogrammed or virgin “AND” gate locations are pulled to logic “0”. 2. Programmable connections. September 10, 1993 39 Philips Semiconductors Programmable Logic Devices Product specification PAL devices 16L8, 16R8, 16R6, 16R4 PLUS16R8D/-7 SERIES LOGIC DIAGRAM CLK PLUS16R8 1 0 D Q Q7 18 Q6 17 Q5 16 Q4 15 Q3 14 Q2 13 Q1 12 Q0 11 OE Q 7 I0 19 2 8 D Q Q 15 I1 3 16 D Q Q 23 I2 4 PRODUCT TERMS (0–63) 24 D Q Q 31 I3 5 32 D Q Q 39 I4 6 40 D Q Q 47 I5 7 48 D Q Q 55 I6 8 56 D Q Q 63 I7 9 0 31 INPUTS (0–31) NOTES: 1. All unprogrammed or virgin “AND” gate locations are pulled to logic “0”. 2. Programmable connections. September 10, 1993 40 Philips Semiconductors Programmable Logic Devices Product specification PAL devices 16L8, 16R8, 16R6, 16R4 PLUS16R8D/-7 SERIES LOGIC DIAGRAM CLK PLUS16R6 1 0 19 B7 18 Q6 17 Q5 16 Q4 15 Q3 14 Q2 13 Q1 12 B0 11 OE 7 I0 2 8 D Q Q 15 I1 3 16 D Q Q 23 I2 4 PRODUCT TERMS (0–63) 24 D Q Q 31 I3 5 32 D Q Q 39 I4 6 40 D Q Q 47 I5 7 48 D Q Q 55 I6 8 56 63 I7 9 0 31 INPUTS (0–31) NOTES: 1. All unprogrammed or virgin “AND” gate locations are pulled to logic “0”. 2. Programmable connections. September 10, 1993 41 Philips Semiconductors Programmable Logic Devices Product specification PAL devices 16L8, 16R8, 16R6, 16R4 PLUS16R8D/-7 SERIES LOGIC DIAGRAM CLK PLUS16R4 1 0 19 B7 18 B6 17 Q5 16 Q4 15 Q3 14 Q2 13 B1 12 B0 11 OE 7 I0 2 8 15 I1 3 16 D Q Q 23 I2 4 PRODUCT TERMS (0–63) 24 D Q Q 31 I3 5 32 D Q Q 39 I4 6 40 D Q Q 47 I5 7 48 55 I6 8 56 63 I7 9 0 31 INPUTS (0–31) NOTES: 1. All unprogrammed or virgin “AND” gate locations are pulled to logic “0”. 2. Programmable connections. September 10, 1993 42 Philips Semiconductors Programmable Logic Devices Product specification PAL devices 16L8, 16R8, 16R6, 16R4 FUNCTIONAL DESCRIPTIONS The PLUS16XX series utilizes the familiar sum-of-products implementation consisting of a programmable AND array and a fixed OR array. These devices are capable of replacing an equivalent of four or more SSI/MSI integrated circuits to reduce package count and board area occupancy, consequently improving reliability and design cycle over Standard Cell or gate array options. By programming the security fuse, proprietary designs can be protected from duplication. The PLUS16XX series consists of four PAL-type devices. Depending on the particular device type, there are a variable number of combinatorial and registered outputs available to the designer. The PLUS16L8 is a combinatorial part with 8 user configurable outputs (6 bidirectional), while the other three devices, PLUS16R8, PLUS16R6, PLUS16R4, have respectively 8, 6, and 4 output registers. 3-State Outputs The PLUS16XX series devices also feature 3-State output buffers on each output pin which can be programmed for individual control of all outputs. The registered outputs (Qn) are controlled by an external input (/OE), and the combinatorial outputs (On, Bn) PLUS16R8D/-7 SERIES use a product term to control the enable function. Programmable Bidirectional Pins The PLUS16XX products feature variable Input/Output ratios. In addition to 8 dedicated inputs, each combinatorial output pin of the registered devices can be individually programmed as an input or output. The PLUS16L8 provides 10 dedicated inputs and 6 Bidirectional I/O lines that can be individually configured as inputs or outputs. Output Registers The PLUS16R8 has 8 output registers, the 16R6 has 6, and the 16R4 has 4. Each output register is a D-type flip-flop which is loaded on the Low-to-High transition of the clock input. These output registers are capable of feeding the outputs of the registers back into the array to facilitate design of synchronous state machines. series are supported by SLICE, the PC-based software development tool from Philips Semiconductors. The PLUS16XX family of devices are also supported by standard CAD tools for PAL devices, including ABEL and CUPL. SLICE is available free of charge to qualified users. Logic Programming The PLUS16XX series is fully supported by industry standard (JEDEC compatible) PLD CAD tools, including Philips Semiconductors SNAP design software package. ABEL CUPL and PALASM 90 design software packages also support the PLUS16XX architecture. All packages allow Boolean and state equation entry formats. SNAP, ABEL and CUPL also accept, as input, schematic capture format. Power-up Reset Programming/Software Support By resetting all flip-flops to a logic Low, as the power is turned on, the PLUS16R8, R6, R4 enhance state machine design and initialization capability. Ref to Section 9 (Development Software) and Section 10. (Third-Party Programmer/ Software Support) of the PLD data handbook for additional information. Software Support Like other Programmable Logic Devices from Philips Semiconductors, the PLUS16XX AND ARRAY – (I, B) I, B I, B I, B I, B I, B I, B I, B I, B STATE INACTIVE1, 2 I, B P, D P, D I, B P, D P, D CODE STATE CODE STATE CODE STATE CODE O I, B H I, B L DON’T CARE – VIRGIN STATE A factory shipped virgin device contains all fusible links intact, such that: 1. All outputs are at “H” polarity. 2. All Pn terms are disabled. 3. All Pn terms are active on all outputs. ABEL is a trademark of Data I/O Corp. CUPL is a trademark of Logical Devices, Inc. PALASM is a registered trademark of AMD Corp. September 10, 1993 I, B I, B 43 Philips Semiconductors Programmable Logic Devices Product specification PAL devices 16L8, 16R8, 16R6, 16R4 PLUS16R8D/-7 SERIES ABSOLUTE MAXIMUM RATINGS1 THERMAL RATINGS TEMPERATURE RATINGS SYMBOL PARAMETER MIN MAX UNIT Maximum junction 150°C VCC Supply voltage –0.5 +7 VDC Maximum ambient 75°C VIN Input voltage –1.2 +8.0 VDC 75°C VOUT Output voltage –0.5 VCC + 0.5V VDC Allowable thermal rise ambient to junction IIN Input currents –30 +30 mA IOUT Output currents +100 mA Tstg Storage temperature range +150 °C –65 NOTE: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied. OPERATING RANGES RATINGS SYMBOL PARAMETER VCC Supply voltage Tamb Operating free–air temperature September 10, 1993 MIN MAX UNIT +4.75 +5.25 VDC 0 +75 °C 44 Philips Semiconductors Programmable Logic Devices Product specification PAL devices 16L8, 16R8, 16R6, 16R4 PLUS16R8D/-7 SERIES DC ELECTRICAL CHARACTERISTICS 0°C ≤ Tamb ≤ +75°C, 4.75 ≤ VCC ≤ 5.25V LIMITS SYMBOL Input PARAMETER TEST CONDITIONS MIN TYP1 MAX UNIT 0.8 V voltage2 VIL Low VCC = MIN VIH High VCC = MAX VIC Clamp 2.0 VCC = MIN, IIN = –18mA V –0.8 –1.5 V 0.5 V Output voltage VCC = MIN, VIN = VIH or VIL VOL Low IOL = 24mA VOH High IOH = –3.2 mA 2.4 V Input current VCC = MAX IIL Low3 VIN = 0.40V –250 µA IIH High3 VIN = 2.7V 25 µA II Maximum input current VIN = VCC = VCCMAX 100 µA Output current VCC = MAX IOZH Output leakage VOUT = 2.7V 100 µA IOZL Output leakage VOUT = 0.4V –100 µA –90 mA 180 mA 4, 5 IOS Short circuit ICC VCC supply current VOUT = 0V VCC = MAX –30 160 Capacitance6 CIN CB Input I/O (B) VCC = 5V VOUT = 2.0V 8 pF VOUT = 2V, f = 1MHz 8 pF NOTES: 1. All typical values are at VCC = 5V, Tamb = +25°C. 2. All voltage values are with respect to network ground terminal. 3. Leakage current for bidirectional pins is the worst case of IIL and IOZL or IIH and IOZH. 4. Test one at a time. 5. Duration of short circuit should not exceed 1 second. 6. These parameters are not 100% tested but periodically sampled. September 10, 1993 45 Philips Semiconductors Programmable Logic Devices Product specification PAL devices 16L8, 16R8, 16R6, 16R4 PLUS16R8D/-7 SERIES AC ELECTRICAL CHARACTERISTICS R1 = 200Ω, R2 = 390Ω, 0°C ≤ Tamb ≤ +75°C, 4.75 ≤ VCC ≤ 5.25V LIMITS SYMBOL PARAMETER FROM TO –7 MIN1 TYP D MAX MIN1 UNIT MAX Pulse Width tCKH Clock High CK+ CK– 5 7 ns tCKL Clock Low CK– CK+ 5 7 ns tCKP Period CK+ CK+ 10 14 ns Setup & Hold time tIS Input Input or feedback CK+ 7 9 ns tIH Input CK+ Input or feedback 0 0 ns 3 Propagation delay tCKO Clock CK± Q± tCKF Clock3 CK± Q tPD Output (16L8, R6, R4)2 I, B Output 3 7.5 tOE1 Output enable4 OE Output enable 3 Output enable4,5 I Output enable Output disable4 OE tOD2 Output disable4,5 tSKW Output tPPR Power-Up Reset tOE2 tOD1 6.5 3 7.5 ns 6.5 ns 3 10 ns 8 3 10 ns 3 10 3 10 ns Output disable 3 8 3 10 ns I Output disable 3 10 3 10 ns Q Q 1 1 ns VCC+ Q+ 10 10 ns 3 Frequency (16R8, R6, R4) fMAX No feedback 1/ (tCKL + tCKH)6 100 71.4 MHz Internal feedback 1/ (tIS + tCKF)6 90 64.5 MHz External feedback 1/ (tIS + tCKO)6 74 60.6 MHz * For definitions of the terms, please refer to the Timing/Frequency Definitions tables. NOTES: 1. CL = 0pF while measuring minimum output delays. 2. tPD test conditions: CL = 50pF (with jig and scope capacitance), VIH = 3V, VIL = 0V, VOH = VOL = 1.5V. 3. tCKF was calculated from measured Internal fMAX. 4. For 3-State output; output enable times are tested with CL = 50pF to the 1.5V level, and S1 is open for high-impedance to High tests and closed for high-impedance to Low tests. Output disable times are tested with CL = 5pF. High-to-High impedance tests are made to an output voltage of VT = (VOH – 0.5V) with S1 open, and Low-to-High impedance tests are made to the VT = (VOL + 0.5V) level with S1 closed. 5. Same function as tOE1 and tOD1, with the difference of using product term control. 6. Not 100% tested, but calculated at initial characterization and at any time a modification in design takes place which may affect the frequency. September 10, 1993 46 Philips Semiconductors Programmable Logic Devices Product specification PAL devices 16L8, 16R8, 16R6, 16R4 PLUS16R8D/-7 SERIES TEST LOAD CIRCUIT VCC C1 +5V S1 C2 R1 B0/O0 I0 Bn/On R2 CL Q0 DUT INPUTS Qn In CLK OE GND NOTE: C1 and C2 are to bypass VCC to GND. OUTPUT REGISTER SKEW 3V CLK 0V 3V Qn (REGISTERED OUTPUT) 1.5V 0V tSKW 3V Qn + 1 (REGISTERED OUTPUT) 1.5V 0V CLOCK TO FEEDBACK PATH CLK tIS D Q tCKF September 10, 1993 47 Philips Semiconductors Programmable Logic Devices Product specification PAL devices 16L8, 16R8, 16R6, 16R4 PLUS16R8D/-7 SERIES TIMING DIAGRAMS1, 2 TIMING DEFINITIONS SYMBOL PARAMETER +3V I, B (INPUTS) 1.5V tCKH Width of input clock pulse. tCKL Interval between clock pulses. +3V tCKP Clock period. 0V tIS Required delay between beginning of valid input and positive transition of clock. tIH Required delay between positive transition of clock and end of valid input data. tCKF Delay between positive transition of clock and when internal Q output of flip-flop becomes valid. tCKO Delay between positive transition of clock and when outputs become valid (with OE Low). tOE1 Delay between beginning of Output Enable Low and when outputs become valid. tOD1 Delay between beginning of Output Enable High and when outputs are in the Off-State. tOE2 Delay between predefined Output Enable High, and when combinational outputs become valid. tOD2 Delay between predefined Output Enable Low and when combinational outputs are in the Off-State. tPPR Delay between VCC (after power-on) and when flip-flop outputs become preset at “1” (internal Q outputs at “0”). tPD Propagation delay between combinational inputs and outputs. 1.5V 0V tIH tIS ÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇ 1.5V CLK tIS 1.5V tCKH Q (REGISTERED OUTPUTS) tCKL tCKP VOH VT 1.5V VOL tOD1 tCKO OE ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ 1.5V +3V 1.5V 1.5V 0V tOE1 Flip-Flop Outputs I, B (INPUTS) ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ 1.5V +3V 0V tPD O, B (COMBINATORIAL OUTPUTS) VOH 1.5V VT VOL tOE2 tOD2 +3V I, B (OUTPUT ENABLE) +1.5V +1.5V 0V Gate Outputs VCC ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ 4.5V VCC 0V tPPR Q (REGISTERED OUTPUTS) VOH 1.5V 1.5V VOL tCKO +3V I, B (INPUTS) 1.5V 1.5V 0V tIH tIS +3V 1.5V CLK 1.5V 1.5V 0V tIS tCKH tCKL tIS+tCKF Power–Up Reset NOTES: 1. Input pulse amplitude is 0V to 3V. 2. Input rise and fall times are 2.5ns. September 10, 1993 48 FREQUENCY DEFINITIONS fMAX No feedback: Determined by the minimum clock period, 1/(tCKL + tCKH). Internal feedback: Determined by the internal delay from flip-flop outputs through the internal feedback and array to the flip-flop inputs, 1/(tIS + tCKF). External feedback: Determined by clock-to-output delay and input setup time, 1/(tIS + tCKO). Philips Semiconductors Programmable Logic Devices Product specification PAL devices 16L8, 16R8, 16R6, 16R4 PLUS16R8D/-7 SERIES OUTPUT REGISTER PRELOAD The output registers can be preloaded to any desired state during device testing. This permits any state to be tested without having to step through the entire state-machine sequence. Each register is preloaded individually by following the steps given below. Step 1. Step 2. Step 3. Step 4. With VCC at 5V and Pin 1 at VIL, raise Pin 11 to VIHH. Apply either VIL or VIH to the output corresponding to the register to be preloaded. Pulse Pin 1, clocking in preload data. Remove output voltage, then lower Pin 11 to VIL. Preload can be verified by observing the voltage level at the output pin. VIHH PIN 11 OE tsu td tw PIN 1 CLOCK VIL td ÉÉ ÉÉ ÇÇ ÉÉ ÇÇ ÉÉ ÇÇ ÇÇ VIH VIL td VOH VIH REGISTERED I/O INPUT VIL NOTE: td = tsu = tw = 100ns to 1000ns. VIHH = 10.25V to 10.75V. Pin number references for DIP package. September 10, 1993 49 OUTPUT VOL Philips Semiconductors Programmable Logic Devices Product specification PAL devices 16L8, 16R8, 16R6, 16R4 PLUS16R8D/-7 SERIES PROGRAMMING/SOFTWARE Refer to Section 9 (Development Software) and Section 10 (Third-Party Programmer/Software Support) of this data handbook for additional information. SNAP RESOURCE SUMMARY DESIGNATIONS I0 – I9 10 DINPAL7 NINPAL7 PROGRAMMABLE AND ARRAY AND 1 1 8 DINPAL7 8 NINPAL7 OR OR NOUTPAL7 NOUTPAL7 B1 – B6 O0, O7 PLUS16L8 CLK I0 – I7 OE 8 CKPAL7 NOEPAL7 DINPAL7 NINPAL7 PROGRAMMABLE AND ARRAY AND NINPAL7 8 DINPAL7 8 OR D Q OR DFFPAL7 D Q Q Q NOUTPAL7 NOUTPAL7 Q7 Q0 PLUS16R8 September 10, 1993 DFFPAL7 50 Philips Semiconductors Programmable Logic Devices Product specification PAL devices 16L8, 16R8, 16R6, 16R4 PLUS16R8D/-7 SERIES SNAP RESOURCE SUMMARY DESIGNATIONS (Continued) I0 – I7 CLK OE CKPAL7 NOEPAL7 8 DINPAL7 NINPAL7 PROGRAMMABLE AND ARRAY AND 1 NINPAL7 8 8 DINPAL7 OR OR DFFPAL7 D Q Q NOUTPAL7 NOUTPAL7 Q1 – Q6 B0, B7 PLUS16R6 I0 – I7 CLK OE CKPAL7 NOEPAL7 8 DINPAL7 NINPAL7 PROGRAMMABLE AND ARRAY AND NINPAL7 8 1 8 DINPAL7 OR OR DFFPAL7 D Q NOUTPAL7 NOUTPAL7 Q2 – Q5 B0, B1, B6, B7 PLUS16R4 September 10, 1993 Q 51