INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF40192B MSI 4-bit up/down decade counter Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification HEF40192B MSI 4-bit up/down decade counter counting, both clock inputs cannot be LOW simultaneously. The outputs TCU and TCD are normally HIGH. When the circuit has reached the maximum count state of ‘9’, the next HIGH to LOW transition of CPU will cause TCU to go LOW. TCU will stay LOW until CPU goes HIGH again. Likewise, output TCD will go LOW when the circuit is in the zero state and CPD goes LOW. When PL is LOW, the information on P0 to P3 is asynchronously loaded into the counter. A HIGH on MR resets the counter independent of all other input conditions. The counter stages are of a static toggle type flip-flop. DESCRIPTION The HEF40192B is a 4-bit synchronous up/down decade counter. The counter has a count-up clock input (CPU), a count-down clock input (CPD), an asynchronous parallel load input (PL), four parallel data inputs (P0 to P3), an asynchronous master reset input (MR), four counter outputs (O0 to O3), an active LOW terminal count-up (carry) output (TCU) and an active LOW terminal count-down (borrow) output (TCD). The counter outputs change state on the LOW to HIGH transition of either clock input. However, for correct Fig.2 Pinning diagram. HEF40192BP(N): 16-lead DIL; plastic (SOT38-1) HEF40192BD(F): 16-lead DIL; ceramic (cerdip) Fig.1 Functional diagram. (SOT74) HEF40192BT(D): 16-lead SO; plastic (SOT109-1) PINNING PL parallel load input (active LOW) P0 to P3 parallel data inputs CPU count-up clock pulse input (LOW to HIGH, edge-triggered) CPD count-down clock pulse input (LOW to HIGH, edge-triggered) MR master reset input (asynchronous) TCU buffered terminal count-up (carry) output (active LOW) TCD buffered terminal count-down (borrow) output (active LOW) O0 to O3 buffered counter outputs January 1995 ( ): Package Designator North America FAMILY DATA, IDD LIMITS category MSI See Family Specifications 2 Philips Semiconductors Product specification HEF40192B MSI 4-bit up/down decade counter Fig.3 Logic diagram (continued on next page). January 1995 3 Philips Semiconductors Product specification HEF40192B MSI 4-bit up/down decade counter Fig.4 Logic diagram (continued from Fig.3). January 1995 4 Philips Semiconductors Product specification HEF40192B MSI 4-bit up/down decade counter Notes FUNCTION TABLE MR PL CPU CPD H X X X reset (asyn.) L L X X parallel load L H H count-up L H H MODE 1. H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage) X = state is immaterial = positive-going transition count-down Logic equations for terminal count: TC D = O 0 ⋅ O 1 ⋅ O 2 ⋅ O 3 ⋅ CP D TC U = O 0 ⋅ O 3 ⋅ CP U Fig.5 State diagram. AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; input transition times ≤ 20 ns VDD V Dynamic power dissipation per package (P) TYPICAL FORMULA FOR P (µW) 5 550 fi + ∑(foCL) × VDD2 10 2400 fi + ∑(foCL) × VDD2 fi = input freq. (MHz) 15 6500 fi + ∑(foCL) × fo = output freq. (MHz) VDD2 where CL = load capacitance (pF) ∑ (foCL) = sum of outputs VDD = supply voltage (V) January 1995 5 Philips Semiconductors Product specification HEF40192B MSI 4-bit up/down decade counter AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V SYMBOL MIN. TYPICAL EXTRAPOLATION FORMULA TYP. MAX. 210 415 ns 183 ns + (0,55 ns/pF) CL 85 165 ns 74 ns + (0,23 ns/pF) CL 60 120 ns 52 ns + (0,16 ns/pF) CL 170 340 ns 143 ns + (0,55 ns/pF) CL 70 140 ns 59 ns + (0,23 ns/pF) CL 50 100 ns 42 ns + (0,16 ns/pF) CL 210 420 ns 183 ns + (0,55 ns/pF) CL 85 170 ns 74 ns + (0,23 ns/pF) CL 65 125 ns 57 ns + (0,16 ns/pF) CL 170 340 ns 143 ns + (0,55 ns/pF) CL 70 140 ns 59 ns + (0,23 ns/pF) CL 50 100 ns 42 ns + (0,16 ns/pF) CL 125 250 ns 98 ns + (0,55 ns/pF) CL 50 100 ns 39 ns + (0,23 ns/pF) CL 15 35 70 ns 27 ns + (0,16 ns/pF) CL 5 95 185 ns 68 ns + (0,55 ns/pF) CL Propagation delays CPU → On HIGH to LOW 5 10 tPHL 15 5 LOW to HIGH 10 tPLH 15 CPD → On HIGH to LOW 5 10 tPHL 15 5 LOW to HIGH 10 tPLH 15 CPU → TCU HIGH to LOW LOW to HIGH CPD → TCD HIGH to LOW LOW to HIGH MR → On HIGH to LOW MR → TCU LOW to HIGH MR → TCD HIGH to LOW PL → On HIGH to LOW 5 10 tPHL 40 80 ns 29 ns + (0,23 ns/pF) CL 15 30 60 ns 22 ns + (0,16 ns/pF) CL 5 140 280 ns 113 ns + (0,55 ns/pF) CL 10 tPLH 55 110 ns 44 ns + (0,23 ns/pF) CL 15 40 80 ns 32 ns + (0,16 ns/pF) CL 5 100 195 ns 73 ns + (0,55 ns/pF) CL 10 tPHL 40 85 ns 29 ns + (0,23 ns/pF) CL 15 30 65 ns 22 ns + (0,16 ns/pF) CL 5 195 390 ns 168 ns + (0,55 ns/pF) CL 10 tPLH 80 160 ns 69 ns + (0,23 ns/pF) CL 15 60 120 ns 52 ns + (0,16 ns/pF) CL 5 145 285 ns 118 ns + (0,55 ns/pF) CL 10 tPHL 60 115 ns 49 ns + (0,23 ns/pF) CL 15 45 90 ns 37 ns + (0,16 ns/pF) CL 5 365 730 ns 338 ns + (0,55 ns/pF) CL 130 265 ns 119 ns + (0,23 ns/pF) CL 10 10 tPLH tPHL 15 100 205 ns 92 ns + (0,16 ns/pF) CL 5 185 360 ns 158 ns + (0,55 ns/pF) CL 75 150 ns 64 ns + (0,23 ns/pF) CL 55 110 ns 47 ns + (0,16 ns/pF) CL 10 tPHL 15 January 1995 6 Philips Semiconductors Product specification HEF40192B MSI 4-bit up/down decade counter VDD V SYMBOL MIN. 5 LOW to HIGH 10 TYPICAL EXTRAPOLATION FORMULA TYP. MAX. 145 290 60 120 ns 49 ns + (0,23 ns/pF) CL 45 90 ns 37 ns + (0,16 ns/pF) CL tPLH 15 ns 118 ns + (0,55 ns/pF) CL AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V Output transition times HIGH to LOW LOW to HIGH SYMBOL MIN. TYP. MAX. 5 Pn → PL Hold time Pn → PL Minimum CPU or CPD pulse width; LOW Minimum MR pulse width; HIGH Minimum PL pulse width; LOW Recovery time for MR Recovery time for PL 120 ns 60 ns 9 ns + (0,42 ns/pF) CL 15 20 40 ns 6 ns + (0,28 ns/pF) CL 5 60 120 ns 10 tTHL tTLH 5 10 tsu pulse frequency 60 ns 9 ns + (0,42 ns/pF) CL 40 ns 6 ns + (0,28 ns/pF) CL 160 80 ns 30 ns 50 25 ns 5 10 −70 ns 5 −25 ns 15 5 −20 ns 5 150 75 ns 10 thold tWCPL 50 25 ns 15 35 20 ns 5 180 90 ns 10 tWMRH 70 35 ns 15 60 30 ns 5 120 60 ns 45 20 ns 15 30 15 ns 5 125 65 ns 70 35 ns 15 50 25 ns 5 90 45 ns 35 15 ns 25 10 ns 5 MHz 7 14 MHz 9 18 MHz 10 10 10 tWPLL tRMR tRPL 5 10 15 January 1995 30 60 10 2,5 fmax 7 10 ns + (1,0 ns/pF) CL 20 15 15 Maximum clock 10 ns + (1,0 ns/pF) CL 60 30 10 15 Set-up time TYPICAL EXTRAPOLATION FORMULA see also waveforms Fig.6 Philips Semiconductors Product specification HEF40192B MSI 4-bit up/down decade counter Fig.6 Waveforms showing recovery times for PL and MR, minimum pulse widths for CPU, CPD, PL and MR, and set-up and hold times for P to PL. Set-up times and hold times are shown as positive values but may be specified as negative values. January 1995 8 Philips Semiconductors Product specification HEF40192B MSI 4-bit up/down decade counter Fig.7 Timing diagram. APPLICATION INFORMATION Some examples of applications for the HEF40192B are: • Up/down difference counting • Multistage ripple counting • Multistage synchronous counting. Fig.8 Example of cascaded HEF40192B ICs. January 1995 9