INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4076B MSI Quadruple D-type register with 3-state outputs Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification HEF4076B MSI Quadruple D-type register with 3-state outputs Information on D0 to D3 is stored in the four flip-flops on the LOW to HIGH transition of CP if both ED0 and ED1 are LOW. A HIGH on either ED0 or ED1 prevents the flip-flops from changing on the LOW to HIGH transition of CP, independent of the information on D0 to D3. When both EO0 and EO1 are LOW, the contents of the four flip-flops are available at O0 to O3. A HIGH on either EO0 or EO1 forces O0 to O3 into the high impedance OFF-state. A HIGH on MR resets all four flip-flops, independent of all other input conditions. DESCRIPTION The HEF4076B is a quadruple edge-triggered D-type flip-flop with four data inputs (D0 to D3), two active LOW data enable inputs (ED0 and ED1), a common clock input (CP), four 3-state outputs (O0 to O3), two active LOW output enable inputs (EO0 and EO1), and an overriding asynchronous master reset input (MR). Fig.2 Pinning diagram. HEF4076BP(N): 16-lead DIL; plastic (SOT38-1) HEF4076BD(F): 16-lead DIL; ceramic (cerdip) (SOT74) HEF4076BT(D): 16-lead SO; plastic (SOT109-1) Fig.1 Functional diagram. ( ): Package Designator North America PINNING FAMILY DATA, IDD LIMITS category MSI D0 to D3 data inputs ED0, ED1 data enable inputs (active LOW) EO0, EO1 output enable inputs (active LOW) CP clock input (LOW to HIGH, edge-triggered) MR master reset input O0 to O3 data outputs January 1995 See Family Specifications 2 Philips Semiconductors Product specification Quadruple D-type register with 3-state outputs Fig.3 Logic diagram. January 1995 3 HEF4076B MSI Philips Semiconductors Product specification HEF4076B MSI Quadruple D-type register with 3-state outputs Notes FUNCTION TABLE INPUTS 1. EO0 = EO1 = LOW When either EO0 or EO1 is HIGH, the outputs are disabled (high impedance OFF-state). H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage) X = state is immaterial = positive-going transition = negative-going transition OUTPUTS MR CP ED0 ED1 Dn On H X X X X L L H X X no change L X H X no change L L L H H L L L L L L X X X no change AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns; see also waveforms Fig.4 VDD V SYMBOL MIN. TYP. MAX. 150 305 TYPICAL EXTRAPOLATION FORMULA Propagation delays CP → On HIGH to LOW LOW to HIGH MR → On HIGH to LOW Output transition times HIGH to LOW LOW to HIGH 5 ns 60 120 ns 49 ns + (0,23 ns/pF) CL 15 45 85 ns 37 ns + (0,16 ns/pF) CL 5 160 320 ns 133 ns + (0,55 ns/pF) CL 10 tPHL 65 130 ns 54 ns + (0,23 ns/pF) CL 15 45 90 ns 37 ns + (0,16 ns/pF) CL 5 95 190 ns 68 ns + (0,55 ns/pF) CL 40 85 ns 29 ns + (0,23 ns/pF) CL 10 10 tPLH tPHL 15 30 65 ns 22 ns + (0,16 ns/pF) CL 5 60 120 ns 10 ns + (1,0 ns/pF) CL 30 60 ns 10 tTHL 40 ns 60 120 ns 30 60 ns 9 ns + (0,42 ns/pF) CL 15 20 40 ns 6 ns + (0,28 ns/pF) CL 5 50 105 ns 10 tTLH 10 35 70 ns HIGH 15 30 65 ns 5 45 90 ns 30 65 ns 30 60 ns 10 tPHZ tPLZ 15 January 1995 6 ns + (0,28 ns/pF) CL 20 5 EOn → On LOW 9 ns + (0,42 ns/pF) CL 15 3-state propagation times Output disable times 123 ns + (0,55 ns/pF) CL 4 10 ns + (1,0 ns/pF) CL Philips Semiconductors Product specification HEF4076B MSI Quadruple D-type register with 3-state outputs VDD V Output enable times SYMBOL MIN. 5 TYPICAL EXTRAPOLATION FORMULA TYP. MAX. 65 130 ns EOn → On 10 30 55 ns HIGH 15 20 40 ns 5 60 120 ns 25 50 ns 20 35 ns LOW tPZH 10 tPZL 15 AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V Set-up times 5 Dn → CP 10 EDn → CP Hold times Dn → CP EDn → CP Minimum clock pulse width; LOW Minimum MR pulse width; HIGH Recovery time for MR Maximum clock pulse frequency MIN. TYP. TYPICAL EXTRAPOLATION FORMULA MAX. 10 −15 ns 0 −10 ns 15 0 −5 ns 5 0 −50 ns tsu 0 −20 ns 15 0 −15 ns 5 55 30 ns 10 10 tsu 20 10 ns 15 15 10 ns 5 25 −25 ns thold 10 −10 ns 15 5 −5 ns 5 120 60 ns 10 10 thold tWCPL 45 20 ns 15 30 15 ns 5 55 25 ns 30 15 ns 15 20 10 ns 5 90 45 ns 35 15 ns 15 20 10 ns 5 4 8 MHz 11 22 MHz 16 32 MHz 10 10 10 15 January 1995 SYMBOL tWMRH tRMR fmax 5 see also waveforms Fig.4 Philips Semiconductors Product specification HEF4076B MSI Quadruple D-type register with 3-state outputs VDD V Dynamic power 5 TYPICAL FORMULA FOR P (µW) 2200 fi + ∑ (foCL) × VDD2 where fi = input freq. (MHz) dissipation per 10 9300 fi + ∑ (foCL) × package (P) 15 24 500 fi + ∑ (foCL) × VDD2 VDD2 fo = output freq. (MHz) CL = load capacitance (pF) ∑ (foCL) = sum of outputs VDD = supply voltage (V) January 1995 6 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... Product specification HEF4076B MSI Waveforms showing propagation delays, output disable/enable times, minimum CP and MR pulse widths, set-up and hold times for Dn to CP and EDn to CP, and recovery time for MR. Set-up and hold times are shown as positive values but may be specified as negative values. Philips Semiconductors 7 Quadruple D-type register with 3-state outputs January 1995 Fig.4