Philips Semiconductors Product specification 10-bit bus interface latch (3-State) 74ABT841 FEATURES DESCRIPTION • High speed parallel latches • Extra data width for wide address/data paths or buses carrying The 74ABT841 Bus interface register is designed to provide extra data width for wider data/address paths of buses carrying parity. The 74ABT841 consists of ten D-type latches with 3-State outputs. The flip-flops appear transparent to the data when Latch Enable (LE) is High. This allows asynchronous operation, as the output transition follows the data in transition. On the LE High-to-Low transition, the data that meets the setup and hold time is latched. parity • Ideal where high speed, light loading, or increased fan-in are required with MOS microprocessors • Slim DIP 300 mil package • Broadside pinout • Output capability: +64mA/–32mA • Latch-up protection exceeds 500mA per Jedec Std 17 • ESD protection exceeds 2000 V per MIL STD 883 Method 3015 Data appears on the bus when the Output Enable (OE) is Low. When OE is High the output is in the High-impedance state. and 200 V per Machine Model • Power-up 3-State • Power-up reset QUICK REFERENCE DATA SYMBOL CONDITIONS Tamb = 25°C; GND = 0V PARAMETER TYPICAL UNIT 4.1 ns tPLH tPHL Propagation delay Dn to Qn CL = 50pF; VCC = 5V CIN Input capacitance VI = 0V or VCC 4 pF COUT Output capacitance Outputs disabled; VO = 0V or VCC 7 pF ICCZ Total supply current Outputs disabled; VCC = 5.5V 500 nA ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER 24-Pin Plastic DIP –40°C to +85°C 74ABT841 N 74ABT841 N SOT222-1 24-Pin plastic SO –40°C to +85°C 74ABT841 D 74ABT841 D SOT137-1 24-Pin Plastic SSOP Type II –40°C to +85°C 74ABT841 DB 74ABT841 DB SOT340-1 24-Pin Plastic TSSOP Type I –40°C to +85°C 74ABT841 PW 74ABT841PW DH SOT355-1 PIN CONFIGURATION PIN DESCRIPTION OE 1 24 VCC D0 2 23 Q0 D1 3 22 Q1 D2 4 21 Q2 D3 5 20 Q3 D4 6 19 Q4 D5 7 18 Q5 D6 8 17 Q6 D7 9 16 Q7 D8 10 15 Q8 D9 11 14 Q9 GND 12 13 LE TOP VIEW PIN NUMBER SYMBOL FUNCTION 1 OE 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 D0-D9 Data inputs 23, 22, 21, 20, 19, 18, 17, 16, 15, 14 Q0-Q9 Data outputs 13 LE 12 GND Ground (0V) 24 VCC Positive supply voltage Output enable input (active-Low) Latch enable input (active falling edge) SA00247 1995 Sep 06 1 853-1628 15703 Philips Semiconductors Product specification 10-bit bus interface latch (3-State) 74ABT841 LOGIC SYMBOL FUNCTION TABLE INPUTS OPERATING MODE OE LE Dn Q0 – Q9 10 11 L L H H L H L H Transparent D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 L L ↓ ↓ l h L H Latched H X X Z High impedance L L X NC 2 3 13 LE 1 OE 4 5 6 7 8 9 23 22 21 20 19 18 17 16 15 14 SA00244 LOGIC SYMBOL (IEEE/IEC) 1 13 2 EN C1 1D 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 Hold H = High voltage level h = High voltage level one set-up time prior to the High-to-Low LE transition L = Low voltage level l = Low voltage level one set-up time prior to the High-to-Low LE transition ↓ = High-to-Low LE transition NC= No change X = Don’t care Z = High impedance “off” state Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 SA00245 1995 Sep 06 OUTPUTS 2 Philips Semiconductors Product specification 10-bit bus interface latch (3-State) 74ABT841 LOGIC DIAGRAM D0 D1 D2 D3 D4 D5 D6 D7 2 3 4 5 6 7 8 9 D L Q L L Q L Q L Q L Q L Q L Q D9 10 11 D D D D D D D D D8 D L Q Q L Q 13 LE 1 OE 23 21 22 Q0 Q2 Q1 18 19 20 Q5 Q4 Q3 17 16 15 Q8 Q7 Q6 14 Q9 SA00246 ABSOLUTE MAXIMUM RATINGS1, 2 SYMBOL VCC IIK PARAMETER CONDITIONS RATING UNIT –0.5 to +7.0 V –18 mA –1.2 to +7.0 V VO < 0 –50 mA output in Off or High state –0.5 to +5.5 V output in Low state 128 mA –65 to 150 °C DC supply voltage DC input diode current VI < 0 voltage3 VI DC input IOK DC output diode current voltage3 VOUT DC output IOUT DC output current Tstg Storage temperature range NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. RECOMMENDED OPERATING CONDITIONS SYMBOL VCC PARAMETER LIMITS DC supply voltage UNIT Min Max 4.5 5.5 V 0 VCC V VI Input voltage VIH High-level input voltage VIL Low-level input voltage 0.8 V IOH High-level output current –32 mA IOL Low-level output current 64 mA 0 5 ns/V –40 +85 °C ∆t/∆v Input transition rise or fall rate Tamb Operating free-air temperature range 1995 Sep 06 2.0 3 V Philips Semiconductors Product specification 10-bit bus interface latch (3-State) 74ABT841 DC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb = –40°C to +85°C Tamb = +25°C Min Max –0.9 –1.2 Min Max VIK Input clamp voltage VOH High-level output voltage VOL Low-level output voltage VCC = 4.5V; IOL = 64mA; VI = VIL or VIH 0.42 0.55 0.55 V VRST Power-up output low voltage3 VCC = 5.5V; IO = 1mA; VI = GND or VCC 0.13 0.55 0.55 V Input leakage Control pins VCC = 5.5V; VI = GND or 5.5V ±0.01 ±1.0 ±1.0 µA current Data pins VCC = 5.5V; VI = GND or 5.5V ±5 ±100 ±100 µA II VCC = 4.5V; IIK = –18mA Typ UNIT –1.2 V VCC = 4.5V; IOH = –3mA; VI = VIL or VIH 2.5 3.5 2.5 V VCC = 5.0V; IOH = –3mA; VI = VIL or VIH 3.0 4.0 3.0 V VCC = 4.5V; IOH = –32mA; VI = VIL or VIH 2.0 2.6 2.0 V Power-off leakage current VCC = 0.0V; VO or VI ≤ 4.5V ±5.0 ±100 ±100 µA Power-up/down 3–state output current4 VCC = 2.0V; VO = 0.5V; VI = GND or VCC; V OE = VCC ±5.0 ±50 ±50 µA IIH + IOZH 3-State output High current VCC = 5.5V; VO = 2.7V; VI = VIL or VIH 5.0 50 50 µA IIL + IOZL 3-State output Low current VCC = 5.5V; VO = 0.5V; VI = VIL or VIH –5.0 –50 –50 µA ICEX Output high leakage current VCC = 5.5V; VO = 5.5V; VI = GND or VCC Output current1 VCC = 5.5V; VO = 2.5V IOFF IPU/PD IO ICCH ICCL Quiescent supply current ICCZ ∆ICC Additional supply current per input pin2 50 µA –180 mA 5.0 50 –100 –180 VCC = 5.5V; Outputs High, VI = GND or VCC 0.5 250 250 µA VCC = 5.5V; Outputs Low, VI = GND or VCC 25 38 38 mA VCC = 5.5V; Outputs 3–State; VI = GND or VCC 0.5 250 250 µA One input at 3.4V, other inputs at VCC or GND; VCC = 5 5.5V 5V 05 0.5 15 1.5 15 1.5 mA A –50 –50 NOTES: 1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. This is the increase in supply current for each input at 3.4V. 3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. 4. This parameter is valid for any VCC between 0V and 2.1V with a transition time of up to 10msec. For VCC = 2.1V to VCC = 5V 10%, a transition time of up to 100µsec is permitted. AC CHARACTERISTICS GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER Tamb = -40 to +85oC VCC = +5.0V ±0.5V Tamb = +25oC VCC = +5.0V WAVEFORM UNIT Min Typ Max Min Max 2 2.1 2.0 4.1 4.0 5.5 5.5 2.1 2.0 6.2 6.2 ns Propagation delay LE to Qn 1 2.1 2.8 4.1 4.6 5.9 6.2 2.1 2.8 6.5 6.7 ns tPZH tPZL Output enable time to High and Low level 4 5 1.0 2.2 3.0 4.1 4.5 5.6 1.0 2.2 5.3 6.3 ns tPHZ tPLZ Output disable time from High and Low level 4 5 2.7 2.8 4.7 4.6 6.2 6.1 2.7 2.8 7.1 6.5 ns tPLH tPHL Propagation delay Dn to Qn tPLH tPHL 1995 Sep 06 4 Philips Semiconductors Product specification 10-bit bus interface latch (3-State) 74ABT841 AC SETUP REQUIREMENTS GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω LIMITS SYMBOL PARAMETER Tamb = +25oC VCC = +5.0V WAVEFORM Tamb = -40 to +85oC VCC = +5.0V ±0.5V UNIT Min Typ Min 3 2.5 1.5 1.0 0.0 2.5 1.5 ns Hold time, High or Low Dn to LE 3 1.5 1.0 0.2 –0.8 1.5 1.0 ns LE pulse width High or Low 1 3.3 1.9 3.3 ns ts(H) ts(L) Setup time, High or Low Dn to LE th(H) th(L) tw(H) tw(L) AC WAVEFORMS VM = 1.5V, VIN = GND to 3.0V LE VM VM VM tw(H) tPHL OE VM VM tPZH tPHZ tPLH Qn Qn VM VOH–0.3V VM VM 0V SA00248 SA00066 Waveform 4. 3-State Output Enable Time to High Level and Output Disable Time from High Level Waveform 1. Propagation Delay, Latch Enable Input to Output, and Enable Pulse Width Dn VM OE VM tPLH Qn VM VM tPZL tPHL VM VM Qn tPLZ VM VOL+0.3V 0V SA00067 SA00064 Waveform 5. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level Waveform 2. Propagation Delay for Data to Outputs Dn ÉÉÉ ÉÉÉÉÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉÉÉÉÉ ÉÉÉ VM VM ts(H) LE VM th(H) VM VM ts(L) th(L) VM NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance. SA00249 Waveform 3. Data Setup and Hold Times 1995 Sep 06 5 Philips Semiconductors Product specification 10-bit bus interface latch (3-State) 74ABT841 TEST CIRCUIT AND WAVEFORM VCC 7.0V PULSE GENERATOR VIN tW 90% VOUT VM NEGATIVE PULSE CL 10% 0V RL tTHL (tF) tTLH (tR) tTLH (tR) tTHL (tF) 90% POSITIVE PULSE Test Circuit for 3-State Outputs AMP (V) 90% VM VM 10% 10% tW SWITCH POSITION TEST SWITCH tPLZ closed tPZL closed All other open DEFINITIONS RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. AMP (V) VM 10% RL D.U.T. RT 90% 0V VM = 1.5V Input Pulse Definition INPUT PULSE REQUIREMENTS FAMILY 74ABT Amplitude Rep. Rate tW tR tF 3.0V 1MHz 500ns 2.5ns 2.5ns SA00012 1995 Sep 06 6