INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4008B MSI 4-bit binary full adder Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification HEF4008B MSI 4-bit binary full adder DESCRIPTION The HEF4008B is a 4-bit binary full adder with two 4-bit data inputs (A0 to A3, B0 to B3), a carry input (CIN), four sum outputs (S0 to S3), and a carry output (COUT). The IC uses full look-ahead across 4-bits to generate COUT. This minimizes the necessity for extensive look-ahead and carry-cascading circuits. Fig.2 Pinning diagram. PINNING A0 to A3 data inputs B0 to B3 data inputs S0 to S3 sum outputs CIN carry input COUT carry output TRUTH TABLE (one adder) Fig.1 Functional diagram. HEF4008BP(N): L COUT L L L L L H L H L H L L H L H H H L H L L L H H L H H L H H L H L H H H H H See Family Specifications 16-lead DIL; ceramic (cerdip) 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America January 1995 L B S FAMILY DATA, IDD LIMITS category MSI (SOT74) HEF4008BT(D): A 16-lead DIL; plastic (SOT38-1) HEF4008BD(F): CIN 2 Philips Semiconductors Product specification HEF4008B MSI 4-bit binary full adder Fig.3 Logic diagram. January 1995 3 Philips Semiconductors Product specification HEF4008B MSI 4-bit binary full adder AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V SYMBOL MIN. TYP. MAX. TYPICAL EXTRAPOLATION FORMULA Propagation delays sum in → sum out HIGH to LOW 150 300 ns 123 ns + (0,55 ns/pF) CL 55 110 ns 44 ns + (0,23 ns/pF) CL 40 80 ns 32 ns + (0,16 ns/pF) CL 135 270 ns 108 ns + (0,55 ns/pF) CL 55 110 ns 44 ns + (0,23 ns/pF) CL 40 80 ns 32 ns + (0,16 ns/pF) CL 125 250 ns 98 ns + (0,55 ns/pF) CL 50 100 ns 39 ns + (0,23 ns/pF) CL 35 70 ns 27 ns + (0,16 ns/pF) CL 100 200 ns 73 ns + (0,55 ns/pF) CL 45 90 ns 34 ns + (0,23 ns/pF) CL 30 60 ns 22 ns + (0,16 ns/pF) CL 130 260 ns 103 ns + (0,55 ns/pF) CL 50 100 ns 39 ns + (0,23 ns/pF) CL 15 35 70 ns 27 ns + (0,16 ns/pF) CL 5 115 230 ns 88 ns + (0,55 ns/pF) CL 5 10 tPHL 15 5 LOW to HIGH 10 tPLH 15 sum in → COUT HIGH to LOW 5 10 tPHL 15 5 LOW to HIGH 10 tPLH 15 CIN → sum out HIGH to LOW LOW to HIGH CIN → COUT HIGH to LOW LOW to HIGH Output transition times HIGH to LOW LOW to HIGH 5 10 50 100 ns 39 ns + (0,23 ns/pF) CL 15 35 70 ns 27 ns + (0,16 ns/pF) CL 5 90 180 ns 63 ns + (0,55 ns/pF) CL 10 tPLH 35 70 ns 24 ns + (0,23 ns/pF) CL 15 25 50 ns 17 ns + (0,16 ns/pF) CL 5 75 150 ns 48 ns + (0,55 ns/pF) CL 10 tPHL 35 70 ns 24 ns + (0,23 ns/pF) CL 15 25 50 ns 17 ns + (0,16 ns/pF) CL 5 60 120 ns 10 ns + (1,0 ns/pF) CL 10 tPLH 30 60 ns 9 ns + (0,42 ns/pF) CL 15 20 40 ns 6 ns + (0,28 ns/pF) CL 5 60 120 ns 30 60 ns 9 ns + (0,42 ns/pF) CL 20 40 ns 6 ns + (0,28 ns/pF) CL 10 10 15 January 1995 tPHL tTHL tTLH 4 10 ns + (1,0 ns/pF) CL Philips Semiconductors Product specification HEF4008B MSI 4-bit binary full adder Dynamic power VDD V TYPICAL FORMULA FOR P (µW) 5 1 500 fi + ∑ (foCL) × VDD2 where fi = input freq. (MHz) dissipation per 10 6 000 fi + ∑ (foCL) × package (P) 15 13 500 fi + ∑ (foCL) × VDD2 VDD2 fo = output freq. (MHz) CL = load capacitance (pF) ∑ (foCL) = sum of outputs VDD = supply voltage (V) APPLICATION INFORMATION Fig.4 Example of a 16-bit full adder using 4 HEF4008B ICs. January 1995 5