INTEGRATED CIRCUITS DATA SHEET 74AHC377; 74AHCT377 Octal D-type flip-flop with data enable; positive-edge trigger Product specification File under Integrated Circuits, IC06 2000 Aug 15 Philips Semiconductors Product specification Octal D-type flip-flop with data enable; positive-edge trigger 74AHC377; 74AHCT377 FEATURES DESCRIPTION • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1000 V The 74AHC/AHCT377 D-type flip-flops are high-speed silicon-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. • Balanced propagation delays The 74AHC/AHCT377 devices have eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. A common clock (CP) input loads all flip-flops simultaneously when the data enable (E) is LOW. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop. • All inputs have Schmitt-trigger actions • Inputs accept voltages higher than VCC • Ideal for addressable register applications • Data enable for address and data synchronization • Eight positive-edge triggered D-type flip-flops • See “273” for master reset version The E input must be stable only one set-up time prior to the LOW-to-HIGH transition for predictable operation. • See “373” for transparent latch version • See “374” for 3-state version • For AHC only: operates with CMOS input levels • For AHCT only: operates with TTL input levels • Specified from −40 to +85 and from −40 to +125 °C. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf ≤ 3.0 ns. TYPICAL SYMBOL PARAMETER CONDITIONS UNIT AHC AHCT tPHL/tPLH propagation delay; CP to Qn CL = 15 pF; VCC = 5 V 3.9 4.0 ns fmax maximum clock frequency CL = 15 pF; VCC = 5 V 175 140 MHz CI input capacitance VI = VCC or GND 3.0 3.0 pF CPD power dissipation capacitance CL = 50 pF; f = 1 MHz; notes 1 and 2 20 23 pF Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; ∑ (CL × VCC2 × fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in Volts. 2. The condition is VI = GND to VCC. 2000 Aug 15 2 Philips Semiconductors Product specification Octal D-type flip-flop with data enable; positive-edge trigger 74AHC377; 74AHCT377 FUNCTION TABLE See note 1. INPUTS OUTPUTS OPERATING MODES E CP Dn Qn l ↑ h H load “0” l ↑ l L hold (do nothing) h ↑ X no change H X X no change load “1” Note 1. H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition; L = LOW voltage level; I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition; X = don’t care; ↑ = LOW-to-HIGH CP transition. ORDERING INFORMATION PACKAGES TYPE NUMBER PINS PACKAGE MATERIAL CODE 74AHC377D 20 SO plastic SOT163-1 74AHC377PW 20 TSSOP plastic SOT360-1 74AHCT377D 20 SO plastic SOT163-1 74AHCT377PW 20 TSSOP plastic SOT360-1 PINNING PIN SYMBOL DESCRIPTION 1 E data enable input (active LOW) 2, 5, 6, 9, 12, 15, 16 and 19 Q0 to Q7 flip-flop outputs 3, 4, 7, 8, 13, 14, 17 and 18 D0 to D7 data inputs 10 GND ground (0 V) 11 CP clock input (LOW-to-HIGH, edge triggered) 20 VCC DC supply voltage 2000 Aug 15 3 Philips Semiconductors Product specification Octal D-type flip-flop with data enable; positive-edge trigger handbook, halfpage 74AHC377; 74AHCT377 20 VCC E 1 Q0 2 19 Q7 D0 3 18 D7 3 17 D6 4 D1 4 7 16 Q6 Q1 5 377 11 handbook, halfpage 8 Q2 6 15 Q5 13 D2 7 14 D5 14 17 D3 8 13 D4 Q3 9 12 Q4 GND 10 11 CP 18 CP D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 E 1 Q7 2 5 6 9 12 15 16 19 MNA605 MNA604 Fig.1 Pin configuration. handbook, halfpage 11 1 3 Fig.2 Logic symbol. handbook, halfpage 1C2 G1 2 2D 4 5 7 6 8 9 13 12 14 15 17 16 18 19 D0 Q0 2 4 D1 Q1 5 7 D2 Q2 6 Q3 9 8 D3 13 D4 14 D5 17 D6 Q6 16 18 D7 Q7 19 FF1 to FF8 OUTPUTS Q4 12 Q5 15 1 E 11 CP MNA606 MNA607 Fig.3 IEC logic symbol 2000 Aug 15 3 Fig.4 Functional diagram. 4 Philips Semiconductors Product specification Octal D-type flip-flop with data enable; positive-edge trigger 74AHC377; 74AHCT377 handbook, full pagewidth D0 D1 D2 D3 D4 D5 D6 D7 E D Q D CP Q D CP FF1 Q D CP FF2 Q D CP FF3 Q D CP FF4 Q D CP FF5 Q D CP FF6 Q CP FF7 FF8 CP Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 MNA610 Fig.5 Logic diagram. 2000 Aug 15 5 Philips Semiconductors Product specification Octal D-type flip-flop with data enable; positive-edge trigger 74AHC377; 74AHCT377 RECOMMENDED OPERATING CONDITIONS 74AHC SYMBOL PARAMETER 74AHCT CONDITIONS UNIT MIN. TYP. MAX. MIN. TYP. MAX. 4.5 5.0 5.5 V VCC DC supply voltage 2.0 5.0 5.5 VI input voltage 0 − 5.5 0 − 5.5 V VO output voltage 0 − VCC 0 − VCC V Tamb operating ambient temperature −40 +25 +85 −40 +25 +85 °C −40 +25 +125 −40 +25 +125 °C tr,tf (∆t/∆f) input rise and fall rates see DC and AC characteristics per device VCC = 3.3 V ±0.3 V − − 100 − − − VCC = 5 V ±0.5 V − 20 − − 20 − ns/V LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VCC DC supply voltage −0.5 +7.0 V VI input voltage range −0.5 +7.0 V IIK DC input diode current VI < −0.5 V; note 1 − −20 mA VO < −0.5 V or VO > VCC + 0.5 V; note 1 IOK DC output diode current − ±20 mA IO DC output source or sink current −0.5 V < VO < VCC + 0.5 V − ±25 mA ICC DC VCC or GND current − ±75 mA Tstg storage temperature range PD power dissipation per package for temperature range: −40 to +125 °C; note 2 −65 +150 °C − 500 Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. For SO packages: above 70 °C the value of PD derates linearly by 8 mW/K. For TSSOP packages: above 60 °C the value of PD derates linearly by 5.5 mW/K. 2000 Aug 15 6 mW Philips Semiconductors Product specification Octal D-type flip-flop with data enable; positive-edge trigger 74AHC377; 74AHCT377 DC CHARACTERISTICS 74AHC family With regard to recommended operating conditions; voltages are referenced to GND (ground = 0 V). Tamb (°C) TEST CONDITIONS SYMBOL OTHER VIH VIL VOH VOL −40 to +85 25 PARAMETER HIGH-level input voltage LOW-level input voltage VCC (V) −40 to +125 UNIT MIN. TYP. MAX. MIN. MAX. MIN. MAX. 2.0 1.5 − − 1.5 − 1.5 − 3.0 2.1 − − 2.1 − 2.1 − 5.5 3.85 − − 3.85 − 3.85 − 2.0 − − 0.5 − 0.5 − 0.5 3.0 − − 0.9 − 0.9 − 0.9 5.5 − − 1.65 − 1.65 − 1.65 2.0 1.9 2.0 − 1.9 − 1.9 − 3.0 2.9 3.0 − 2.9 − 2.9 − 4.5 4.4 4.5 − 4.4 − 4.4 − V V HIGH-level output voltage; all outputs VI = VIH or VIL; IO = −50 µA V HIGH-level output voltage VI = VIH or VIL; IO = −4.0 mA 3.0 2.58 − − 2.48 − 2.40 − VI = VIH or VIL; IO = −8.0 mA 4.5 3.94 − − 3.8 − 3.70 − LOW-level output voltage; all outputs VI = VIH or VIL; IO = 50 µA 2.0 − 0 0.1 − 0.1 − 0.1 3.0 − 0 0.1 − 0.1 − 0.1 4.5 − 0 0.1 − 0.1 − 0.1 LOW-level output voltage VI = VIH or VIL; IO = 4 mA 3.0 − − 0.36 − 0.44 − 0.55 VI = VIH or VIL; IO = 8 mA 4.5 − − 0.36 − 0.44 − 0.55 − 1.0 − 2.0 ±2.5 − ±10.0 µA V V V II input leakage current VI = VCC or GND 5.5 − − 0.1 IOZ 3-state output OFF current VI = VIH or VIL; 5.5 VO = VCC or GND − − ±0.25 − ICC quiescent supply current VI = VCC or GND; IO = 0 5.5 − − 4.0 − 40 − 80 µA CI input capacitance − − 3 10 − 10 − 10 pF 2000 Aug 15 7 µA Philips Semiconductors Product specification Octal D-type flip-flop with data enable; positive-edge trigger 74AHC377; 74AHCT377 74AHCT family With regard to recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL Tamb (°C) PARAMETER −40 to +85 25 OTHER VCC (V) −40 to +125 UNIT MIN. TYP. MAX. MIN. MAX. MIN. MAX. VIH HIGH-level input voltage 4.5 to 5.5 2.0 − − 2.0 − 2.0 − V VIL LOW-level input voltage 4.5 to 5.5 − − 0.8 − 0.8 − 0.8 V VOH HIGH-level output voltage; all outputs VI = VIH or VIL; IO = −50 µA 4.5 4.4 4.5 − 4.4 − 4.4 − V HIGH-level output voltage VI = VIH or VIL; IO = −8.0 mA 4.5 3.94 − − 3.8 − 3.70 − V LOW-level output voltage; all outputs VI = VIH or VIL; IO = 50 µA 4.5 − 0 0.1 − 0.1 − 0.1 V LOW-level output voltage VI = VIH or VIL; IO = 8 mA 4.5 − − 0.36 − 0.44 − 0.55 V II input leakage current VI = VIH or VIL 5.5 − − 0.1 − 1.0 − 2.0 µA IOZ 3-state output OFF current VI = VIH or VIL; 5.5 VO = VCC or GND per input pin; other inputs at VCC or GND; IO = 0 − − ±0.25 − ±2.5 − ±10.0 µA ICC quiescent supply current VI = VCC or GND; 5.5 IO = 0 − − 4.0 − 40 − 80 µA ∆ICC additional quiescent supply current per input pin VI = VCC − 2.1 V other inputs at VCC or GND; IO = 0 4.5 to 5.5 − − 1.35 − 1.5 − 1.5 mA CI input capacitance − 3 10 − 10 − 10 pF VOL 2000 Aug 15 − 8 Philips Semiconductors Product specification Octal D-type flip-flop with data enable; positive-edge trigger 74AHC377; 74AHCT377 AC CHARACTERISTICS Type 74AHC377 GND = 0 V; tr = tf ≤ 3.0 ns. Tamb (°C) TEST CONDITIONS SYMBOL −40 to +85 25 PARAMETER WAVEFORMS CL −40 to +125 UNIT MIN. TYP. MAX. MIN. MAX. MIN. MAX. VCC = 3.0 to 3.6 V; typical values at VCC = 3.3 V tPHL/tPLH propagation delay CP to Qn see Figs 6 and 8 15 pF − 5.6 12.8 1.0 15.0 1.0 16.0 ns fmax maximum clock pulse frequency see Figs 6 and 8 125 − 70 − 70 − MHz tPHL/tPLH propagation delay CP to Qn see Figs 6 and 8 50 pF − 8.0 16.0 1.0 18.0 1.0 20.0 ns tW clock pulse width HIGH or LOW see Figs 6 and 8 5.0 − − 5.0 − 5.0 − ns tsu set-up time Dn to CP see Figs 7 and 8 5.0 − − 5.0 − 5.0 − ns 5.0 − − 5.0 − 5.0 − ns hold time Dn to CP 1.5 − − 1.5 − 1.5 − ns hold time E to CP 1.5 − − 1.5 − 1.5 − ns 50 75 − 45 − 45 − MHz 80 set-up time E to CP th fmax maximum clock pulse frequency see Figs 6 and 8 VCC = 4.5 to 5.5 V; typical values at VCC = 5.0 V tPHL/tPLH propagation delay CP to Qn see Figs 6 and 8 15 pF − 3.9 9.0 1.0 10.5 1.0 11.5 ns fmax maximum clock pulse frequency see Figs 6 and 8 175 − 110 − 110 − MHz tPHL/tPLH propagation delay CP to Qn see Figs 6 and 8 50 pF − 5.6 10.5 1.0 12.0 1.0 13.5 ns tW clock pulse width HIGH or LOW see Figs 6 and 8 5.0 − − 5.0 − 5.0 − ns tsu set-up time Dn to CP see Figs 7 and 8 4.5 − − 4.5 − 4.5 − ns tsu set-up time E to CP 4.5 − − 4.5 − 4.5 − ns th hold time Dn to CP 2.0 − − 2.0 − 2.0 − ns th hold time E to CP 2.0 − − 2.0 − 2.0 − ns fmax maximum clock pulse frequency 85 120 − 75 − 75 − MHz 2000 Aug 15 125 see Figs 6 and 8 9 Philips Semiconductors Product specification Octal D-type flip-flop with data enable; positive-edge trigger 74AHC377; 74AHCT377 Type 74AHCT377 GND = 0 V; tr = tf ≤ 3.0 ns. TEST CONDITIONS SYMBOL Tamb (°C) −40 to +85 25 PARAMETER WAVEFORMS CL MIN. TYP. −40 to +125 UNIT MAX. MIN. MAX. MIN. MAX. 4.0 9.0 1.0 10.5 1.0 11.5 ns 140 − 80 − 80 − MHz 5.7 10.5 1.0 12.0 1.0 13.5 ns VCC = 4.5 to 5.5 V; typical values at VCC = 5.0 V 15 pF − tPHL/tPLH propagation delay CP to Qn see Figs 6 and 8 fmax maximum clock pulse frequency see Figs 6 and 8 tPHL/tPLH propagation delay CP to Qn see Figs 6 and 8 tW clock pulse width HIGH or LOW see Figs 6 and 8 5.0 − − 5.0 − 5.0 − ns tsu set-up time Dn to CP see Figs 7 and 8 4.5 − − 4.5 − 4.5 − ns set-up time E to CP 4.5 − − 4.5 − 4.5 − ns hold time Dn to CP 2.0 − − 2.0 − 2.0 − ns hold time E to CP 2.0 − − 2.0 − 2.0 − ns 85 130 − 75 − 75 − MHz th fmax maximum clock pulse frequency 2000 Aug 15 see Figs 6 and 8 90 50 pF − 10 Philips Semiconductors Product specification Octal D-type flip-flop with data enable; positive-edge trigger 74AHC377; 74AHCT377 AC WAVEFORMS 1/f max handbook, full pagewidth VI CP input VM(1) GND tW tPHL tPLH VOH VM(2) Qn output VOL FAMILY VM(1) INPUT VI INPUT REQUIREMENTS MNA608 VM(2) OUTPUT AHC GND to VCC 50% VCC 50% VCC AHCT GND to 3.0 V 1.5 V 50% VCC Fig.6 The clock (CP) to output (Qn) propagation delays. VCC handbook, full pagewidth VM(1) E input GND th th t su t su VCC stable VM(1) Dn input GND t su th tW VCC VM(1) CP input GND MNA609 FAMILY VI INPUT REQUIREMENTS VM(1) INPUT AHC GND to VCC 50% VCC AHCT GND to 3.0 V 1.5 V The shaded areas indicate when the input is permitted to change for predicable output performance. Fig.7 The data set-up and hold times for Dn input 2000 Aug 15 11 Philips Semiconductors Product specification Octal D-type flip-flop with data enable; positive-edge trigger 74AHC377; 74AHCT377 S1 handbook, full pagewidth VCC PULSE GENERATOR VI 1000 Ω VO D.U.T. CL RT MNA183 TEST S1 tPLH/tPHL open tPLZ/tPZL VCC tPHZ/tPZH GND Fig.8 Load circuit for switching times. 2000 Aug 15 12 VCC open GND Philips Semiconductors Product specification Octal D-type flip-flop with data enable; positive-edge trigger 74AHC377; 74AHCT377 PACKAGE OUTLINES SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c HE y v M A Z 11 20 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 10 e bp detail X w M 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.30 0.10 2.45 2.25 0.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.9 0.4 inches 0.10 0.012 0.096 0.004 0.089 0.01 0.019 0.013 0.014 0.009 0.51 0.49 0.30 0.29 0.050 0.419 0.043 0.055 0.394 0.016 0.043 0.039 0.01 0.01 0.004 0.035 0.016 Z (1) θ 8o 0o Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT163-1 075E04 MS-013 2000 Aug 15 EIAJ EUROPEAN PROJECTION ISSUE DATE 97-05-22 99-12-27 13 Philips Semiconductors Product specification Octal D-type flip-flop with data enable; positive-edge trigger 74AHC377; 74AHCT377 TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 E D A X c HE y v M A Z 11 20 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 10 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.10 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 1.0 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.5 0.2 8 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 2000 Aug 15 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 95-02-04 99-12-27 MO-153 14 o Philips Semiconductors Product specification Octal D-type flip-flop with data enable; positive-edge trigger SOLDERING 74AHC377; 74AHCT377 If wave soldering is used the following conditions must be observed for optimal results: Introduction to soldering surface mount packages • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. Reflow soldering The footprint must incorporate solder thieves at the downstream end. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Wave soldering Manual soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. To overcome these problems the double-wave soldering method was specifically developed. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. 2000 Aug 15 15 Philips Semiconductors Product specification Octal D-type flip-flop with data enable; positive-edge trigger 74AHC377; 74AHCT377 Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE REFLOW(1) WAVE BGA, SQFP not suitable suitable(2) HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not PLCC(3), SO, SOJ suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO suitable suitable suitable not recommended(3)(4) suitable not recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 2000 Aug 15 16 Philips Semiconductors Product specification Octal D-type flip-flop with data enable; positive-edge trigger 74AHC377; 74AHCT377 DATA SHEET STATUS DATA SHEET STATUS PRODUCT STATUS DEFINITIONS (1) Objective specification Development This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. Preliminary specification Qualification This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product specification Production This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Note 1. Please consult the most recently issued data sheet before initiating or completing a design. DEFINITIONS DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 2000 Aug 15 17 Philips Semiconductors Product specification Octal D-type flip-flop with data enable; positive-edge trigger NOTES 2000 Aug 15 18 74AHC377; 74AHCT377 Philips Semiconductors Product specification Octal D-type flip-flop with data enable; positive-edge trigger NOTES 2000 Aug 15 19 74AHC377; 74AHCT377 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW, Tel. +48 22 5710 000, Fax. +48 22 5710 001 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 58088 Newville 2114, Tel. +27 11 471 5401, Fax. +27 11 471 5398 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SÃO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 93 301 6312, Fax. +34 93 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 5F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2451, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 60/14 MOO 11, Bangna Trad Road KM. 3, Bagna, BANGKOK 10260, Tel. +66 2 361 7910, Fax. +66 2 398 3447 Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye, ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 800 943 0087 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 3341 299, Fax.+381 11 3342 553 For all other countries apply to: Philips Semiconductors, Marketing Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com SCA 70 © Philips Electronics N.V. 2000 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 613507/01/pp20 Date of release: 2000 Aug 15 Document order number: 9397 750 07331