PHILIPS VC162374ADL

INTEGRATED CIRCUITS
DATA SHEET
74LVC162374A; 74LVCH162374A
16-bit edge triggered D-type
flip-flop with 30 Ω series termination
resistors; 5 V input/output tolerant;
3-state
Product specification
File under Integrated Circuits, IC24
1999 Aug 05
Philips Semiconductors
Product specification
16-bit edge triggered D-type flip-flop with 30 Ω series
74LVC162374A;
termination resistors; 5 V input/output tolerant; 3-state 74LVCH162374A
FEATURES
DESCRIPTION
• ESD protection:
HBM EIA/JESD22-A114-A
exceeds 2000 V
MM EIA/JESD22-A115-A
exceeds 200 V
• 5 V tolerant input/output for
interfacing with 5 V logic
The 74LVC(H)162374A is a 16-bit edge triggered flip-flop featuring separate
D-type inputs for each flip-flop and 3-state outputs for bus oriented applications.
The 74LVC162374A consists of 2 sections of eight edge-triggered flip-flops.
A clock (CP) input and an output enable (OE) are provided for each octal.
Inputs can be driven from either 3.3 or 5 V devices. In 3-state operation,
outputs can handle 5 V. These features allow the use of these devices in a
mixed 3.3 and 5 V environment.
• Wide supply voltage range of
1.2 to 3.6 V
The flip-flops will store the state of their individual D-inputs that meet the set-up
and hold time requirements on the LOW-to-HIGH CP transition.
• Complies with JEDEC standard
no. 8-1A
• CMOS low power consumption
When OE is LOW, the contents of the flip-flops are available at the outputs.
When OE is HIGH, the outputs go to the high-impedance OFF-state.
Operation of the OE input does not affect the state of the flip-flops.
• MULTIBYTE flow-through
standard pin-out architecture
The 74LVCH162374A bus hold data inputs eliminates the need for external pull
up resistors to hold unused inputs.
• Low inductance multiple power and
ground pins for minimum noise and
ground bounce
The 74LVC(H)162374A is designed with 30 Ω series termination resistors in
both HIGH and LOW output stages to reduce line noise.
• Direct interface with TTL levels
• All data inputs have bus hold
(74LVCH162374A only)
• High impedance when VCC = 0
• Power off disables outputs,
permitting live insertion.
FUNCTION TABLE
See note 1.
INPUTS
Load and read register
Latch register and disable outputs
nOE
nCP
nDn
L
↑
l
L
L
L
↑
h
H
H
H
↑
l
L
Z
H
↑
h
H
Z
Note
1. H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
Z = high-impedance OFF-state;
↑ = LOW-to-HIGH CP transition.
1999 Aug 05
OUTPUTS
INTERNAL
FLIP-FLOPS
OPERATION MODES
2
Q0 to Q7
Philips Semiconductors
Product specification
16-bit edge triggered D-type flip-flop with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state
74LVC162374A;
74LVCH162374A
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns.
SYMBOL
PARAMETER
CONDITIONS
CL = 50 pF; VCC = 3.3 V
TYPICAL
UNIT
tPHL/tPLH
propagation delay CP to Qn
3.8
ns
fmax
maximum clock frequency
150
MHz
CI
input capacitance
5.0
pF
CPD
power dissipation capacitance per
flip-flop
30
pF
VCC = 3.3 V; note 1
Note
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
∑ (CL × VCC2 × fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in Volts.
ORDERING INFORMATION
PACKAGE
OUTSIDE NORTH
AMERICA
NORTH AMERICA
TEMPERATURE
RANGE
PINS
PACKAGE
MATERIAL
CODE
−40 to +85 °C
48
SSOP
plastic
SOT370-1
TSSOP
plastic
SOT362-1
74LVC162374ADL
VC162374A DL
74LVC162374ADGG
VC162374A DGG
48
74LVCH162374ADL
VCH162374A DL
48
SSOP
plastic
SOT370-1
74LVCH162374ADGG
VCH162374A DGG
48
TSSOP
plastic
SOT362-1
PINNING
PIN
1
SYMBOL
DESCRIPTION
1OE
output enable input (active LOW)
2, 3, 5, 6, 8, 9, 11, 12
1Q0 to 1Q7
3-state flip-flop outputs
4, 10, 15, 21, 28, 34, 39, 45
GND
ground (0 V)
7, 18, 31, 42
VCC
DC supply voltage
13, 14, 16, 17, 19, 20, 22, 23 2Q0 to 2Q7
3-state flip-flop outputs
24
2OE
output enable input (active LOW)
25
2CP
clock input
36, 35, 33, 32, 30, 29, 27, 26 2D0 to 2D7
data inputs
47, 46, 44, 43, 41, 40, 38, 37 1D0 to 1D7
data inputs
48
clock input
1999 Aug 05
1CP
3
Philips Semiconductors
Product specification
16-bit edge triggered D-type flip-flop with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state
handbook, halfpage
1OE 1
48 1CP
1Q0
2
47 1D0
1Q1
3
46 1D1
GND
4
45 GND
1Q2
5
44 1D2
1Q3
6
VCC
7
74LVC162374A;
74LVCH162374A
1
24
1OE
2OE
handbook, halfpage
47
1D0
1Q0
2
43 1D3
46
1D1
1Q1
3
42 VCC
44
1D2
1Q2
5
43
1D3
1Q3
6
41
1D4
1Q4
8
40
1D5
1Q5
9
11
1Q4
8
41 1D4
1Q5
9
40 1D5
GND 10
39 GND
38
1D6
1Q6
1Q6 11
38 1D6
37
1D7
1Q7
12
36
2D0
2Q0
13
37 1D7
1Q7 12
35
2D1
2Q1
14
36 2D0
33
2D2
2Q2
16
2Q1 14
35 2D1
32
2D3
2Q3
17
GND 15
34 GND
30
2D4
2Q4
19
29
2D5
2Q5
20
27
2D6
2Q6
22
26
2D7
2Q7
23
2Q0 13
162374A
2Q2 16
33 2D2
2Q3 17
32 2D3
VCC 18
31 VCC
1CP
2CP
2Q4 19
30 2D4
48
25
2Q5 20
29 2D5
GND 21
28 GND
2Q6 22
27 2D6
2Q7 23
26 2D7
2OE 24
25 2CP
MNA434
MNA433
Fig.1 Pin configuration.
1999 Aug 05
Fig.2 Logic symbol.
4
Philips Semiconductors
Product specification
16-bit edge triggered D-type flip-flop with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state
74LVC162374A;
74LVCH162374A
handbook, full pagewidth
1D0
D
1Q0
Q
2D0
D
CP
2Q0
Q
CP
FF1
FF2
1CP
2CP
1OE
2OE
to 7 other channels
to 7 other channels
MNA435
Fig.3 Logic diagram.
handbook, halfpage
1OE
1CP
2OE
2CP
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
1
48
24
25
47
1EN
C3
2EN
C2
1D
1
2
46
3
44
5
43
6
41
8
40
9
38
11
37
12
36
2D
2
13
35
14
33
16
32
17
30
19
29
20
27
22
26
23
1Q0
1Q1
handbook, halfpage
1Q2
VCC
1Q3
1Q4
input
1Q5
to internal circuit
1Q6
1Q7
MNA428
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
MNA436
Fig.4 IEC logic symbol.
1999 Aug 05
Fig.5 Bus hold circuit.
5
Philips Semiconductors
Product specification
16-bit edge triggered D-type flip-flop with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state
74LVC162374A;
74LVCH162374A
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
CONDITIONS
UNIT
MIN.
VCC
MAX.
DC supply voltage
for max. speed performance
2.7
3.6
V
for low-voltage applications
1.2
3.6
V
0
5.5
V
VI
DC input voltage range
VO
DC output voltage range
output HIGH or LOW state
0
VCC
V
3-state
0
5.5
V
see DC and AC characteristics per
device
−40
+85
°C
VCC = 1.2 to 2.7 V
0
20
ns/V
VCC = 2.7 to 3.6 V
0
10
ns/V
Tamb
operating ambient temperature
tr, tf
input rise and fall times
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
−0.5
+6.5
V
VI < 0
−
−50
mA
DC input voltage
note 1
−0.5
+5.5
V
IOK
DC output diode current
VO > VCC or VO < 0
−
±50
mA
VO
DC output voltage
output HIGH or LOW
note 1
−0.5
VCC + 0.5
V
output 3-state
note 1
−0.5
+6.5
V
VO = 0 to VCC
−
±50
mA
−
±100
mA
−65
+150
°C
−
500
mW
VCC
DC supply voltage
IIK
DC input diode current
VI
IO
DC output diode current
IGND, ICC
DC VCC or GND current
Tstg
storage temperature
Ptot
power dissipation plastic shrink
mini-pack (SSOP and TSSOP)
above 60 °C derate linearly with
5.5 mW/K
Note
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1999 Aug 05
6
Philips Semiconductors
Product specification
16-bit edge triggered D-type flip-flop with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state
74LVC162374A;
74LVCH162374A
DC CHARACTERISTICS
Over recommended operating conditions; voltage are referenced to GND (ground = 0 V).
TEST CONDITIONS
SYMBOL
−40 to +85
PARAMETER
VCC (V)
OTHER
VIH
Tamb (°C)
HIGH-level input voltage
MIN.
VOH
VOL
LOW-level input voltage
HIGH-level output voltage
LOW-level output voltage
MAX.
−
−
−
−
−
−
GND
2.7 to 3.6 −
−
0.8
1.2
VCC
2.7 to 3.6 2.0
VIL
TYP.(1)
UNIT
1.2
VI = VIH or VIL; IO = −6 mA 2.7
VCC − 0.5
−
−
VI = VIH or VIL;
IO = −100 µA
3.0
VCC − 0.2
VCC
−
VI = VIH or VIL;
IO = −12 mA
3.0
VCC − 0.8
−
−
VI = VIH or VIL; IO = 6 mA
2.7
−
−
0.40
VI = VIH or VIL;
IO = 100 µA
3.0
−
−
0.20
VI = VIH or VIL; IO = 12 mA 3.0
−
−
0.55
V
V
V
V
II
input leakage current
VI = 5.5 V or GND; note 2
3.6
−
±0.1
±5
µA
IOZ
3-state output OFF-state
current
VI = VIH or VIL;
VO = 5.5 V or GND
3.6
−
0.1
±5
µA
Ioff
power off leakage supply
VI or VO = 5.5 V
0.0
−
0.1
±10
µA
ICC
quiescent supply current
VI = VCC or GND; IO = 0
3.6
−
0.1
20
µA
∆ICC
additional quiescent supply VI = VCC − 0.6 V; IO = 0
current per control pin
2.7 to 3.6 −
5
500
µA
IBHL
bus hold LOW sustaining
current
VI = 0.8 V; notes 3,
4 and 5
3.0
75
−
−
µA
IBHH
bus hold HIGH sustaining
current
VI = 2.0 V; notes 3,
4 and 5
3.0
−75
−
−
µA
IBHLO
bus hold LOW overdrive
current
VI = 0.8 V; notes 3,
4 and 6
3.6
500
−
−
µA
IBHHO
bus hold HIGH overdrive
current
VI = 0.8 V; notes 3,
4 and 6
3.6
−500
−
−
µA
Notes
1. All typical values are at VCC = 3.3 V and Tamb = 25 °C.
2. For bus hold parts, the bus hold circuit is switched off when VI exceeds VCC allowing 5.5 V on the input terminal.
3. Valid for data inputs of bus hold parts (LVCH162374A) only.
4. For data inputs only, control inputs do not have a bus hold circuit.
5. The specified sustaining current at the data input holds the input below the specified VI level.
6. The specified overdrive current at the data input forces the data input to the opposite logic input state.
1999 Aug 05
7
Philips Semiconductors
Product specification
16-bit edge triggered D-type flip-flop with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state
74LVC162374A;
74LVCH162374A
AC CHARACTERISTICS
GND = 0 V; tr = tf ≤ 2.5 ns; Tamb = −40 to +85 °C.
LIMITS
SYMBOL
PARAMETER
VCC = 3.3 V ±0.3 V
WAVEFORMS
MIN.
TYP.(1)
MAX.
VCC = 2.7 V
MIN.
UNIT
MAX.
tPHL/tPLH
propagation delay
nCP to nQn
see Figs 6 and 9
1.5
3.8
6.2
1.5
7.2
ns
tPZH/tPZL
3-state output enable
time nOE to nQn
see Figs 8 and 9
1.5
4.1
7.1
1.5
8.1
ns
tPHZ/tPLZ
3-state output disable
time nOE to nQn
see Figs 8 and 9
1.5
3.7
5.2
1.5
6.2
ns
tW
nCP pulse width HIGH or see Fig.6
LOW
3
1.5
−
3.0
−
ns
tsu
set-up time nDn to nCP
see Fig.7
2.0
0.3
−
2.0
−
ns
th
hold time nDn to nCP
see Fig.7
+1.5
−0.3
−
1.5
−
ns
fmax
maximum clock pulse
frequency
see Fig.6
100
−
−
80
−
MHz
Note
1. Typical values at VCC = 3.3 V and Tamb = 25 °C.
1999 Aug 05
8
Philips Semiconductors
Product specification
16-bit edge triggered D-type flip-flop with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state
74LVC162374A;
74LVCH162374A
AC WAVEFORMS
1/fmax
handbook, full pagewidth
VI
nCP INPUT
VM
VM
GND
tW
t PHL
t PLH
VOH
VM
nQn OUTPUT
VOL
Fig.6
MNA437
Clock input (nCP) to output (nQn) propagation delay, the clock pulse width and the maximum clock pulse
frequency.
VI
handbook, full pagewidth
VM
nCP INPUT
GND
t su
t su
th
th
VI
VM
nDn INPUT
GND
VOH
VM
nQn OUTPUT
VOL
MNA438
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig.7 Data set-up and hold times for the nDn input to the nCP input.
1999 Aug 05
9
Philips Semiconductors
Product specification
16-bit edge triggered D-type flip-flop with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state
74LVC162374A;
74LVCH162374A
VI
handbook, full pagewidth
nOE INPUT
VM
GND
t PLZ
t PZL
VCC
nQn OUTPUT
LOW-to-OFF
OFF-to-LOW
VM
VX
VOL
t PZH
t PHZ
VOH
VY
nQn OUTPUT
HIGH-to-OFF
OFF-to-HIGH
VM
GND
outputs
enabled
outputs
enabled
outputs
disabled
MNA432
Fig.8 3-state enable and disable times.
S1
handbook, full pagewidth
VCC
PULSE
GENERATOR
VI
RL
500 Ω
VO
2 × VCC
open
GND
D.U.T.
CL
50 pF
RT
RL
500 Ω
MNA296
TEST
Definitions for test circuit:
RL = Load resistor; see Chapter “AC Characteristics”.
CL = Load capacitance including jig and probe capacitance
(see Chapter “AC Characteristics”).
RT = Termination resistance should be equal to the output
impedance Zo of the pulse generator.
S1
VCC
VI
tPLH/tPHL
open
tPLZ/tPZL
2 × VCC
<2.7 V
VCC
tPHZ/tPZH
GND
2.7 - 3.6 V
2.7 V
Fig.9 Load circuitry for switching times.
1999 Aug 05
10
Philips Semiconductors
Product specification
16-bit edge triggered D-type flip-flop with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state
74LVC162374A;
74LVCH162374A
PACKAGE OUTLINES
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm
SOT370-1
D
E
A
X
c
y
HE
v M A
Z
25
48
Q
A2
A1
A
(A 3)
θ
pin 1 index
Lp
L
24
1
detail X
w M
bp
e
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
2.8
0.4
0.2
2.35
2.20
0.25
0.3
0.2
0.22
0.13
16.00
15.75
7.6
7.4
0.635
10.4
10.1
1.4
1.0
0.6
1.2
1.0
0.25
0.18
0.1
0.85
0.40
8
0o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT370-1
1999 Aug 05
REFERENCES
IEC
JEDEC
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
93-11-02
95-02-04
MO-118AA
11
o
Philips Semiconductors
Product specification
16-bit edge triggered D-type flip-flop with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state
74LVC162374A;
74LVCH162374A
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm
SOT362-1
E
D
A
X
c
HE
y
v M A
Z
48
25
Q
A2
(A 3)
A1
pin 1 index
A
θ
Lp
L
1
detail X
24
w M
bp
e
2.5
0
5 mm
scale
DIMENSIONS (mm are the original dimensions).
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z
θ
mm
1.2
0.15
0.05
1.05
0.85
0.25
0.28
0.17
0.2
0.1
12.6
12.4
6.2
6.0
0.5
8.3
7.9
1
0.8
0.4
0.50
0.35
0.25
0.08
0.1
0.8
0.4
8
0o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT362-1
1999 Aug 05
REFERENCES
IEC
JEDEC
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
93-02-03
95-02-10
MO-153ED
12
o
Philips Semiconductors
Product specification
16-bit edge triggered D-type flip-flop with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state
SOLDERING
74LVC162374A;
74LVCH162374A
If wave soldering is used the following conditions must be
observed for optimal results:
Introduction to soldering surface mount packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
Reflow soldering
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Wave soldering
Manual soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
1999 Aug 05
13
Philips Semiconductors
Product specification
16-bit edge triggered D-type flip-flop with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state
74LVC162374A;
74LVCH162374A
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
REFLOW(1)
WAVE
BGA, SQFP
not suitable
HLQFP, HSQFP, HSOP, SMS
not
PLCC(3), SO, SOJ
suitable
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
suitable(2)
suitable
suitable
not
recommended(3)(4)
suitable
not
recommended(5)
suitable
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1999 Aug 05
14
Philips Semiconductors
Product specification
16-bit edge triggered D-type flip-flop with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state
NOTES
1999 Aug 05
15
74LVC162374A;
74LVCH162374A
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© Philips Electronics N.V. 1999
SCA 67
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Printed in The Netherlands
245004/01/pp16
Date of release: 1999
Aug 05
Document order number:
9397 750 05975