74HC2G66; 74HCT2G66 Dual single-pole single-throw analog switch Rev. 06 — 2 April 2010 Product data sheet 1. General description 74HC2G66 and 74HCT2G66 are high-speed Si-gate CMOS devices. They are dual single-pole single-throw analog switches. Each switch has two input/output pins (nY and nZ) and an active HIGH enable input pin (nE). When pin nE is LOW, the analog switch is turned off. 2. Features and benefits Wide supply voltage range from 2.0 V to 10.0 V for 74HC2G66 Very low ON resistance: 41 Ω (typ.) at VCC = 4.5 V 30 Ω (typ.) at VCC = 6.0 V 21 Ω (typ.) at VCC = 9.0 V High noise immunity Low power dissipation 25 mA continuous switch current Multiple package options ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Specified from −40 °C to +85 °C and −40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC2G66DP −40 °C to +125 °C TSSOP8 plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2 −40 °C to +125 °C VSSOP8 plastic very thin shrink small outline package; 8 SOT765-1 leads; body width 2.3 mm −40 °C to +125 °C XSON8U plastic extremely thin small outline package; no SOT996-2 leads; 8 terminals; UTLP based; body 3 × 2 × 0.5 mm 74HCT2G66DP 74HC2G66DC 74HCT2G66DC 74HC2G66GD 74HCT2G66GD 74HC2G66; 74HCT2G66 NXP Semiconductors Dual single-pole single-throw analog switch 4. Marking Table 2. Marking codes Type number Marking 74HC2G66DP H66 74HCT2G66DP T66 74HC2G66DC H66 74HCT2G66DC T66 74HC2G66GD H66 74HCT2G66GD T66 5. Functional diagram 1Y 1Z 1E 2Z 2Y Y Z 2E E 001aah372 001aag497 Fig 1. Logic symbol Fig 2. Logic diagram for 1 switch 6. Pinning information 6.1 Pinning 74HC2G66 74HCT2G66 74HC2G66 74HCT2G66 1Y 1 8 VCC 1Z 2 7 1E 2E 3 6 2Z GND 4 5 2Y 1Y 1 8 VCC 1Z 2 7 1E 2E 3 6 2Z GND 4 5 2Y 001aal625 Transparent top view 001aai699 Fig 3. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8) 74HC_HCT2G66_6 Product data sheet Fig 4. Pin configuration SOT996-2 (XSON8U) All information provided in this document is subject to legal disclaimers. Rev. 06 — 2 April 2010 © NXP B.V. 2010. All rights reserved. 2 of 21 74HC2G66; 74HCT2G66 NXP Semiconductors Dual single-pole single-throw analog switch 6.2 Pin description Table 3. Pin description Symbol Pin Description 1Y, 2Y 1, 5 independent input or output 1Z, 2Z 2, 6 independent input or output GND 4 ground (0 V) 1E, 2E 7, 3 enable input (active HIGH) VCC 8 supply voltage 7. Functional description Table 4. Function table[1] Input nE Switch L OFF H ON [1] H = HIGH voltage level; L = LOW voltage level. 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage Conditions Min Max Unit −0.5 +11.0 V - ±20 mA - ±20 mA - ±20 mA input clamping current VI < −0.5 V or VI > VCC + 0.5 V [1] ISK switch clamping current VI < −0.5 V or VI > VCC + 0.5 V [1] ISW switch current VSW > −0.5 V or VSW < VCC + 0.5 V ICC supply current - 30 mA IGND ground current −30 - mA Tstg storage temperature −65 +150 °C Ptot total power dissipation IIK [1] [2] Tamb = −40 °C to +125 °C per package [2] - 300 mW per switch [2] - 100 mW The input and output voltage ratings may be exceeded if the input and output current ratings are observed. For TSSOP8 packages above 55 °C the value of Ptot derates linearly with 2.5 mW/K. For VSSOP8 packages above 110 °C the value of Ptot derates linearly with 8.0 mW/K. For XSON8U package: above 118 °C the value of Ptot derates linearly with 7.8 mW/K. 74HC_HCT2G66_6 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 06 — 2 April 2010 © NXP B.V. 2010. All rights reserved. 3 of 21 74HC2G66; 74HCT2G66 NXP Semiconductors Dual single-pole single-throw analog switch 9. Recommended operating conditions Table 6. Recommended operating conditions Voltages are referenced to GND (ground = 0 V).[1] Symbol Parameter Conditions 74HC2G66 74HCT2G66 Min Typ Max Min Typ Unit Max VCC supply voltage 2.0 5.0 10.0 4.5 5.0 5.5 V VI input voltage 0 - VCC 0 - VCC V VO output voltage 0 - VCC 0 - VCC V VSW switch voltage 0 - VCC 0 - VCC V Tamb ambient temperature °C Δt/ΔV input transition rise and fall rate [1] −40 +25 +125 −40 +25 +125 VCC = 2.0 V - - 625 - - - ns/V VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V VCC = 6.0 V - - 83 - - - ns/V VCC = 10.0 V - - 35 - - - ns/V To avoid drawing VCC current out of pin nZ, when switch current flows in pin nY, the voltage drop across the bidirectional switch must not exceed 0.4 V. If the switch current flows into pin nZ, no VCC current will flow out of terminal nY. In this case there is no limit for the voltage drop across the switch, but the voltage at pins nY and nZ may not exceed VCC or GND. 10. Static characteristics Table 7. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter −40 °C to +85 °C Conditions Min Typ[1] Max VCC = 2.0 V 1.5 1.2 VCC = 4.5 V 3.15 2.4 VCC = 6.0 V 4.2 VCC = 9.0 V 6.3 −40 °C to +125 °C Unit Min Max - 1.5 - V - 3.15 - V 3.2 - 4.2 - V 4.7 - 6.3 - V 74HC2G66 VIH VIL II HIGH-level input voltage LOW-level input voltage input leakage current VCC = 2.0 V - 0.8 0.5 - 0.5 V VCC = 4.5 V - 2.1 1.35 - 1.35 V VCC = 6.0 V - 2.8 1.8 - 1.8 V VCC = 9.0 V - 4.3 2.7 - 2.7 V VCC = 6.0 V - - ±0.1 - ±0.1 μA VCC = 9.0 V - - ±0.2 - ±0.2 μA nE; VI = VCC or GND IS(OFF) OFF-state leakage current nY or nZ; VCC = 9.0 V; see Figure 5 - 0.1 1.0 - 1.0 μA IS(ON) ON-state leakage current nY or nZ; VCC = 9.0 V; see Figure 6 - 0.1 1.0 - 1.0 μA ICC supply current nE, nY and nZ = VCC or GND VCC = 6.0 V - - 10 - 20 μA VCC = 9.0 V - - 20 - 40 μA 74HC_HCT2G66_6 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 06 — 2 April 2010 © NXP B.V. 2010. All rights reserved. 4 of 21 74HC2G66; 74HCT2G66 NXP Semiconductors Dual single-pole single-throw analog switch Table 7. Static characteristics …continued Voltages are referenced to GND (ground = 0 V). Symbol Parameter −40 °C to +85 °C Conditions −40 °C to +125 °C Unit Min Typ[1] Max Min Max CI input capacitance - 3.5 - - - pF CPD power dissipation capacitance - 9 - - - pF CS(ON) ON-state capacitance - 8 - - - pF 74HCT2G66 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 V II input leakage current nE; VI = VCC or GND; VCC = 5.5 V - - ±1.0 - ±1.0 μA IS(OFF) OFF-state leakage current nY or nZ; VCC = 5.5 V; see Figure 5 - 0.1 1.0 - 1.0 μA IS(ON) ON-state leakage current nY or nZ; VCC = 5.5 V; see Figure 6 - 0.1 1.0 - 1.0 μA ICC supply current nE, nY and nZ = VCC or GND; VCC = 4.5 V to 5.5 V - - 10 - 20 μA ΔICC additional supply current nE = VCC − 2.1 V; IO = 0 A; VCC = 4.5 V to 5.5 V; - - 375 - 410 μA CI input capacitance - 3.5 - - - pF CPD power dissipation capacitance - 9 - - - pF CS(ON) ON-state capacitance - 8 - - - pF [1] Typical values are measured at Tamb = 25 °C. 10.1 Test circuits VCC VCC nE VIL IS VI nE VIH nY nZ IS IS GND VO VI 001aaj465 Test circuit for measuring OFF-state leakage current 74HC_HCT2G66_6 Product data sheet nZ GND VO 001aaj466 VI = VCC or GND and VO = GND or VCC. Fig 5. nY VI = VCC or GND and VO = open circuit. Fig 6. Test circuit for measuring ON-state leakage current All information provided in this document is subject to legal disclaimers. Rev. 06 — 2 April 2010 © NXP B.V. 2010. All rights reserved. 5 of 21 74HC2G66; 74HCT2G66 NXP Semiconductors Dual single-pole single-throw analog switch 10.2 ON resistance Table 8. ON resistance for 74HC2G66 and 74HCT2G66 At recommended operating conditions; voltages are referenced to GND (ground 0 V); for graph see Figure 8. Symbol Parameter −40 °C to +85 °C Conditions −40 °C to +125 °C Unit Min Typ[2] Max Min Max ISW = 0.1 mA; VCC = 2.0 V - 250 - - - Ω ISW = 1.0 mA; VCC = 4.5 V - 41 118 - 142 Ω ISW = 1.0 mA; VCC = 6.0 V - 30 105 - 126 Ω ISW = 1.0 mA; VCC = 9.0 V - 21 88 - 105 Ω 74HC2G66[1] RON(peak) ON resistance (peak) RON(rail) ON resistance (rail) VI = GND to VCC; see Figure 7 and 8 VI = GND; see Figure 7 and 8 ISW = 0.1 mA; VCC = 2.0 V - 65 - - - Ω ISW = 1.0 mA; VCC = 4.5 V - 28 95 - 115 Ω ISW = 1.0 mA; VCC = 6.0 V - 22 82 - 100 Ω ISW = 1.0 mA; VCC = 9.0 V - 18 70 - 80 Ω ISW = 0.1 mA; VCC = 2.0 V - 65 - - - Ω ISW = 1.0 mA; VCC = 4.5 V - 31 106 - 128 Ω ISW = 1.0 mA; VCC = 6.0 V - 23 94 - 113 Ω ISW = 1.0 mA; VCC = 9.0 V - 19 78 - 95 Ω VCC = 4.5 V - 5 - - - Ω VCC = 6.0 V - 4 - - - Ω VCC = 9.0 V - 3 - - - Ω - 41 118 - 142 Ω - 28 95 - 115 Ω - 31 106 - 128 Ω - 5 - - - Ω VI = VCC; see Figure 7 and 8 ΔRON ON resistance mismatch between channels VI = VCC to GND; see Figure 7 and 8 74HCT2G66 RON(peak) ON resistance (peak) VI = GND to VCC; see Figure 7 and 8 ISW = 1.0 mA; VCC = 4.5 V RON(rail) ON resistance (rail) VI = GND; see Figure 7 and 8 ISW = 1.0 mA; VCC = 4.5 V VI = VCC; see Figure 7 and 8 ISW = 1.0 mA; VCC = 4.5 V ΔRON ON resistance mismatch between channels VI = VCC to GND; see Figure 7 and 8 VCC = 4.5 V [1] At supply voltages approaching 2 V, the ON resistance becomes extremely non-linear. Therefore it is recommended that these devices be used to transmit digital signals only, when using this supply voltage. [2] Typical values are measured at Tamb = 25 °C. 74HC_HCT2G66_6 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 06 — 2 April 2010 © NXP B.V. 2010. All rights reserved. 6 of 21 74HC2G66; 74HCT2G66 NXP Semiconductors Dual single-pole single-throw analog switch 10.3 ON resistance test circuit and graphs mnb006 60 RON (Ω) VSW VCC = 4.5 V 40 VCC VCC = 6.0 V nE VIH nY VI 20 nZ VCC = 9.0 V GND ISW 0 0 2 4 6 8 Tamb = 25 °C. RON = VSW / ISW. Fig 7. 10 VI (V) 001aaj467 Test circuit for measuring ON resistance Fig 8. Typical ON resistance as a function of input voltage 11. Dynamic characteristics Table 9. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); For test circuit see Figure 11. Symbol Parameter −40 °C to +85 °C Conditions −40 °C to +125 °C Unit Min Typ[1] Max Min Max VCC = 2.0 V - 6.5 65 - 80 ns VCC = 4.5 V - 2 13 - 15 ns VCC = 6.0 V - 1.5 11 - 14 ns VCC = 9.0 V - 1.2 10 - 12 ns VCC = 2.0 V - 40 125 - 150 ns VCC = 4.5 V - 12 29 - 30 ns VCC = 6.0 V - 10 21 - 26 ns - 7 16 - 20 ns VCC = 2.0 V - 21 145 - 175 ns VCC = 4.5 V - 12 29 - 35 ns VCC = 6.0 V - 11 28 - 33 ns - 10 23 - 27 ns - 9 - - - pF 74HC2G66 tpd ten propagation delay nY to nZ or nZ to nY; RL = ∞ Ω; see Figure 9 enable time nE to nY or nZ; see Figure 10 [2] [2] VCC = 9.0 V tdis disable time nE to nY or nZ; see Figure 10 [2] VCC = 9.0 V CPD power dissipation VI = GND to VCC capacitance 74HC_HCT2G66_6 Product data sheet [3] All information provided in this document is subject to legal disclaimers. Rev. 06 — 2 April 2010 © NXP B.V. 2010. All rights reserved. 7 of 21 74HC2G66; 74HCT2G66 NXP Semiconductors Dual single-pole single-throw analog switch Table 9. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); For test circuit see Figure 11. Symbol Parameter −40 °C to +85 °C Conditions −40 °C to +125 °C Unit Min Typ[1] Max Min Max - 2 15 - 18 ns - 13 30 - 36 ns - 13 44 - 53 ns - 9 - - - pF 74HCT2G66 propagation delay nY to nZ or nZ to nY; RL = ∞ Ω; see Figure 9 tpd [2] VCC = 4.5 V ten enable time nE to nY or nZ; see Figure 10 tdis disable time nE to nY or nZ; see Figure 10 [2] VCC = 4.5 V [2] VCC = 4.5 V power dissipation VI = GND to VCC − 1.5 V capacitance CPD [1] [2] [3] All typical values are measured at Tamb = 25 °C. tpd is the same as tPLH and tPHL. ten is the same as tPZL and tPZH. tdis is the same as tPLZ and tPHZ. [3] CPD is used to determine the dynamic power dissipation PD (μW). PD = CPD × VCC2 × fi + Σ((CL × CSW) × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; CSW = maximum switch capacitance in pF (see Table 7); VCC = supply voltage in volts; Σ((CL × CSW) × VCC2 × fo) = sum of outputs. 11.1 Waveforms and test circuit VI nY or nZ input VM VM GND t PLH t PHL VOH nZ or nY output VM VM VOL 001aaa541 Measurement points are given in Table 10. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 9. Input (nY or nZ) to output (nZ or nY) propagation delays 74HC_HCT2G66_6 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 06 — 2 April 2010 © NXP B.V. 2010. All rights reserved. 8 of 21 74HC2G66; 74HCT2G66 NXP Semiconductors Dual single-pole single-throw analog switch VI nE input VM GND t PLZ t PZL VCC nY or nZ output LOW-to-OFF OFF-to-LOW VM VX VOL t PZH t PHZ nY or nZ output HIGH-to-OFF OFF-to-HIGH VOH VY VM GND switch enabled switch disabled switch enabled 001aaa542 Measurement points are given in Table 10. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 10. Enable and disable times Table 10. Measurement points Type Input Output VM VM VX VY 74HC2G66 0.5VCC 0.5VCC VOL + 10 % VOH − 10 % 74HCT2G66 1.3 V 1.3 V VOL + 10 % VOH − 10 % 74HC_HCT2G66_6 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 06 — 2 April 2010 © NXP B.V. 2010. All rights reserved. 9 of 21 74HC2G66; 74HCT2G66 NXP Semiconductors Dual single-pole single-throw analog switch VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VCC G VCC VI VO RL S1 open DUT CL RT 001aad983 Test data is given in Table 11. Definitions for test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch. Fig 11. Test circuit for measuring switching times Table 11. Test data Type Input Load [1] S1 position VI tr, tf CL RL tPHL, tPLH tPZH, tPHZ tPZL, tPLZ 74HC2G66 GND to VCC 6 ns 50 pF 1 kΩ open GND VCC 74HCT2G66 GND to 3 V 6 ns 50 pF 1 kΩ open GND VCC [1] There is no constraint on tr, tf with a 50 % duty factor when measuring fmax. 11.2 Additional dynamic characteristics Table 12. Additional dynamic characteristics for 74HC2G66 and 74HCT2G66 GND = 0 V; tr = tf = 6.0 ns; CL = 50 pF; unless otherwise specified. All typical values are measured at Tamb = 25 °C. Symbol Parameter Conditions Min Typ Max Unit THD total harmonic distortion fi = 1 kHz; RL = 10 kΩ; see Figure 12 VCC = 4.5 V; VI = 4.0 V (p-p) - 0.04 - % VCC = 9.0 V; VI = 8.0 V (p-p) - 0.02 - % VCC = 4.5 V; VI = 4.0 V (p-p) - 0.12 - % VCC = 9.0 V; VI = 8.0 V (p-p) - 0.06 - % % fi = 10 kHz; RL = 10 kΩ; see Figure 12 74HC_HCT2G66_6 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 06 — 2 April 2010 © NXP B.V. 2010. All rights reserved. 10 of 21 74HC2G66; 74HCT2G66 NXP Semiconductors Dual single-pole single-throw analog switch Table 12. Additional dynamic characteristics for 74HC2G66 and 74HCT2G66 …continued GND = 0 V; tr = tf = 6.0 ns; CL = 50 pF; unless otherwise specified. All typical values are measured at Tamb = 25 °C. Symbol Parameter Conditions f(−3dB) −3 dB frequency response RL = 50 Ω; CL = 10 pF; see Figure 13 and 14 αiso isolation (OFF-state) crosstalk voltage Vct Xtalk Min Typ Max Unit VCC = 4.5 V - 180 - MHz VCC = 9.0 V - 200 - MHz VCC = 4.5 V - −50 - dB VCC = 9.0 V - −50 - dB VCC = 4.5 V - 110 - mV VCC = 9.0 V - 220 - mV VCC = 4.5 V - −60 - dB VCC = 9.0 V - −60 - dB RL = 600 Ω; fi = 1 MHz; see Figure 15 and 16 between digital input and switch (peak to peak value); RL = 600 Ω; fi = 1 MHz; see Figure 17 between switches; RL = 600 Ω; fi = 1 MHz; see Figure 18 crosstalk 11.3 Test circuits and graphs VCC VCC VCC nE VIH 10 μF nY/nZ fi nE VIH 2RL 2RL 0.1 μF nZ/nY VO 2RL CL VCC D nY/nZ fi 001aaj468 nZ/nY VO 2RL CL dB 001aaj469 With fi = 1 MHz adjust the switch input voltage for a 0 dBm level at the switch output, (0 dBm = 1 mW into 50 Ω). Then Increase the input frequency until the dB meter reads −3 dB. Fig 12. Test circuit for measuring total harmonic distortion 74HC_HCT2G66_6 Product data sheet Fig 13. Test circuit for measuring the −3 dB frequency response All information provided in this document is subject to legal disclaimers. Rev. 06 — 2 April 2010 © NXP B.V. 2010. All rights reserved. 11 of 21 74HC2G66; 74HCT2G66 NXP Semiconductors Dual single-pole single-throw analog switch mna083 5 (dB) 0 −5 10 102 103 104 105 106 fi (kHz) Test conditions: VCC = 4.5 V; GND = 0 V; RL = 50 Ω; RSOURCE = 1 kΩ. Fig 14. Typical −3 dB frequency response VCC VCC nE VIL 2RL 0.1 μF nY/nZ fi nZ/nY VO CL 2RL dB 001aaj470 Adjust the switch input voltage for a 0 dBm level (0 dBm = 1 mW into 600 Ω) Fig 15. Test circuit for measuring isolation (OFF-state) 74HC_HCT2G66_6 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 06 — 2 April 2010 © NXP B.V. 2010. All rights reserved. 12 of 21 74HC2G66; 74HCT2G66 NXP Semiconductors Dual single-pole single-throw analog switch mna082 0 (dB) −20 −40 −60 −80 −100 10 102 103 104 105 106 fi (kHz) Test conditions: VCC = 4.5 V; GND = 0 V; RL = 50 Ω; RSOURCE = 1 kΩ. Fig 16. Typical isolation (OFF-state) as a function of frequency VCC nE VCC VCC GND 2RL 2RL nY/nZ nZ/nY DUT 2RL 2RL CL oscilloscope GND mnb011 a. Circuit V(p−p) mnb012 b. Crosstalk voltage Adjust the switch input voltage for a 0 dBm level (0 dBm = 1 mW into 600 Ω) Fig 17. Test circuit for measuring crosstalk voltage (between the digital input and the switch) 74HC_HCT2G66_6 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 06 — 2 April 2010 © NXP B.V. 2010. All rights reserved. 13 of 21 74HC2G66; 74HCT2G66 NXP Semiconductors Dual single-pole single-throw analog switch VCC 1E VIH 0.1 μF RL 2RL 1Y or 1Z 1Z or 1Y CHANNEL ON fi 2RL CL V VO1 V VO2 2E VIL VCC VCC 2RL 2RL 2Y or 2Z 2RL 2Z or 2Y CHANNEL OFF 2RL CL 001aai846 Adjust the switch input voltage for a 0 dBm level (0 dBm = 1 mW into 600 Ω) Fig 18. Test circuit for measuring crosstalk (between the switches) 74HC_HCT2G66_6 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 06 — 2 April 2010 © NXP B.V. 2010. All rights reserved. 14 of 21 74HC2G66; 74HCT2G66 NXP Semiconductors Dual single-pole single-throw analog switch 12. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm D E A SOT505-2 X c HE y v M A Z 5 8 A A2 (A3) A1 pin 1 index θ Lp L 1 4 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(1) e HE L Lp v w y Z(1) θ mm 1.1 0.15 0.00 0.95 0.75 0.25 0.38 0.22 0.18 0.08 3.1 2.9 3.1 2.9 0.65 4.1 3.9 0.5 0.47 0.33 0.2 0.13 0.1 0.70 0.35 8° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT505-2 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 02-01-16 --- Fig 19. Package outline SOT505-2 (TSSOP8) 74HC_HCT2G66_6 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 06 — 2 April 2010 © NXP B.V. 2010. All rights reserved. 15 of 21 74HC2G66; 74HCT2G66 NXP Semiconductors Dual single-pole single-throw analog switch VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm D E SOT765-1 A X c y HE v M A Z 5 8 Q A A2 A1 pin 1 index (A3) θ Lp 1 4 e L detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(2) e HE L Lp Q v w y Z(1) θ mm 1 0.15 0.00 0.85 0.60 0.12 0.27 0.17 0.23 0.08 2.1 1.9 2.4 2.2 0.5 3.2 3.0 0.4 0.40 0.15 0.21 0.19 0.2 0.13 0.1 0.4 0.1 8° 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT765-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 02-06-07 MO-187 Fig 20. Package outline SOT765-1 (VSSOP8) 74HC_HCT2G66_6 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 06 — 2 April 2010 © NXP B.V. 2010. All rights reserved. 16 of 21 74HC2G66; 74HCT2G66 NXP Semiconductors Dual single-pole single-throw analog switch XSON8U: plastic extremely thin small outline package; no leads; 8 terminals; UTLP based; body 3 x 2 x 0.5 mm B D SOT996-2 A A E A1 detail X terminal 1 index area e1 v w b e L1 1 4 8 5 C C A B C M M y y1 C L2 L X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max A1 b D E e e1 L L1 L2 v w y y1 mm 0.5 0.05 0.00 0.35 0.15 2.1 1.9 3.1 2.9 0.5 1.5 0.5 0.3 0.15 0.05 0.6 0.4 0.1 0.05 0.05 0.1 REFERENCES OUTLINE VERSION IEC SOT996-2 --- JEDEC JEITA --- EUROPEAN PROJECTION ISSUE DATE 07-12-18 07-12-21 Fig 21. Package outline SOT996-2 (XSON8U) 74HC_HCT2G66_6 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 06 — 2 April 2010 © NXP B.V. 2010. All rights reserved. 17 of 21 74HC2G66; 74HCT2G66 NXP Semiconductors Dual single-pole single-throw analog switch 13. Abbreviations Table 13. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic DUT Device Under Test 14. Revision history Table 14. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT2G66_6 20100402 Product data sheet - 74HC_HCT2G66_5 Modifications: 74HC_HCT2G66_5 Modifications: • Added type number 74HC2G66GD and 74HCT2G66GD (XSON8U package) 20090126 Product data sheet - 74HC_HCT2G66_4 • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • Legal texts have been adapted to the new company name where appropriate. • • Table 1 “Ordering information” and Section 12 “Package outline” package SOT765-1 added. Quick Reference Data and Soldering sections removed. Section 2 “Features and benefits” updated. 74HC_HCT2G66_4 20040519 Product specification - 74HC_HCT2G66_3 74HC_HCT2G66_3 20031126 Product specification - 74HC_HCT2G66_2 74HC_HCT2G66_2 20030808 Product specification - 74HC_HCT2G66_1 74HC_HCT2G66_1 20030625 Product specification - - 74HC_HCT2G66_6 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 06 — 2 April 2010 © NXP B.V. 2010. All rights reserved. 18 of 21 74HC2G66; 74HCT2G66 NXP Semiconductors Dual single-pole single-throw analog switch 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 15.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. The product is not designed, authorized or warranted to be 74HC_HCT2G66_6 Product data sheet suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer’s third party customer(s) (hereinafter both referred to as “Application”). It is customer’s sole responsibility to check whether the NXP Semiconductors product is suitable and fit for the Application planned. Customer has to do all necessary testing for the Application in order to avoid a default of the Application and the product. NXP Semiconductors does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 06 — 2 April 2010 © NXP B.V. 2010. All rights reserved. 19 of 21 74HC2G66; 74HCT2G66 NXP Semiconductors Dual single-pole single-throw analog switch 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74HC_HCT2G66_6 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 06 — 2 April 2010 © NXP B.V. 2010. All rights reserved. 20 of 21 NXP Semiconductors 74HC2G66; 74HCT2G66 Dual single-pole single-throw analog switch 17. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 10.1 10.2 10.3 11 11.1 11.2 11.3 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ON resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ON resistance test circuit and graphs. . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms and test circuit . . . . . . . . . . . . . . . . 8 Additional dynamic characteristics . . . . . . . . . 10 Test circuits and graphs . . . . . . . . . . . . . . . . . 11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 18 Legal information. . . . . . . . . . . . . . . . . . . . . . . 19 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Contact information. . . . . . . . . . . . . . . . . . . . . 20 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 2 April 2010 Document identifier: 74HC_HCT2G66_6