74LV4051 8-channel analog multiplexer/demultiplexer Rev. 04 — 10 August 2009 Product data sheet 1. General description The 74LV4051 is an 8-channel analog multiplexer/demultiplexer with three digital select inputs (S0 to S2), an active-LOW enable input (E), eight independent inputs/outputs (Y0 to Y7) and a common input/output (Z). It is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC4051 and 74HCT4051. With E LOW, one of the eight switches is selected (low impedance ON-state) by S0 to S2. With E HIGH, all switches are in the high-impedance OFF-state, independent of S0 to S2. VCC and GND are the supply voltage pins for the digital control inputs (S0 to S2, and E). The VCC to GND ranges are 1.0 V to 6.0 V. The analog inputs/outputs (Y0 to Y7, and Z) can swing between VCC as a positive limit and VEE as a negative limit. VCC − VEE may not exceed 6.0 V. For operation as a digital multiplexer/demultiplexer, VEE is connected to GND (typically ground). 2. Features n Optimized for low-voltage applications: 1.0 V to 6.0 V n Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V n Low ON resistance: u 145 Ω (typical) at VCC − VEE = 2.0 V u 80 Ω (typical) at VCC − VEE = 3.0 V u 60 Ω (typical) at VCC − VEE = 4.5 V n Logic level translation: u To enable 3 V logic to communicate with ±3 V analog signals n Typical ‘break before make’ built in n ESD protection: u HBM JESD22-A114E exceeds 2000 V u MM JESD22-A115-A exceeds 200 V n Multiple package options n Specified from −40 °C to +85 °C and from −40 °C to +125 °C 74LV4051 NXP Semiconductors 8-channel analog multiplexer/demultiplexer 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LV4051N −40 °C to +125 °C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 74LV4051D −40 °C to +125 °C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 74LV4051DB −40 °C to +125 °C SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 74LV4051PW −40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 74LV4051BQ −40 °C to +125 °C DHVQFN16 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 × 3.5 × 0.85 mm SOT763-1 4. Functional diagram VCC 16 13 Y0 S0 11 14 Y1 15 Y2 S1 10 12 Y3 LOGIC LEVEL CONVERSION 1-OF-8 DECODER S2 9 1 Y4 5 Y5 2 Y6 4 Y7 E 6 3 Z 8 GND Fig 1. 7 VEE 001aad543 Functional diagram 74LV4051_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 10 August 2009 2 of 26 74LV4051 NXP Semiconductors 8-channel analog multiplexer/demultiplexer 11 10 9 6 13 S0 S1 S2 14 11 10 15 9 12 1 5 2 E 6 4 3 0 8X 2 G8 Y0 Y1 MUX/DMUX 0 Y2 13 14 1 Y3 15 2 Y4 12 3 3 Y5 1 4 Y6 5 5 Y7 2 6 4 7 Z 001aad541 Fig 2. 0 7 Logic symbol 001aad542 Fig 3. IEC logic symbol Y VEE VCC VCC VCC VCC from logic VEE VEE Z 001aad544 Fig 4. Schematic diagram (one switch) 74LV4051_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 10 August 2009 3 of 26 74LV4051 NXP Semiconductors 8-channel analog multiplexer/demultiplexer 5. Pinning information 5.1 Pinning 74LV4051 Z 3 14 Y1 Y7 4 Y5 13 Y0 12 Y3 5 E 6 11 S0 VEE 7 10 S1 GND 8 9 S2 74LV4051 15 Y2 3 14 Y1 1 16 VCC Y6 2 15 Y2 Y7 4 13 Y0 Z 3 14 Y1 Y5 5 12 Y3 Y7 4 13 Y0 E 6 Y5 5 12 Y3 7 E 6 11 S0 VEE VEE 7 10 S1 GND 8 9 S2 Fig 6. Pin configuration SOT338-1 and SOT403-1 VCC(1) 11 S0 10 S1 001aak408 Transparent top view 001aak407 Pin configuration SOT38-4 and SOT109-1 2 Z Y4 001aak433 Fig 5. Y6 9 15 Y2 S2 2 Y4 Y6 terminal 1 index area 1 16 VCC 8 1 GND Y4 16 VCC 74LV4051 Fig 7. Pin configuration for SOT763-1 5.2 Pin description Table 2. Pin description Symbol Pin Description E 6 enable input (active LOW) VEE 7 supply voltage GND 8 ground supply voltage S0, S1, S2 11, 10, 9 select input Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7 13, 14, 15, 12, 1, 5, 2, 4 independent input or output Z 3 common output or input VCC 16 supply voltage 74LV4051_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 10 August 2009 4 of 26 74LV4051 NXP Semiconductors 8-channel analog multiplexer/demultiplexer 6. Functional description 6.1 Function table Table 3. Function table[1] Input Channel ON E S2 S1 S0 L L L L Y0 to Z L L L H Y1 to Z L L H L Y2 to Z L L H H Y3 to Z L H L L Y4 to Z L H L H Y5 to Z L H H L Y6 to Z L H H H Y7 to Z H X X X switches off [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground). Symbol Parameter Conditions supply voltage VCC Min Max Unit [1] −0.5 +7.0 V input clamping current VI < −0.5 V or VI > VCC + 0.5 V [2] - ±20 mA ISK switch clamping current VSW < −0.5 V or VSW > VCC + 0.5 V [2] - ±20 mA ISW switch current VSW > −0.5 V or VSW < VCC + 0.5 V; source or sink current [2] - ±25 mA Tstg storage temperature −65 +150 °C Tamb = −40 °C to +125 °C [3] DIP16 package - 750 mW SO16 package - 500 mW TSSOP16 package - 500 mW DHVQFN16 package - 500 mW IIK total power dissipation Ptot [1] To avoid drawing VCC current out of terminal Z, when switch current flows into terminals Yn, the voltage drop across the bidirectional switch must not exceed 0.4 V. If the switch current flows into terminal Z, no VCC current will flow out of terminals Yn, and in this case there is no limit for the voltage drop across the switch, but the voltages at Yn and Z may not exceed VCC or VEE. [2] The minimum input voltage rating may be exceeded if the input current rating is observed. [3] For DIP16 packages: above 70 °C the value of Ptot derates linearly with 12 mW/K. For SO16 packages: above 70 °C the value of Ptot derates linearly with 8 mW/K. For SSOP16 and TSSOP16 packages: above 60 °C the value of Ptot derates linearly with 5.5 mW/K. For DHVQFN16 packages: above 60 °C the value of Ptot derates linearly with 4.5 mW/K. 74LV4051_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 10 August 2009 5 of 26 74LV4051 NXP Semiconductors 8-channel analog multiplexer/demultiplexer 8. Recommended operating conditions Table 5. Recommended operating conditions[1] Symbol Parameter Conditions Min Typ Max Unit VCC supply voltage see Figure 8 1 3.3 6 V VI input voltage 0 - VCC V VSW switch voltage 0 - VCC V Tamb ambient temperature −40 - +125 °C ∆t/∆V input transition rise and fall rate VCC = 1.0 V to 2.0 V - - 500 ns/V VCC = 2.0 V to 2.7 V - - 200 ns/V VCC = 2.7 V to 3.6 V - - 100 ns/V [1] in free air The static characteristics are guaranteed from VCC = 1.2 V to 6.0 V, but LV devices are guaranteed to function down to VCC = 1.0 V (with input levels GND or VCC). 001aak344 8.0 VCC - GND (V) 6.0 operating area 4.0 2.0 0 0 Fig 8. 2.0 4.0 6.0 8.0 VCC - VEE (V) Guaranteed operating area as a function of the supply voltages 74LV4051_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 10 August 2009 6 of 26 74LV4051 NXP Semiconductors 8-channel analog multiplexer/demultiplexer 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter HIGH-level input voltage VIH LOW-level input voltage VIL input leakage current II IS(OFF) IS(ON) OFF-state leakage current ON-state leakage current supply current ICC ∆ICC additional supply current CI input capacitance Csw switch capacitance [1] Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ[1] Max Min Max VCC = 1.2 V 0.9 - - 0.9 - V VCC = 2.0 V 1.4 - - 1.4 - V VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V VCC = 4.5 V 3.15 - - 3.15 - V VCC = 6.0 V 4.20 - - 4.20 - V VCC = 1.2 V - - 0.3 - 0.3 V VCC = 2.0 V - - 0.6 - 0.6 V VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V VCC = 4.5 V - - 1.35 - 1.35 V VCC = 6.0 V - - 1.80 - 1.80 V VCC = 3.6 V - - 1.0 - 1.0 µA VCC = 6.0 V - - 2.0 - 2.0 µA VCC = 3.6 V - - 1.0 - 1.0 µA VCC = 6.0 V - - 2.0 - 2.0 µA VCC = 3.6 V - - 1.0 - 1.0 µA VCC = 6.0 V - - 2.0 - 2.0 µA VCC = 3.6 V - - 20 - 40 µA VCC = 6.0 V - - 40 - 80 µA per input; VI = VCC − 0.6 V; VCC = 2.7 V to 3.6 V - - 500 - 850 µA - 3.5 - - - pF independent pins Yn - 5 - - - pF common pin Z - 25 - - - pF VI = VCC or GND VI = VIH or VIL; see Figure 9 VI = VIH or VIL; see Figure 10 VI = VCC or GND; IO = 0 A Typical values are measured at Tamb = 25 °C. 74LV4051_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 10 August 2009 7 of 26 74LV4051 NXP Semiconductors 8-channel analog multiplexer/demultiplexer 9.1 Test circuits VCC VCC S0 to S2 VIH or VIL S0 to S2 VIH or VIL Z Yn Z E IS IS GND = VEE Yn VCC GND = VEE GND VI VO IS E VO VI 001aak409 001aak410 VI = VCC or VEE and VO = VEE or VCC. VI = VCC or VEE and VO = open circuit. Fig 9. Test circuit for measuring OFF-state leakage current Fig 10. Test circuit for measuring ON-state leakage current 9.2 ON resistance Table 7. ON resistance At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for graphs see Figure 11 and Figure 12. Symbol Parameter RON(peak) ON resistance (peak) −40 °C to +85 °C Conditions Min Max Min Max - - - - - Ω - 145 325 - 375 Ω VI = 0 V to VCC − VEE VCC = 1.2 V; ISW = 100 µA [2] VCC = 2.0 V; ISW = 1000 µA ∆RON VCC = 2.7 V; ISW = 1000 µA - 90 200 - 235 Ω VCC = 3.0 V to 3.6 V; ISW = 1000 µA - 80 180 - 210 Ω VCC = 4.5 V; ISW = 1000 µA - 60 135 - 160 Ω VCC = 6.0 V; ISW = 1000 µA - 55 125 - 145 Ω - - - - - Ω - 5 - - - Ω ON resistance mismatch VI = 0 V to VCC − VEE between channels VCC = 1.2 V; ISW = 100 µA [2] VCC = 2.0 V; ISW = 1000 µA VCC = 2.7 V; ISW = 1000 µA - 4 - - - Ω VCC = 3.0 V to 3.6 V; ISW = 1000 µA - 4 - - - Ω VCC = 4.5 V; ISW = 1000 µA - 3 - - - Ω VCC = 6.0 V; ISW = 1000 µA - 2 - - - Ω 74LV4051_4 Product data sheet −40 °C to +125 °C Unit Typ[1] © NXP B.V. 2009. All rights reserved. Rev. 04 — 10 August 2009 8 of 26 74LV4051 NXP Semiconductors 8-channel analog multiplexer/demultiplexer Table 7. ON resistance …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for graphs see Figure 11 and Figure 12. Symbol RON(rail) Parameter ON resistance (rail) −40 °C to +85 °C Conditions Min Max Min Max - 225 - - - Ω VCC = 2.0 V; ISW = 1000 µA - 110 235 - 270 Ω VCC = 2.7 V; ISW = 1000 µA - 70 145 - 165 Ω VCC = 3.0 V to 3.6 V; ISW = 1000 µA - 60 130 - 150 Ω VCC = 4.5 V; ISW = 1000 µA - 45 100 - 115 Ω VCC = 6.0 V; ISW = 1000 µA - 40 85 - 100 Ω - 250 - - - Ω VCC = 2.0 V; ISW = 1000 µA - 120 320 - 370 Ω VCC = 2.7 V; ISW = 1000 µA - 75 195 - 225 Ω VCC = 3.0 V to 3.6 V; ISW = 1000 µA - 70 175 - 205 Ω VCC = 4.5 V; ISW = 1000 µA - 50 130 - 150 Ω VCC = 6.0 V; ISW = 1000 µA - 45 120 - 135 Ω VI = GND VCC = 1.2 V; ISW = 100 µA RON(rail) ON resistance (rail) −40 °C to +125 °C Unit Typ[1] [2] VI = VCC − VEE VCC = 1.2 V; ISW = 100 µA [2] [1] Typical values are measured at Tamb = 25 °C. [2] When supply voltages (VCC − VEE) near 1.2 V the analog switch ON resistance becomes extremely non-linear. When using a supply of 1.2 V, it is recommended to use these devices only for transmitting digital signals. 74LV4051_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 10 August 2009 9 of 26 74LV4051 NXP Semiconductors 8-channel analog multiplexer/demultiplexer 9.3 On resistance waveform and test circuit V VSW VCC S0 to S2 VIH or VIL Z Yn E GND = VEE GND ISW VI 001aak411 RON = VSW / ISW. Fig 11. Test circuit for measuring RON 001aak412 180 RON (Ω) VCC = 2.0 V 120 VCC = 3.0 V VCC = 4.5 V 60 0 0 1.2 2.4 3.6 4.8 VI (V) Vi = 0 V to VCC − VEE Fig 12. Typical RON as a function of input voltage 74LV4051_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 10 August 2009 10 of 26 74LV4051 NXP Semiconductors 8-channel analog multiplexer/demultiplexer 10. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 15. Symbol Parameter tpd −40 °C to +85 °C Conditions Min Max Min Max VCC = 1.2 V - 25 - - - ns VCC = 2.0 V - 9 17 - 20 ns - 6 13 - 15 ns - 5 10 - 12 ns - 4 9 - 10 ns - 3 8 - 8 ns VCC = 1.2 V - 145 - - - ns VCC = 2.0 V - 49 94 - 112 ns propagation delay Yn to Z, Z to Yn; see Figure 13 VCC = 3.0 V to 3.6 V [3] VCC = 4.5 V VCC = 6.0 V enable time E to Yn, Z; see Figure 14 [2] VCC = 2.7 V - 36 69 - 83 ns VCC = 3.0 V to 3.6 V; CL = 15 pF [3] - 23 - - - ns VCC = 3.0 V to 3.6 V [3] - 28 55 - 66 ns - 25 47 - 56 ns - 19 38 - 43 ns VCC = 1.2 V - 140 - - - ns VCC = 2.0 V - 48 90 - 107 ns VCC = 4.5 V VCC = 6.0 V Sn to Yn; see Figure 14 [2] VCC = 2.7 V - 35 66 - 79 ns VCC = 3.0 V to 3.6 V; CL = 15 pF [3] - 22 - - - ns VCC = 3.0 V to 3.6 V [3] - 27 53 - 63 ns VCC = 4.5 V - 24 45 - 54 ns VCC = 6.0 V - 18 34 - 41 ns 74LV4051_4 Product data sheet Unit [2] VCC = 2.7 V ten −40 °C to +125 °C Typ[1] © NXP B.V. 2009. All rights reserved. Rev. 04 — 10 August 2009 11 of 26 74LV4051 NXP Semiconductors 8-channel analog multiplexer/demultiplexer Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 15. Symbol Parameter tdis disable time −40 °C to +85 °C Conditions Min VCC = 1.2 V - 145 - - - ns VCC = 2.0 V - 51 93 - 110 ns E to Yn, Z; see Figure 14 Min Max - 38 69 - 82 ns VCC = 3.0 V to 3.6 V; CL = 15 pF - 25 - - - ns VCC = 3.0 V to 3.6 V [3] - 30 56 - 66 ns - 29 48 - 56 ns - 21 37 - 44 ns VCC = 1.2 V - 115 - - - ns VCC = 2.0 V - 41 73 - 90 ns VCC = 6.0 V Sn to Yn; see Figure 14 [2] VCC = 2.7 V - 31 54 - 67 ns VCC = 3.0 V to 3.6 V; CL = 15 pF [3] - 20 - - - ns VCC = 3.0 V to 3.6 V [3] - 24 44 - 54 ns - 22 37 - 46 ns - 17 29 - 36 ns - 25 - - - pF VCC = 4.5 V VCC = 6.0 V CL = 50 pF; fi = 1 MHz; VI = GND to VCC [1] All typical values are measured at Tamb = 25 °C. [2] tpd is the same as tPLH and tPHL. ten is the same as tPZL and tPZH. tdis is the same as tPLZ and tPHZ. [3] Typical values are measured at nominal supply voltage (VCC = 3.3 V). [4] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ((CL + CSW) × VCC2 × fo) where: fi = input frequency in MHz, fo = output frequency in MHz CL = output load capacitance in pF CSW = maximum switch capacitance in pF; VCC = supply voltage in Volts N = number of inputs switching Σ(CL × VCC2 × fo) = sum of the outputs. [4] 74LV4051_4 Product data sheet Max [3] VCC = 4.5 V power dissipation capacitance Unit [2] VCC = 2.7 V CPD −40 °C to +125 °C Typ[1] © NXP B.V. 2009. All rights reserved. Rev. 04 — 10 August 2009 12 of 26 74LV4051 NXP Semiconductors 8-channel analog multiplexer/demultiplexer 10.1 Waveforms VCC Yn or Z input VM VEE tPLH tPHL VO Z or Yn output VM VEE 001aak418 Measurement points are given in Table 9. VOL and VOH are typical voltage output levels that occur with the output load. Fig 13. Propagation delay input (An) to output (Yn) VCC Sn, E input VM VSS tPLZ Yn or Z output LOW-to-OFF OFF-to-LOW tPZL VO 90 % 10 % VEE tPHZ VO tPZH 90 % Yn or Z output HIGH-to-OFF OFF-to-HIGH 10 % VEE switch ON switch OFF switch ON 001aak419 Measurement points are given in Table 9. VOL and VOH are typical voltage output levels that occur with the output load. Fig 14. Enable and disable times Table 9. Measurement points Supply voltage Input Output VCC VM VM VX VY < 2.7 V 0.5VCC 0.5VCC VOL + 0.1VCC VOH − 0.1VCC 2.7 V to 3.6 V 1.5 V 1.5 V VOL + 0.3 V VOH − 0.3 V > 3.6 V 0.5VCC 0.5VCC VOL + 0.1VCC VOH − 0.1VCC 74LV4051_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 10 August 2009 13 of 26 74LV4051 NXP Semiconductors 8-channel analog multiplexer/demultiplexer VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VEXT VCC VI RL VO G DUT RT VEE CL RL 001aak353 Test data is given in Table 10. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 15. Test circuit for measuring switching times Table 10. Test data Supply voltage Input VCC VI tr, tf Load CL RL VEXT tPHL, tPLH tPZH, tPHZ tPZL, tPLZ < 2.7 V VCC ≤ 6 ns 50 pF 1 kΩ open VEE 2VCC 2.7 V to 3.6 V 2.7 V ≤ 6 ns 15 pF, 50 pF 1 kΩ open VEE 2VCC > 3.6 V VCC ≤ 6 ns 50 pF 1 kΩ open VEE 2VCC 74LV4051_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 10 August 2009 14 of 26 74LV4051 NXP Semiconductors 8-channel analog multiplexer/demultiplexer 10.2 Additional dynamic parameters Table 11. Additional dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); VI = GND or VCC (unless otherwise specified); tr = tf ≤ 6.0 ns; Tamb = 25 °C. Symbol Parameter Conditions THD fi = 1 kHz; CL = 50 pF; RL = 10 kΩ; see Figure 20 total harmonic distortion Min Typ Max Unit VCC = 3.0 V; VI = 2.75 V (p-p) - 0.8 - % VCC = 6.0 V; VI = 5.5 V (p-p) - 0.4 - % fi = 10 kHz; CL = 50 pF; RL = 10 kΩ; see Figure 20 f(−3dB) VCC = 3.0 V; VI = 2.75 V (p-p) - 2.4 - % VCC = 6.0 V; VI = 5.5 V (p-p) - 1.2 - % - 180 - MHz - 200 - MHz - −50 - dB - −50 - dB VCC = 3.0 V - 0.11 - V VCC = 6.0 V - 0.12 - V VCC = 3.0 V - −60 - dB VCC = 6.0 V - −60 - dB −3 dB frequency response CL = 50 pF; RL = 50 Ω; see Figure 16 isolation (OFF-state) fi = 1 MHz; CL = 50 pF; RL = 600 Ω; see Figure 18 [1] VCC = 3.0 V VCC = 6.0 V αiso [2] VCC = 3.0 V VCC = 6.0 V crosstalk voltage Vct Xtalk crosstalk between digital inputs and switch; fi = 1 MHz; CL = 50 pF; RL = 600 Ω; see Figure 21 between switches; fi = 1 MHz; CL = 50 pF; RL = 600 Ω; see Figure 22 [1] Adjust fi voltage to obtain 0 dBm level at output for 1 MHz (0 dBm = 1 mW into 50 Ω). [2] Adjust fi voltage to obtain 0 dBm level at output for 1 MHz (0 dBm = 1 mW into 600 Ω). 74LV4051_4 Product data sheet [2] © NXP B.V. 2009. All rights reserved. Rev. 04 — 10 August 2009 15 of 26 74LV4051 NXP Semiconductors 8-channel analog multiplexer/demultiplexer 10.2.1 Test circuits 001aak361 5 (dB) VCC VCC VIH or VIL S0 to S2 Z 0 2RL Yn E 0.1 µF GND = VEE GND 2RL CL dB fi −5 10 102 103 104 105 106 f (kHz) 001aak420 VCC = 3.0 V; GND = 0 V; VEE = −3.0 V; RL = 50 Ω; RSOURCE = 1 kΩ. Fig 16. Test circuit for measuring frequency response Fig 17. Typical frequency response 001aak360 0 (dB) VCC VCC VIH or VIL S0 to S2 Z 0.1 µF VCC −50 2RL Yn E GND = VEE 2RL CL dB fi −100 10 102 103 104 105 106 f (kHz) 001aak421 VCC = 3.0 V; GND = 0 V; VEE = −3.0 V; RL = 50 Ω; RSOURCE = 1 kΩ. Fig 18. Test circuit for measuring isolation (OFF-state) Fig 19. Typical isolation (OFF-state) as function of frequency 74LV4051_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 10 August 2009 16 of 26 74LV4051 NXP Semiconductors 8-channel analog multiplexer/demultiplexer VCC VCC S0 to S2 VIH or VIL Z 2RL Yn E 10 µF GND = VEE GND 2RL CL D fi 001aak422 Fig 20. Test circuit for measuring total harmonic distortion VCC VCC VCC 2RL S0 to S2 Z 2RL Yn E 2RL G GND = VEE VIH or VIL 2RL CL V VO 001aak423 a. Test circuit logic input (Sn, E) off on off Vct VO 001aaj908 b. Input and output pulse definitions VI may be connected to Sn or E. Fig 21. Test circuit for measuring crosstalk voltage between digital inputs and switch 74LV4051_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 10 August 2009 17 of 26 74LV4051 NXP Semiconductors 8-channel analog multiplexer/demultiplexer VCC VCC VCC 2RL VIH or VIL RL S0 to S2 Y0 Z Yn 2RL E 0.1 µF GND = VEE GND 2RL VO CL 2RL dB VI 001aak434 a. Switch closed condition VCC VCC VCC 2RL VCC 2RL VIH or VIL S0 to S2 Y0 Z Yn 2RL E GND = VEE GND RL 2RL VO VI 2RL CL dB 001aak435 b. Switch open condition Fig 22. Test circuit for measuring crosstalk between switches 74LV4051_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 10 August 2009 18 of 26 74LV4051 NXP Semiconductors 8-channel analog multiplexer/demultiplexer 11. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b b2 MH 9 16 pin 1 index E 1 8 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 b2 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.30 0.53 0.38 1.25 0.85 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 0.76 inches 0.17 0.02 0.13 0.068 0.051 0.021 0.015 0.049 0.033 0.014 0.009 0.77 0.73 0.26 0.24 0.1 0.3 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.03 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 95-01-14 03-02-13 SOT38-4 Fig 23. Package outline SOT38-4 (DIP16) 74LV4051_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 10 August 2009 19 of 26 74LV4051 NXP Semiconductors 8-channel analog multiplexer/demultiplexer SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.16 0.15 0.05 0.244 0.041 0.228 0.01 0.01 0.028 0.004 0.012 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 24. Package outline SOT109-1 (SO16) 74LV4051_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 10 August 2009 20 of 26 74LV4051 NXP Semiconductors 8-channel analog multiplexer/demultiplexer SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm D SOT338-1 E A X c y HE v M A Z 9 16 Q A2 A (A 3) A1 pin 1 index θ Lp L 8 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.00 0.55 8 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 Fig 25. Package outline SOT338-1 (SSOP16) 74LV4051_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 10 August 2009 21 of 26 74LV4051 NXP Semiconductors 8-channel analog multiplexer/demultiplexer TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 E D A X c y HE v M A Z 9 16 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 8 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig 26. Package outline SOT403-1 (TSSOP16) 74LV4051_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 10 August 2009 22 of 26 74LV4051 NXP Semiconductors 8-channel analog multiplexer/demultiplexer DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT763-1 16 terminals; body 2.5 x 3.5 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 7 y y1 C v M C A B w M C b L 1 8 Eh e 16 9 15 10 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. A1 b 1 0.05 0.00 0.30 0.18 c D (1) Dh E (1) Eh 0.2 3.6 3.4 2.15 1.85 2.6 2.4 1.15 0.85 e 0.5 e1 L v w y y1 2.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT763-1 --- MO-241 --- EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 27. Package outline SOT763-1 (DHVQFN16) 74LV4051_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 10 August 2009 23 of 26 74LV4051 NXP Semiconductors 8-channel analog multiplexer/demultiplexer 12. Abbreviations Table 12. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 13. Revision history Table 13. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LV4051_4 20090810 Product data sheet - 74LV4051_3 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • Legal texts have been adapted to the new company name where appropriate. Added type number 74LV4051BQ (DHVQFN16 package) 74LV4051_3 19960623 Product specification - 74LV4051_2 74LV4051_2 19970715 Product specification - 74LV4051_1 74LV4051_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 10 August 2009 24 of 26 74LV4051 NXP Semiconductors 8-channel analog multiplexer/demultiplexer 14. Legal information 14.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 14.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 14.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 14.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 15. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74LV4051_4 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 04 — 10 August 2009 25 of 26 74LV4051 NXP Semiconductors 8-channel analog multiplexer/demultiplexer 16. Contents 1 2 3 4 5 5.1 5.2 6 6.1 7 8 9 9.1 9.2 9.3 10 10.1 10.2 10.2.1 11 12 13 14 14.1 14.2 14.3 14.4 15 16 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 ON resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 8 On resistance waveform and test circuit . . . . . 10 Dynamic characteristics . . . . . . . . . . . . . . . . . 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Additional dynamic parameters . . . . . . . . . . . 15 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 19 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 24 Legal information. . . . . . . . . . . . . . . . . . . . . . . 25 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 25 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Contact information. . . . . . . . . . . . . . . . . . . . . 25 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 10 August 2009 Document identifier: 74LV4051_4