INTEGRATED CIRCUITS 74ALS646/74ALS646–1 74ALS648/74ALS648–1 Transceiver/register Product specification IC05 Data Handbook 1991 Feb 08 Philips Semiconductors Product specification 74ALS646/74ALS646-1 74ALS648/74ALS648-1 Transceiver/register 74ALS646/646-1 74ALS648/648-1 Octal transceiver/register, non-inverting (3-State) Octal transceiver/register, inverting (3-State) FEATURES • Combines TYPICAL fMAX TYPICAL SUPPLY CURRENT (TOTAL) 74ALS646/646-1 140MHz 48mA 74ALS648/648-1 140MHz 54mA TYPE 74ALS245 and two 74ALS374 type functions in one chip • Independent registers for A and B buses • Multiplexed real-time and stored data • Choice of non-inverting and inverting data paths • 3-State outputs • The -1 version sink 48mA IOL within the ±5% VCC range ORDERING INFORMATION ORDER CODE 24-pin plastic DIP 74ALS646N, 74ALS646-1N, 74ALS648N, 74ALS648-1N SOT222-1 24-pin plastic SOL 74ALS646D, 74ALS646-1D, 74ALS648D, 74ALS648-1D SOT137-1 DESCRIPTION The 74ALS646/74ALS646-1 and 74ALS648/74ALS648-1 transceivers/registers consist of bus transceiver circuits with 3-State outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes High. Output enable (OE) and direction (DIR) and select (SAB, SBA) pins are provided for bus management. DRAWING NUMBER DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C The 74ALS646-1 and 74ALS648-1 will sink 48mA if the VCC is limited to 5.0V ±0.25V. INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS DESCRIPTION 74ALS (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW A0 – A7 A inputs 1.0/1.0 20µA/0.1mA B0 – B7 B inputs 1.0/1.0 20µA/0.1mA CPAB A-to-B clock input 1.0/1.0 20µA/0.1mA CPBA B-to-A clock input 1.0/1.0 20µA/0.1mA SAB A-to-B select input 1.0/1.0 20µA/0.1mA SBA B-to-A select input 1.0/1.0 20µA/0.1mA DIR Data flow directional control input 1.0/1.0 20µA/0.1mA OE Output enable input 1.0/1.0 20µA/0.1mA A0 – A7, B0 – B7 Data outputs 750/240 15mA/24mA A0 – A7, B0 – B7 Data outputs (-1 version) 750/480 15mA/48mA NOTE: One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state. 1991 Feb 08 2 853–1408 01670 Philips Semiconductors Product specification 74ALS646/74ALS646-1 74ALS648/74ALS648-1 Transceiver/register PIN CONFIGURATION – 74ALS646/646-1 CPAB 1 24 VCC SAB 2 DIR 3 A0 PIN CONFIGURATION – 74ALS648/648-1 CPAB 1 24 VCC 23 CPBA SAB 2 23 CPBA 22 SBA DIR 3 22 SBA 4 21 OE A0 4 21 OE A1 5 20 B0 A1 5 20 B0 A2 6 19 B1 A2 6 19 B1 A3 7 18 B2 A3 7 18 B2 A4 8 17 B3 A4 8 17 B3 A5 9 16 B4 A5 9 16 B4 A6 10 15 B5 A6 10 15 B5 A7 11 14 B6 A7 11 14 B6 GND 12 13 B7 GND 12 13 B7 SC00118 SC00119 LOGIC SYMBOL – 74ALS646/646-1 4 5 6 7 8 9 10 LOGIC SYMBOL – 74ALS648/648-1 11 4 A0 A1 A2 A3 A4 A5 A6 A7 1 CPAB 2 3 23 22 21 SAB DIR SPBA SBA OE 20 19 18 17 16 15 14 13 23 22 1 2 CPAB 2 3 23 22 21 SAB DIR SPBA SBA OE 21 3 3 EN1 [BA] 3 EN2 [AB] 23 C4 G5 22 1 C6 2 G7 1 5 1 5 7 6D 1 7 4D 8 9 10 11 20 19 18 17 16 15 14 13 SC00121 IEC/IEEE SYMBOL – 74ALS648/648-1 G3 4 5 1 VCC = Pin 24 GND = Pin 12 IEC/IEEE SYMBOL – 74ALS646/646-1 21 7 B0 B1 B2 B3 B4 B5 B6 B7 SC00120 3 6 A0 A1 A2 A3 A4 A5 A6 A7 B0 B1 B2 B3 B4 B5 B6 B7 VCC = Pin 24 GND = Pin 12 5 20 G3 3 EN1 [BA] 3 EN2 [AB] C4 G5 C6 G7 1 4 5 1 1 1 5 7 6D 2 1 7 4D 20 1 1 2 19 5 6 18 6 18 7 17 7 17 8 16 8 16 9 15 9 15 10 14 10 14 11 13 11 13 SC00122 1991 Feb 08 19 SC00123 3 Philips Semiconductors Product specification 74ALS646/74ALS646-1 74ALS648/74ALS648-1 Transceiver/register BUS MANAGEMENT FUNCTIONS The following examples demonstrate the four fundamental bus-management functions that can be performed with the 74ALS646/646-1 and 74ALS648/648-1. The select pins determine whether data is stored or transferred through the device in real time. The DIR determines which bus will receive data when the OE pin is Low. REAL TIME BUS TRANSFER BUS B TO BUS A BUS A BUS B OE DIR CPAB CPBA SAB SBA L L X X X L STORAGE FROM A, B, OR A AND B REAL TIME BUS TRANSFER BUS A TO BUS B BUS A BUS A BUS B OE DIR CPAB CPBA SAB SBA L H X X L X BUS B OE DIR CPAB CPBA SAB SBA X X ↑ X X X X X X ↑ X X H X ↑ ↑ X X TRANSFER STORED DATA TO A AND/OR B BUS A BUS B OE DIR CPAB CPBA SAB SBA L L X H or L X H L H H or L X H X SF00392 1991 Feb 08 4 Philips Semiconductors Product specification 74ALS646/74ALS646-1 74ALS648/74ALS648-1 Transceiver/register LOGIC SYMBOL – 74ALS646/646-1 OE LOGIC SYMBOL – 74ALS648/648-1 21 OE 3 DIR 23 CPBA 22 SBA 1 CPAB 2 SAB 21 3 DIR 23 CPBA 22 SBA 1 CPAB 2 SAB 1 OF 8 CHANNELS 1 OF 8 CHANNELS 1D C1 A0 1D C1 4 20 A0 4 20 B0 B0 1D 1D C1 VCC = Pin 24 GND = Pin 12 C1 VCC = Pin 24 GND = Pin 12 TO 7 OTHER CHANNELS SC00124 TO 7 OTHER CHANNELS SC00125 FUNCTION TABLE INPUTS OE DIR X X H X H X L L L L L L DATA I/O CPAB CPBA SAB SBA X ↑ X X X X ↑ X ↑ ↑ H or L H or L X X X H or L H X H H or L OPERATING MODE An Bn 74ALS646/74ALS646-1 74ALS648/74ALS648-1 X Input Unspecified* Store A, B unspecified* Store A, B unspecified* X Unspecified* Input Store B, A unspecified* Store B, A unspecified* X X Input Input Store A and B data Store A and B data X X Input Input Isolation, hold storage Isolation, hold storage X L Output Input Real time B data to A bus Real time B data to A bus X H Output Input Stored B data to A bus Stored B data to A bus X L X Input Output Real time A data to B bus Real time A data to B bus X H X Input Output Stored A data to B bus Stored A data to B bus NOTES: H = High voltage level L = Low voltage level X = Don’t care * = The data output function may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every Low-to-High transition of the clock. ↑ = Low-to-High clock transition 1991 Feb 08 5 Philips Semiconductors Product specification 74ALS646/74ALS646-1 74ALS648/74ALS648-1 Transceiver/register ABSOLUTE MAXIMUM RATINGS (Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) PARAMETER SYMBOL RATING UNIT VCC Supply voltage –0.5 to +7.0 V VIN Input voltage –0.5 to +7.0 V IIN Input current VOUT Voltage applied to output in High output state IOUT O Current applied to output in Low output state Tamb Operating free-air temperature range Tstg Storage temperature range All versions -1 version –30 to +5 mA –0.5 to VCC V 48 mA 96 mA 0 to +70 °C –65 to +150 °C RECOMMENDED OPERATING CONDITIONS LIMITS PARAMETER SYMBOL MIN NOM MAX 5.0 5.5 UNIT VCC Supply voltage 4.5 V VIH High-level input voltage 2.0 VIL Low-level input voltage 0.8 V V IIK Input clamp current –18 mA IOH High-level output current –15 mA All versions 24 mA IOL O Low level output current Low-level -1 version 48 1 mA +70 °C Tamb Operating free-air temperature range 0 NOTE: 1. The 48mA limit applies only under the condition of VCC = 5.0V ±5%. 1991 Feb 08 6 Philips Semiconductors Product specification 74ALS646/74ALS646-1 74ALS648/74ALS648-1 Transceiver/register DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL VOH TEST CONDITIONS1 PARAMETER VCC±10%,, VIL = MAX,, VIH = MIN High-level High level out output ut voltage VCC = MIN, VIL = MAX, VIH = MIN VOL VIK II All versions VCC = MIN,, VIL = MAX,, VIH = MIN -1 versions VCC = 4.75V, VIL = MAX, VIH = MIN Low-level Low level out output ut voltage Input clamp voltage LIMITS MIN IOH = –0.4mA VCC – 2 IOH = –3mA 2.4 IOH = –15mA 2.0 MAX UNIT V 3.2 V V IOL = 12mA 0.25 0.40 V IOL = 24mA 0.35 0.50 V IOL = 48mA 0.35 0.50 V –0.73 –1.5 V VCC = MIN, II = IIK Input current at maximum input voltage TYP2 control inputs VCC = MAX, VI = 7.0V 0.1 mA A or B ports VCC = MAX, VI = 5.5V 0.1 mA IIH High-level input current3 VCC = MAX, VI = 2.7V 20 µA IIL Low-level input current3 VCC = MAX, VI = 0.4V –0.1 mA IO Output current4 VCC = MAX, VO = 2.25V –30 ICCH ICC Supply current (total) ICCL VCC = MAX ICCZ –112 mA 40 57 mA 53 78 mA 51 72 mA NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. For I/O ports, the parameter IIH and IIL include the off-state current. 4. The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. AC ELECTRICAL CHARACTERISTICS FOR 74ALS646/74ALS646-1 LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = 0°C to +70°C VCC = +5.0V ± 10% CL = 50pF, RL = 500Ω MIN UNIT MAX fmax Maximum clock frequency Waveform 1 100 tPLH tPHL Propagation delay CPBA to An, CPAB to Bn Waveform 1 5.0 6.0 13.0 13.0 ns tPLH tPHL Propagation delay An to Bn or Bn to An Waveform 2, 3 2.0 3.0 8.0 9.0 ns tPLH tPHL Propagation delay SBA to An or SAB to Bn (A or B Low) Waveform 2, 3 5.0 5.0 13.0 11.0 ns tPLH tPHL Propagation delay SBA to An or SAB to Bn (A or B High) Waveform 2, 3 5.0 5.0 11.0 11.0 ns tPZH tPZL Output enable time OE to An or Bn Waveform 5 Waveform 6 3.0 5.0 9.0 11.0 ns tPHZ tPLZ Output disable time OE to An or Bn Waveform 5 Waveform 6 2.0 3.0 8.0 10.0 ns tPZH tPZL Output enable time DIR to An or Bn Waveform 5 Waveform 6 2.0 5.0 10.0 12.0 ns tPHZ tPLZ Output disable time DIR to An or Bn Waveform 5 Waveform 6 2.0 3.0 10.0 13.0 ns 1991 Feb 08 7 MHz Philips Semiconductors Product specification 74ALS646/74ALS646-1 74ALS648/74ALS648-1 Transceiver/register AC ELECTRICAL CHARACTERISTICS FOR 74ALS648/74ALS648-1 LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = 0°C to +70°C VCC = +5.0V ± 10% CL = 50pF, RL = 500Ω MIN fmax Maximum clock frequency tPLH tPHL Propagation delay CPBA to An, CPAB to Bn tPLH tPHL UNIT MAX Waveform 1 100 Waveform 1 5.0 6.0 13.0 13.0 MHz ns Propagation delay An to Bn or Bn to An Waveform 2, 3 1.0 3.0 7.0 9.0 ns tPLH tPHL Propagation delay SBA to An or SAB to Bn (A or B Low) Waveform 2, 3 5.0 5.0 13.0 11.0 ns tPLH tPHL Propagation delay SBA to An or SAB to Bn (A or B High) Waveform 2, 3 4.0 5.0 11.0 11.0 ns tPZH tPZL Output enable time OE to An or Bn Waveform 5 Waveform 6 2.0 4.0 8.0 13.0 ns tPHZ tPLZ Output disable time OE to An or Bn Waveform 5 Waveform 6 1.0 2.0 8.0 10.0 ns tPZH tPZL Output enable time DIR to An or Bn Waveform 5 Waveform 6 3.0 5.0 10.0 12.0 ns tPHZ tPLZ Output disable time DIR to An or Bn Waveform 5 Waveform 6 2.0 2.0 11.0 11.0 ns AC SETUP REQUIREMENTS LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = 0°C to +70°C VCC = +5.0V ± 10% CL = 50pF, RL = 500Ω UNIT tsu (H) tsu (L) Setup time, High or Low An or Bn to CPAB or CPBA Waveform 4 5.0 5.0 ns th (H) th (L) Hold time, High or Low An or Bn to CPAB or CPBA Waveform 4 0.0 1.0 ns tw (H) tw (L) Pulse width, High or Low CPAB or CPBA Waveform 1 6.0 4.0 ns 1991 Feb 08 8 Philips Semiconductors Product specification 74ALS646/74ALS646-1 74ALS648/74ALS648-1 Transceiver/register AC WAVEFORMS For all waveforms, VM = 1.3V. The shaded areas indicate when the input is permitted to change for predictable output performance. 1/fmax CPBA or CPAB VM An or Bn VM tw(H) VM SBA or SAB VM VM tPHL tPHL VM VM An or Bn tPLH tPLH tw(L) VM Bn or An VM An or Bn SF00394 SF00395 Waveform 2. Waveform 1. Propagation Delay for Clock Input to Output, Clock Pulse Width, and Maximum Clock Frequency An or Bn VM tPLH Bn or An SBA or SAB VM An or Bn VM tsu(H) tPHL VM VM Propagation Delay for An to Bn or Bn to An and SAB or SBA to An or Bn CPBA or CPAB An or Bn VM VM tsu(L) th(H) VM SF00397 Waveform 3. Propagation Delay for An to Bn or Bn to An and SAB or SBA to An or Bn Waveform 4. Data Setup Time and Hold Times OE OE VM VM VM DIR VM DIR tPZH tPHZ VOH -0.3V tPZL VM An or Bn 0V tPLZ 3.5V VM VOL +0.3V SF00398 SF00399 Waveform 5. 3-State Output Enable Time to High Level and Output Disable Time from High Level 1991 Feb 08 th(L) VM SF00396 An or Bn VM Waveform 6. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level 9 Philips Semiconductors Product specification 74ALS646/74ALS646-1 74ALS648/74ALS648-1 Transceiver/register TEST CIRCUIT AND WAVEFORMS VCC 7.0V VIN VOUT PULSE GENERATOR tw 90% NEGATIVE PULSE 10% RL CL RL AMP (V) VM VM D.U.T. RT 90% 10% tTHL (tff) tTLH (tr ) tTLH (tr ) tTHL (tf ) 0.3V AMP (V) 90% Test Circuit for 3-State and Open Collector Outputs POSITIVE PULSE closed All other open VM VM 10% SWITCH POSITION TEST SWITCH closed tPLZ, tPZL open collector 90% 10% tw 0.3V Input Pulse Definition INPUT PULSE REQUIREMENTS Family Amplitude VM DEFINITIONS: RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RT = Termination resistance should be equal to ZOUT of pulse generators. 74ALS 3.5V 1.3V Rep.Rate tw tTLH tTHL 1MHz 500ns 2.0ns 2.0ns SC00126 1991 Feb 08 10 Philips Semiconductors Product specification 74ALS646/74ALS646–1 74ALS648/74ALS648–1 Transceiver/register DIP24: plastic dual in-line package; 24 leads (300 mil) 1991 Feb 08 11 SOT222-1 Philips Semiconductors Product specification 74ALS646/74ALS646–1 74ALS648/74ALS648–1 Transceiver/register SO24: plastic small outline package; 24 leads; body width 7.5 mm 1991 Feb 08 12 SOT137-1 Philips Semiconductors Product specification 74ALS646/74ALS646–1 74ALS648/74ALS648–1 Transceiver/register DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Formative or in Design This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. Preliminary Specification Preproduction Product This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product Specification Full Production This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Copyright Philips Electronics North America Corporation 1997 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 1991 Feb 08 13