PHILIPS 74ABT651D

Philips Semiconductors
Product specification
Octal transceiver/register, inverting (3-State)
FEATURES
74ABT651
DESCRIPTION
• Independent registers for A and B buses
• The 74ABT651 is the inverting version of the 74ABT652
• Multiplexed real-time and stored data
• 3-State outputs
• Live insertion/extraction permitted.
• Power-up 3-State
• Power-up reset
• Output capability: +64mA/–32mA
• Latch-up protection exceeds 500mA per Jedec Std 17
• ESD protection exceeds 2000 V per MIL STD 883 Method 3015
The 74ABT651 high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
The 74ABT651 transceiver/register consists of bus transceiver
circuits with 3-State outputs, D-type flip-flops, and control circuitry
arranged for multiplexed transmission of data directly from the input
bus or the internal registers. Data on the A or B bus will be clocked
into the registers as the appropriate clock pin goes High. Output
Enable (OEAB, OEBA) and Select (SAB, SBA) pins are provided for
bus management.
The following examples demonstrate the four fundamental
bus-management functions that can be performed with the
74ABT651.
The select pins determine whether data is stored or transferred
through the device in real time.
and 200 V per Machine Model
The output enable pins determine the direction of the data flow.
QUICK REFERENCE DATA
SYMBOL
CONDITIONS
Tamb = 25°C; GND = 0V
PARAMETER
tPLH
tPHL
Propagation delay
CPBA to An or CPAB to Bn
CL = 50pF; VCC = 5V
CIN
Input capacitance
VI = 0V or VCC
CI/O
I/O capacitance
Outputs disabled; VO = 0V or VCC
ICCZ
Total supply current
Outputs disabled; VCC =5.5V
TYPICAL
UNIT
3.8
4.4
ns
4
pF
7
pF
110
µA
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
24-Pin Plastic DIP
–40°C to +85°C
74ABT651 N
74ABT651 N
SOT222-1
24-Pin plastic SO
–40°C to +85°C
74ABT651 D
74ABT651 D
SOT137-1
24-Pin Plastic SSOP Type II
–40°C to +85°C
74ABT651 DB
74ABT651 DB
SOT340-1
24-Pin Plastic TSSOP Type I
–40°C to +85°C
74ABT651 PW
74ABT651PW DH
SOT355-1
PIN CONFIGURATION
PIN DESCRIPTION
CPAB
1
24
VCC
SAB
2
23
CPBA
OEAB
3
22
SBA
A0
4
21
OEBA
A1
5
20
B0
A2
6
19
B1
A3
7
18
B2
A4
8
17
B3
A5
9
16
B4
A6
10
15
B5
A7
11
14
B6
GND
12
13
B7
PIN
NUMBER
SYMBOL
1, 23
CPAB /
CPBA
2, 22
SAB /
SBA
3, 21
OEAB /
OEBA
A to B Output Enable input /
B to A Output Enable input
(active–Low)
4, 5, 6, 7, 8,
9, 10, 11
A0 – A7
Data inputs/outputs (A side)
20, 19, 18,
17, 16, 15,
14, 13
B0 – B7
Data inputs/outputs (B side)
12
GND
Ground (0V)
24
VCC
Positive supply voltage
FUNCTION
A to B clock input / B to A clock input
A to B select input / B to A select input
SA00094
1995 Sep 06
1
853-1783 15703
Philips Semiconductors
Product specification
Octal transceiver/register, inverting (3-State)
LOGIC SYMBOL (IEEE/IEC)
21
EN1 [BA]
3
EN2 [AB]
74ABT651
LOGIC SYMBOL
C4
23
G5
22
4
5
6
7
8
9
10
11
A0
A1
A2
A3
A4
A5
A6
A7
C6
1
G7
2
5
1
4
1
20
CPBA
22
SBA
OEAB
3
2
SAB
OEBA
21
1
CPAB
5 1
6D 7
1
4D
23
7
1
B0
B1
B2
B3
B4
B5
B6
B7
20
19
18
17
16
15
14
13
2
5
19
6
18
7
17
8
16
SA00095
9
15
10
14
11
13
SA00125
REAL TIME BUS TRANSFER
BUS B TO BUS A
A
REAL TIME BUS TRANSFER
BUS A TO BUS B
B
A
B
X
X
L
OEABOEBA CPAB CPBA SAB SBA
H
H
X
X
A
B
L
}
X
B
}
L
TRANSFER STORED DATA
TO A OR B
A
}
}
OEABOEBA CPAB CPBA SAB SBA
L
STORAGE FROM
A, B, OR A AND B
OEABOEBA CPAB CPBA SAB SBA
X
X
H
↑
X
X
X
L
X
X
↑
X
X
L
H
↑
↑
X
X
OEABOEBA CPAB CPBA SAB SBA
H
L
H|L H|L
H
H
SA00097
1995 Sep 06
2
Philips Semiconductors
Product specification
Octal transceiver/register, inverting (3-State)
74ABT651
FUNCTION TABLE
INPUTS
H
L
X
↑
*
**
DATA I/O
OPERATING MODE
OEAB
OEBA
CPAB
CPBA
SAB
SBA
An
Bn
L
L
H
H
H or L
↑
H or L
↑
X
X
X
X
Input
Input
Isolation
Store A and B data
X
H
H
H
↑
↑
H or L
↑
X
**
X
X
Input
Unspecified
output*
Store A, Hold B
Store A in both registers
L
L
X
L
H or L
↑
↑
↑
X
X
X
**
Unspecified
output*
Input
Hold A, Store B
Store B in both registers
L
L
L
L
X
X
X
H or L
X
X
L
H
Output
Input
Real time B data to A bus
Stored B data to A bus
H
H
H
H
X
H or L
X
X
L
H
X
X
Input
Output
Real time A data to B bus
Store A data to B bus
H
L
H or L
H or L
H
H
Output
Output
Stored A data to B bus
Stored B data to A bus
=
=
=
=
High voltage level
Low voltage level
Don’t care
Low-to-High clock transition
The data output function may be enabled or disabled by various signals at the OEBA and OEAB inputs. Data input functions are always
enabled, i.e., data at the bus pins will be stored on every Low-to-High transition of the clock.
If both Select controls (SAB and SBA) are Low, then clocks can occur simultaneously. If either Select control is High, the clocks must be
staggered in order to load both registers.
LOGIC DIAGRAM
21
OEBA
3
OEAB
23
CPBA
22
SBA
1
CPAB
2
SAB
1of 8 Channels
1D
C1
Q
A0
4
20
B0
1D
C1
Q
A1
A2
A3
A4
A5
A6
A7
5
19
6
18
7
17
8
DETAIL A X 7
16
9
15
10
14
11
13
B1
B2
B3
B4
B5
B6
B7
SA00098
1995 Sep 06
3
Philips Semiconductors
Product specification
Octal transceiver/register, inverting (3-State)
74ABT651
ABSOLUTE MAXIMUM RATINGS1, 2
SYMBOL
VCC
IIK
PARAMETER
CONDITIONS
RATING
UNIT
–0.5 to +7.0
V
–18
mA
–1.2 to +7.0
V
VO < 0
–50
mA
output in Off or High state
–0.5 to +5.5
V
output in Low state
128
mA
–65 to 150
°C
DC supply voltage
DC input diode current
VI < 0
voltage3
VI
DC input
IOK
DC output diode current
voltage3
VOUT
DC output
IOUT
DC output current
Tstg
Storage temperature range
NOTES:
1. 1Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
VCC
PARAMETER
UNIT
DC supply voltage
Min
Max
4.5
5.5
V
0
VCC
V
VI
Input voltage
VIH
High-level input voltage
VIL
Low-level Input voltage
0.8
V
IOH
High-level output current
–32
mA
IOL
Low-level output current
64
mA
0
10
ns/V
–40
+85
°C
∆t/∆v
Input transition rise or fall rate
Tamb
Operating free-air temperature range
1995 Sep 06
2.0
4
V
Philips Semiconductors
Product specification
Octal transceiver/register, inverting (3-State)
74ABT651
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Min
VIK
Input clamp voltage
Tamb = –40°C
to +85°C
Tamb = +25°C
VCC = 4.5V; IIK = –18mA
Typ
Max
–0.9
–1.2
Min
UNIT
Max
–1.2
V
VCC = 4.5V; IOH = –3mA; VI = VIL or VIH
2.5
3.2
2.5
V
VCC = 5.0V; IOH = –3mA; VI = VIL or VIH
3.0
3.7
3.0
V
VCC = 4.5V; IOH = –32mA; VI = VIL or VIH
2.0
2.30
VOH
High–level output voltage
VOL
Low–level output voltage
VCC = 4.5V; IOL = 64mA; VI = VIL or VIH
0.42
0.55
0.55
Power-up output low voltage
VCC = 5.5V; IO = 1mA; VI = GND or VCC
0.13
0.55
0.55
V
Control pins
VCC = 5.5V; VI = GND or 5.5V
±0.01
±1.0
±1.0
µA
Data pins
VCC = 5.5V; VI = GND or 5.5V
±5
±100
±100
µA
Power-off leakage current
VCC = 0.0V; VO or VI ≤ 4.5V
±5.0
±100
±100
µA
Power-up/down 3-State
output current4
VCC = 2.1V; VO = 0.5V; V OE = Don’t Care;
VI = GND or VCC
±5.0
±50
±50
µA
IIH + IOZH
3–State output High current
VCC = 5.5V; VO = 2.7V; VI = VIL or VIH
5.0
50
50
µA
IIL + IOZL
3–State output Low current
VCC = 5.5V; VO = 0.5V; VI = VIL or VIH
–5.0
–50
–50
µA
ICEX
Output High leakage current
VCC = 5.5V; VO = 5.5V; VI = GND or VCC
5.0
50
50
µA
Output current1
VCC = 5.5V; VO = 2.5V
–65
–180
–180
mA
VRST3
II
IOFF
IPU/IPD
IO
Input leakage
current
–40
2.0
–40
V
V
ICCH
VCC = 5.5V; Outputs High, VI = GND or VCC
110
250
250
µA
ICCL
VCC = 5.5V; Outputs Low, VI = GND or VCC
20
30
30
mA
Q i
Quiescent
supply
l current
VCC = 5.5V; Outputs 3–State;
VI = GND or VCC
110
250
250
µA
Additional supply current per
input pin2
VCC = 5.5V; one input at 3.4V,
other inputs at VCC or GND; VCC = 5.5V
0.3
1.5
1.5
mA
ICCZ
∆ICC
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
4. This parameter is valid for any VCC between 0V and 2.1V, with a transition time of up to 10msec. From VCC = 2.1V to VCC = 5V ± 10%, a
transition time of up to 100µsec is permitted.
AC CHARACTERISTICS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω
LIMITS
SYMBOL
PARAMETER
Tamb = -40 to
+85oC
VCC = +5.0V ±0.5V
Tamb = +25oC
VCC = +5.0V
WAVEFORM
Min
Typ
1
125
300
Propagation delay
CPAB to Bn or CPBA to An
1
2.2
1.7
3.8
4.4
5.1
5.1
2.2
1.7
5.6
5.6
ns
tPLH
tPHL
Propagation delay
An to Bn or Bn to An
2
1.5
1.5
3.2
3.7
5.1
4.6
1.5
1.5
6.2
5.4
ns
tPLH
tPHL
Propagation delay
SAB to Bn or SBA to An
3
1.5
1.5
3.8
4.4
5.1
4.9
1.5
1.5
6.5
5.9
ns
tPZH
tPZL
Output enable time
OEBA to An
5
6
1.3
2.5
3.7
4.7
4.6
6.8
1.3
2.5
5.8
8.5
ns
tPHZ
tPLZ
Output disable time
OEBA to An
5
6
1.5
1.5
4.0
3.2
4.5
3.8
1.5
1.5
5.0
4.1
ns
tPZH
tPZL
Output enable time
OEAB to Bn
5
6
1.8
2.9
3.4
4.5
6.1
6.5
1.8
2.9
6.5
7.4
ns
tPHZ
tPLZ
Output disable time
OEAB to Bn
5
6
1.5
1.5
3.8
3.1
4.5
4.4
1.5
1.5
5.5
5.1
ns
fMAX
Maximum clock frequency
tPLH
tPHL
1995 Sep 06
5
Max
Min
UNIT
Max
125
MHz
Philips Semiconductors
Product specification
Octal transceiver/register, inverting (3-State)
74ABT651
AC SETUP REQUIREMENTS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω
LIMITS
SYMBOL
PARAMETER
+25oC
Tamb = -40 to +85oC
VCC = +5.0V ±0.5V
Tamb =
VCC = +5.0V
WAVEFORM
UNIT
Min
Typ
Min
4
3.0
3.0
1.2
0.8
3.0
3.0
ns
Hold time
An to CPAB, Bn to CPBA
4
0.0
0.0
–0.8
–0.9
0.0
0.0
ns
Pulse width, High or Low
CPAB or CPBA
1
4.0
4.0
1.2
1.1
4.0
4.0
ns
ts(H)
ts(L)
Setup time
An to CPAB, Bn to CPBA
th(H)
th(L)
tw(H)
tw(L)
AC WAVEFORMS
VM = 1.5V, VIN = GND to 3.0V
1/fMAX
An or Bn
CPBA or
CPAB
VM
VM
VM
ÉÉÉ ÉÉÉÉÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉÉÉÉÉ
ÉÉÉ
ÉÉÉ ÉÉÉÉÉÉÉ
ÉÉÉ
VM
VM
ts(H)
tw(H)
tw(L)
An or Bn
VM
VM
ts(L)
th(H)
th(L)
tW(L)
CPBA or
CPAB
tPLH
tPHL
VM
VM
VM
VM
NOTE: The shaded areas indicate when the input is permitted
to change for predictable output performance.
SA00087
SA00090
Waveform 1. Propagation Delay, Clock Input to Output, Clock
Pulse Width, and Maximum Clock Frequency
Waveform 4. Data Setup and Hold Times
OEBA
An or Bn
VM
VM
VM
VM
OEAB
tPZH
tPLH
tPHZ
tPHL
An or Bn
0V
VM
VM
Bn or An
VOH –0.3V
VM
SA00100
SA00016
Waveform 5. 3–State Output Enable Time to High Level and
Output Disable Time from High Level
Waveform 2. Propagation Delay, An to Bn or Bn to An
OEBA
SBA or SAB
VM
VM
VM
VM
OEAB
tPHL
An or Bn
tPZL
tPLH
VM
VM
An or Bn
tPLZ
VM
VOL +0.3V
0V
SA00089
SA00101
Waveform 3. Propagation Delay, SBA to An or SAB to Bn
1995 Sep 06
Waveform 6. 3–State Output Enable Time to Low Level and
Output Disable Time from Low Level
6
Philips Semiconductors
Product specification
Octal transceiver/register, inverting (3-State)
74ABT651
TEST CIRCUIT AND WAVEFORM
VCC
7.0V
PULSE
GENERATOR
VIN
tW
90%
VOUT
VM
NEGATIVE
PULSE
CL
10%
0V
RL
tTHL (tF)
tTLH (tR)
tTLH (tR)
tTHL (tF)
90%
POSITIVE
PULSE
Test Circuit for 3-State Outputs
AMP (V)
90%
VM
VM
10%
10%
tW
SWITCH POSITION
TEST
SWITCH
tPLZ
closed
tPZL
closed
All other
open
AMP (V)
VM
10%
RL
D.U.T.
RT
90%
0V
VM = 1.5V
Input Pulse Definition
INPUT PULSE REQUIREMENTS
DEFINITIONS
FAMILY
RL = Load resistor; see AC CHARACTERISTICS for value.
CL = Load capacitance includes jig and probe capacitance;
see AC CHARACTERISTICS for value.
RT = Termination resistance should be equal to ZOUT of
pulse generators.
74ABT
Amplitude
Rep. Rate
tW
tR
tF
3.0V
1MHz
500ns
2.5ns
2.5ns
SA00012
1995 Sep 06
7