P5Cx012/02x/40/73/80/144 family Secure dual interface and contact PKI smart card controller Rev. 03 — 24 January 2008 Objective short data sheet 1. General description 1.1 SmartMX family approach The new CMOS14 SmartMX family members feature a modular set of devices with: • • • • • • • • • • • • • • 12 KB to 144 KB EEPROM 200 KB user ROM 6144 B RAM High-performance secured Public Key Infrastructure (PKI) coprocessor (RSA, ECC) Secured dual/triple-DES coprocessor Secured AES coprocessor Memory Management Unit (MMU) ISO/IEC 7816 contact interface Optional ISO/IEC 14443 A Contactless Interface Unit (CIU) Optional S2C interface for NFC communication link 5-metal-layer 0.14 µm CMOS technology EEPROM with typical 500000 cycles endurance and minimum 20 years retention time Broad spectrum of delivery types Optional certified crypto library modules for RSA, ECC, DES, AES, SHA and PRNG 1.2 SmartMX family properties The long-term approved SmartMX family features a significantly enhanced secure smart card IC architecture. Extended instructions for Java and C code, linear addressing, high speed at low power and a universal memory management unit are among many other improvements added to the classic 80C51 core architecture. The technology transfer step from 5-metal-layer 0.18 µm to 5-metal-layer 0.14 µm CMOS technology offers now even more advantages in terms of security features, memory resources, crypto coprocessor calculation speed for RSA and ECC as well as availability of secure hardware support for 2/3-key Digital Encryption Standard (DES) and Advanced Encryption Standard (AES) operations. The availability of contact interface, optional contactless or S2C interface enables the easy implementation of native or open platform and multi-application operating systems in market segments like e.g. banking, E-passport, ID card, Health Card, secure access, Java card, Near Field Communication (NFC) connectable mobile hand sets as well as Trusted Platform Modules (TPM). NXP Semiconductors P5Cx012/02x/40/73/80/144 family Secure dual interface and contact PKI smart card controller 1.3 Naming conventions Table 1. Naming conventions P5xyzzz SmartMX platform x Type of category: y Interface options: C = PKI controller + Triple-DES coprocessor + AES coprocessor on selected products C = contact interface - ISO/IEC 7816 D = dual interface - ISO/IEC 7816 + ISO/IEC 14443 contactless interface N = ISO/IEC 7816 + S2C Interface for NFC zzz Amount of non-volatile memory in KB, increasing count for further product options 1.4 Cryptographic hardware coprocessors 1.4.1 FameXE coprocessor The approved and modular FameXE architecture supports the trend of increasing RSA keys with faster execution speeds as well as Elliptic Curve Cryptography (ECC) based on GF(p) or GF(2n) at best performance. FameXE supports RSA with an operand length of up to 8-kbit (up to 4-kbit with intermediate storage in RAM only). The FameXE PKI coprocessor supports 192-bit ECC key length that offers the same level of security as 2048-bit RSA. An ECC GF(2n) based signature, using a 163-bit key can be executed in less than 30 ms providing a security level comparable to 1024-bit RSA. The operand size for ECC, supported by FameXE, is only limited by the 2.5 KB size of the FXRAM. FameXE is easy to use and the flexible interface provides programmers with the freedom to implement their own cryptology solutions. A secured and CC EAL5+ certified crypto library providing a large range of required functions will be available for all devices in order to support customers in implementing public key-based solutions. 1.4.2 Triple-DES coprocessor The DES for widely used symmetric encryption is supported by a dedicated, high performance, highly attack resistant hardware coprocessor. Single DES and triple-DES, based on two or three DES keys, can be executed within less than 40 µs. Relevant standards (ISO/IEC, ANSI, FIPS) and Message Authentication Code (MAC) are fully supported. A secured crypto library element for DES is available. 1.4.3 AES coprocessor SmartMX is the first smart card microcontroller platform to provide a dedicated high performance 128-bit parallel processing coprocessor to support secure AES. The implementation is based on FIPS197 as standardized by the National Institute for Standards and Technology (NIST), and supports key lengths of 128-bit, 192-bit, and 256-bit with performance levels comparable to DES. AES is the next generation for symmetric data encryption and recommended successor of DES providing significantly improved security level. A secured crypto library element for AES is available. P5CX012_02X_40_73_80_144_FAM_SDS_3 Objective short data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 24 January 2008 2 of 18 NXP Semiconductors P5Cx012/02x/40/73/80/144 family Secure dual interface and contact PKI smart card controller 1.5 SmartMX interfaces 1.5.1 SmartMX contact interface Operating in accordance with ISO/IEC 7816, the SmartMX contact interface is supported by a built-in Universal Asynchronous Receiver/Transmitter (UART), which enables data rates of up to 1 Mbit/s allowing for the automatic generation of all typical baud rates and supports transmission protocols T = 0 and T = 1. Either one or two additional IOs are available. 1.5.2 SmartMX contactless interface The optional contactless interface is fully compatible with ISO/IEC 14443 A as well as NXP Semiconductors field proven MIFARE technology. A dedicated Contactless Interface Unit (CIU) manages and supports communication using data rates of up to 848 kbit/s. A true anti-collision method (according to ISO/IEC 14443-3) enables multiple cards to be handled simultaneously. The optional MIFARE functionality provided in configurations B1 (MIFARE 1 KB emulation) and B4 (MIFARE 4 KB emulation) safeguard the interface compatibility with any installed MIFARE infrastructure. The ability to run the MIFARE protocol concurrently with other contactless transmission protocols implemented by the user OS (T = CL or self defined) enables the combination of new services and existing applications based on MIFARE (e.g. ticketing) on a single dual interface controller based smart card. A tutorial software library for ISO/IEC 14443-3 and ISO/IEC 14443-4 is available to support NXP Semiconductors customers for easy integration of the contactless technology into current system solutions. 1.5.3 SmartMX S2C interface The S2C interface is intended for use with NXP Semiconductors NFC circuits (e.g. PN511, PN531) in order to configure a secure NFC system, e.g. in mobile hand sets. Operated both in Contact mode (ISO/IEC 7816) and in S2C mode the user defines the final function of the controller chip with its operating system. This allows the same level of security, functionality and flexibility for the contact interface as well as for S2C interface. The S2C interface is connected to the internal ISO 14443 CIU. The CIU handles the demodulation and the modulation of the S2C signals in a way that a full contactless communication via this interface and the NFC IC can be enabled. As the S2C interface is connected to the CIU the power of the P5CN080/P5CN144 has to be supplied via the VDD and VSS pads to use the S2C interface. The S2C interface does not need any software adaptation compared to the normal contactless operation. Connected to the S2C interface of a NFC IC the device is compatible with existing MIFARE reader infrastructure and the optional emulation modes of MIFARE 1 KB or MIFARE 4 KB enable fast system integration and backward compatibility to MIFARE based cards. The communication on the S2C interface supports both the ISO/IEC 14443 A part 3 and the ISO/IEC 14443 part 4. P5CX012_02X_40_73_80_144_FAM_SDS_3 Objective short data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 24 January 2008 3 of 18 NXP Semiconductors P5Cx012/02x/40/73/80/144 family Secure dual interface and contact PKI smart card controller 1.6 Security features SmartMX incorporates a big range of both inherent and OS controlled security features as counter measure against all types of attacks. NXP Semiconductors has used the deep knowledge of chip security, combined with the used handshaking circuit technology, the very dense 5-metal-layer 0.14 µm technology, glue logic and active shielding methodology for optimum results in CC EAL5+, EMVCo and other third party certifications and approvals. SmartMX Memory Management Unit (MMU), designed to define various memory segments and assign security attributes accordingly, supports a strong firewall concept that keeps different applications separate from each other. Only the System mode has full access privileges to all memory space and on-chip peripherals, while the User mode only has privileges defined upon card personalization and executed under the control of the System mode. 1.7 Security evaluation and certificates The reached target of the certification is CC EAL5+. Also third party approvals like e.g. EMVCo (Visa, CAST), ZKA and others, depending on the application requirements, are available. NXP Semiconductors continues to drive forward third party security evaluations to provide its customers with the relevant information and documentation needed to execute subsequent composite evaluations of implemented applications. 1.8 Optional crypto library NXP Semiconductors will offer for all family types an optional crypto library: • Various algorithms – AES encryption and decryption using the AES coprocessor – DES and Triple-DES encryption and decryption using the DES coprocessor – RSA encryption and decryption, signature generation and verification for straightforward and CRT keys up to 5024 bits – RSA key generation – ECC over GF(p) signature generation and verification (ECDSA) and Diffie-Hellman key exchange for keys up to 544 bits – ECC over GF(p) key generation – ECC over GF(2n) signature generation and verification (ECDSA) and Diffie-Hellman key exchange for keys up to 571 bits – ECC over GF(2n) key generation – SHA-1, SHA-224 and SHA-256 hash algorithm – Pseudo-Random Number Generator (PRNG) • Easy to use API for all algorithms • Secure operation in contact as well as in the contactless mode • Latest built-in security features to avoid power (SPA/DPA), timing and fault attacks (DFA) P5CX012_02X_40_73_80_144_FAM_SDS_3 Objective short data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 24 January 2008 4 of 18 NXP Semiconductors P5Cx012/02x/40/73/80/144 family Secure dual interface and contact PKI smart card controller • Common criteria CC EAL5+ certification planned [except ECC over GF(2n)] according to BSI-PP-0002 protection profile 2. Features 2.1 Standard family features n EEPROM: choice of 12 KB, 20 KB, 40 KB, 72 KB, 80 KB or 144 KB u Data retention time: 20 years minimum u Endurance: 500000 cycles typical n ROM: 200 KB n RAM: 6144 B u 256 B IRAM + 3.25 KB standard RAM usable for CPU u 2560 B FXRAM usable for FameXE n Dedicated Secure_MX51 Smart Card CPU (Memory eXtended/enhanced 80C51) u 5-metal-layer 0.14 µm CMOS technology u Operating in Contact and Contactless mode (dependent on family type option) u Featuring a 24-bit universal memory space, 24-bit program counter u Combined universal program and data linear address range up to 16 MB u Additional instructions to improve: - Pointer operations - Performance - Code density of both C and Java source code n ISO/IEC 7816 contact interface n PKI coprocessor FameXE n Support of major Public Key Cryptography (PKC) systems like RSA, Elgamel, DSS, Diffie-Hellman, Guillou-Quisquater, Fiat-Shamir and Elliptic Curves u 8192 bits maximum key length for RSA with randomly chosen modulus u 4096 bits maximum key length for calculation within RAM u 32-bit interface u Boolean operations for acceleration of standard, symmetric cipher algorithms n High speed Triple-DES coprocessor (64-bit parallel processing DES engine) u Two or three keys loadable u DES3 performance < 40 µs n High speed AES coprocessor (128-bit parallel processing AES engine) n Memory Management Unit (MMU) n Low power and low voltage design using NXP Semiconductors handshaking technology n Multiple source vectorized interrupt system with four priority levels n Watch exception provides software debugging facility n Multiple source RESET system n Two 16-bit timers n High reliable EEPROM for both data storage and program execution n Bytewise EEPROM programming and read access P5CX012_02X_40_73_80_144_FAM_SDS_3 Objective short data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 24 January 2008 5 of 18 NXP Semiconductors P5Cx012/02x/40/73/80/144 family Secure dual interface and contact PKI smart card controller n Versatile EEPROM programming of 1 B to 64 B at a time or, optionally 1 B to 128 B at a time n Typical EEPROM page erasing time: 1.7 ms n Typical EEPROM page programming time: 1.0 ms u Power-saving Idle mode u Wake-up from Idle mode by RESET or any activated interrupt u Power-saving Sleep (power-down) mode or Clockstop mode u Wake-up from Sleep or Clockstop mode by RESET or external interrupt n Contact configuration and serial interface according to ISO/IEC 7816: GND, VDD, CLK, RST_N, IO1 n ISO/IEC 7816 UART supporting standard protocols T = 0 and T = 1 as well as high speed personalization up to 1 Mbit/s n External or internally generated configurable CPU clock n 1 MHz to 10 MHz operating external clock frequency range u Internal CPU clock up to 30 MHz with synchronous operation u Internal clocking independent of externally applied frequency n High speed 16-bit CRC engine according to ITU-T polynomial definition n Low power Random Number Generator (RNG) in hardware, AIS-31 compliant n 1.62 V to 5.5 V extended operating voltage range for class C, B and A n Optional extended Class B operation mode (targeted for battery supplied applications) n −25 °C to +85 °C ambient temperature n Broad spectrum of delivery types: u Wafers u Modules 2.2 Product specific family features n P5CC021, P5CC040, P5CC073, P5CC080 and P5CC144 u ISO/IEC 7816 contact interface u Two additional IO ports IO2 and IO3 for full-duplex serial data communication n P5CD012, P5CD020, P5CD040, P5CD080 and P5CD144 u CIU fully compatible with ISO/IEC 14443 A: - Fully supports the T = CL protocol according ISO/IEC 14443-4 - Data transfer rates supported: 106 kbit/s, 212 kbit/s, 424 kbit/s and 848 kbit/s u MIFARE contactless interface according ISO/IEC 14443-2: - 13.56 MHz operating frequency - Reliable communication due to 100 % ASK - High speed efficient frame support - True anticollision u MIFARE reader infrastructure compatibility u Optional MIFARE 1 KB and MIFARE 4 KB emulation u Two additional IO ports IO2 and IO3 for full-duplex serial data communication n P5CN080 and P5CN144 u S2C interface u One additional IO port IO2 for full-duplex serial data communication P5CX012_02X_40_73_80_144_FAM_SDS_3 Objective short data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 24 January 2008 6 of 18 NXP Semiconductors P5Cx012/02x/40/73/80/144 family Secure dual interface and contact PKI smart card controller 2.3 Security features n Enhanced security sensors: u Low and high clock frequency sensor u Low and high temperature sensor u Low and high supply voltage sensor u Single Fault Injection (SFI) attack detection u Light sensors (included integrated memory light sensor functionality) n Electronic fuses for safeguarded mode control n Active shielding n Unique ID for each die n Clock input filter for protection against spikes n Power-up and power-down reset n Optional programmable card disable feature n Memory security (encryption and physical measures) for RAM, EEPROM and ROM n Memory Management Unit (MMU) including memory protection: u Secure multi application operating systems via two different operation modes: System mode and User mode u OS controlled access restriction mechanism to peripherals in User mode u Memory mapping up to 8-MB code memory u Memory mapping up to 8-MB (64-kbit) data memory n Optional disabling of ROM read instructions by code executed in EEPROM n Optional disabling of any code execution out of RAM n EEPROM programming: u No external clock u Hardware sequencer controlled u On-chip high voltage generation u Enhanced error correction mechanism n 64-B or 128-B EEPROM for customer-defined Security FabKey. Featuring batch, wafer or die-individual security data, included encrypted diversification features on request n 14 B user write protected security area in EEPROM (byte access, inhibit functionality per byte) n 32 B write once security area in EEPROM (bit access) n 32 B user read only area in EEPROM (byte access) n Customer specific EEPROM initialization available P5CX012_02X_40_73_80_144_FAM_SDS_3 Objective short data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 24 January 2008 7 of 18 NXP Semiconductors P5Cx012/02x/40/73/80/144 family Secure dual interface and contact PKI smart card controller 2.4 Design-in support n Approved development tool chain: u Keil PK51 development tool package inclusive µVision3/dScope C51 simulator, additional specific hardware drivers inclusive simulation of contactless interface and ISO/IEC 7816 card interface board. A SmartMX DBox allows software debugging and integration tests. u Ashling Ultra-Emulator platform, stand alone ROM prototyping boards and ISO/IEC 7816 and ISO/IEC 14443 card interface board. Code coverage and performance measurement software tools for real time software testing. u Dual interface dummy modules OM6711 (PDM 1.1 - SOT658) with special antenna bonding on C4 and C8 for testing the implanting process and antenna connection. n Software libraries: u Libraries supporting contactless communication according to ISO 14443, part 3 and 4 u EEPROM read/write routines 3. Applications 3.1 Application areas n n n n n n Banking Java cards E-passports ID cards Secure access Trusted platform modules P5CX012_02X_40_73_80_144_FAM_SDS_3 Objective short data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 24 January 2008 8 of 18 P5Cx012/02x/40/73/80/144 family NXP Semiconductors Secure dual interface and contact PKI smart card controller 4. Quick reference data Table 2. Quick reference data Symbol Parameter supply voltage VDD Conditions Min Typ Max Unit Class A: 5 V range 4.5 5.0 5.5 V 2.7 3.0 3.3 V 2.2 3.0 3.3 V 1.62 1.8 1.98 V Class B: 3 V range Class BE: 3 V range Class C: 1.8 V range [1] [1] In case of extended Class B (Class BE) operation mode (targeted for battery supplied applications), the class C is not supported. 5. Ordering information Table 3. Ordering information Type number P5CC021UA Package Name Description Version FFC 8 inch wafer (sawn; 150 µm thickness; on film frame carrier; electronic fail die marking according to SECSII format) <tbd> FFC 8 inch wafer (sawn; 75 µm thickness; on film frame <tbd> carrier; electronic fail die marking according to SECSII format) PCM1.1 contact chip card module (super 35 mm format, 8-contact) SOT658 PDM1.1 contactless chip card module (Plug-in type; super 35 mm format, 8-contact) SOT658 P5CC040UA P5CC073UA P5CC080UA P5CC144UA P5CD012UA P5CD020UA P5CD040UA P5CD080UA P5CD144UA P5CN080UA P5CN144UA P5CD012UE P5CD020UE P5CD040UE P5CD080UE P5CD144UE P5CC021XS P5CC040XS P5CC073XS P5CC080XS P5CC144XS P5CD012X1 P5CD020X1 P5CD040X1 P5CD080X1 P5CD144X1 P5CX012_02X_40_73_80_144_FAM_SDS_3 Objective short data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 24 January 2008 9 of 18 P5Cx012/02x/40/73/80/144 family NXP Semiconductors Secure dual interface and contact PKI smart card controller Table 3. Ordering information …continued Type number P5CD012X0 Package Name Description PDM1.1 contactless chip card module (super 35 mm format, SOT658 8-contact) MOB4 plastic leadless module carrier package; 35 mm wide tape SOT500-2 MOB6 plastic leadless module carrier package; 35 mm wide tape SOT500-3 P5CD020X0 Version P5CD040X0 P5CD080X0 P5CD144X0 P5CD012A4 P5CD020A4 P5CD040A4 P5CD080A4 P5CD144A4 P5CD012A6 P5CD020A6 P5CD040A6 P5CD080A6 P5CD144A6 Table 4. Feature table Product type EEPROM [KB] User ROM [KB] Total RAM [KB] CXRAM [KB] P5CD012 12 200 6 3.5 2.5 yes yes yes 3 dual interface P5CC021 20 200 6 3.5 2.5 yes yes yes 3 contact P5CD020 20 200 6 3.5 2.5 yes yes yes 3 dual interface P5CC040 40 200 6 3.5 2.5 yes yes yes 3 contact P5CD040 40 200 6 3.5 2.5 yes yes yes 3 dual interface P5CC073 72 200 6 3.5 2.5 yes yes yes 3 contact P5CN080 80 200 6 3.5 2.5 yes yes yes 3 contact + S2C interface for NFC P5CC080 80 200 6 3.5 2.5 yes yes yes 3 contact P5CD080 80 200 6 3.5 2.5 yes yes yes 3 dual interface P5CN144 144 200 6 3.5 2.5 yes yes yes 2 contact + S2C interface for NFC P5CC144 144 200 6 3.5 2.5 yes yes yes 3 contact P5CD144 144 200 6 3.5 2.5 yes yes yes 3 dual interface FXRAM Coprocessor [KB] FameXE DES P5CX012_02X_40_73_80_144_FAM_SDS_3 Objective short data sheet AES ISO 7816 Interface option IO pads © NXP B.V. 2008. All rights reserved. Rev. 03 — 24 January 2008 10 of 18 xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x IO2 PROGRAMMABLE IO 1, 2, 3 EEPROM RAM 200 KB PROGRAM MEMORY 20 KB/40 KB/ 72 KB/80 KB/ 144 KB DATA AND PROGRAM MEMORY 6144 B DATA MEMORY UART ISO 7816 IO3 FameXE ENHANCED PUBLIC KEY COPROCESSOR e.g. RSA, ECC NXP Semiconductors IO1 ROM 6. Functional diagram P5CX012_02X_40_73_80_144_FAM_SDS_3 Objective short data sheet P5CC021 P5CC040 P5CC073 P5CC080 P5CC144 RST_N CLOCK FILTER CLOCK GENERATION SECURE_MX51 CPU TRIPLE-DES COPROCESSOR TIMERS SECURITY SENSORS RESET GENERATION CRC16 16-bit 16-bit T0 T1 AES COPROCESSOR FAST RNG VOLTAGE REGULATOR 11 of 18 © NXP B.V. 2008. All rights reserved. VDD VSS Fig 1. Functional diagram P5CC021/P5CC040/P5CC073/P5CC080/P5CC144 001aae954 Secure dual interface and contact PKI smart card controller Rev. 03 — 24 January 2008 CLK P5Cx012/02x/40/73/80/144 family MEMORY MANAGEMENT UNIT (MMU) xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors P5CX012_02X_40_73_80_144_FAM_SDS_3 Objective short data sheet P5CD020 P5CD040 P5CD080 P5CD144 LA RF INTERFACE CIU ISO 14443 ROM EEPROM RAM 200 KB PROGRAM MEMORY 20 KB/40 KB/ 80 KB/144 KB DATA AND PROGRAM MEMORY 6144 B DATA MEMORY LB IO1 IO2 PROGRAMMABLE IO 1, 2, 3 UART ISO 7816 IO3 FameXE ENHANCED PUBLIC KEY COPROCESSOR e.g. RSA, ECC RST_N CLOCK FILTER CLOCK GENERATION SECURE_MX51 CPU TRIPLE-DES COPROCESSOR TIMERS SECURITY SENSORS RESET GENERATION CRC16 16-bit 16-bit T0 T1 AES COPROCESSOR FAST RNG VOLTAGE REGULATOR 12 of 18 © NXP B.V. 2008. All rights reserved. VDD VSS Fig 2. Functional diagram P5CD012/P5CD020/P5CD040/P5CD080/P5CD144 001aae953 P5Cx012/02x/40/73/80/144 family CLK Secure dual interface and contact PKI smart card controller Rev. 03 — 24 January 2008 MEMORY MANAGEMENT UNIT (MMU) xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors P5CX012_02X_40_73_80_144_FAM_SDS_3 Objective short data sheet P5CN080 P5CN144 SIGIN S2C INTERFACE CIU ISO 14443 ROM EEPROM RAM 200 KB PROGRAM MEMORY 80 KB/ 144 KB DATA AND PROGRAM MEMORY 6144 B DATA MEMORY SIGOUT IO1 PROGRAMMABLE IO 1, 2 UART ISO 7816 IO2 FameXE ENHANCED PUBLIC KEY COPROCESSOR e.g. RSA, ECC RST_N CLOCK FILTER CLOCK GENERATION SECURE_MX51 CPU TRIPLE-DES COPROCESSOR TIMERS SECURITY SENSORS RESET GENERATION CRC16 16-bit 16-bit T0 T1 AES COPROCESSOR FAST RNG VOLTAGE REGULATOR 13 of 18 © NXP B.V. 2008. All rights reserved. VDD VSS Fig 3. Functional diagram P5CN080/P5CN144 001aae955 P5Cx012/02x/40/73/80/144 family CLK Secure dual interface and contact PKI smart card controller Rev. 03 — 24 January 2008 MEMORY MANAGEMENT UNIT (MMU) P5Cx012/02x/40/73/80/144 family NXP Semiconductors Secure dual interface and contact PKI smart card controller 7. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS (ground = 0 V). Symbol Parameter Conditions Min Max Unit VDD supply voltage −0.5 +6.0 V VI input voltage any signal pad −0.5 VDD + 0.5 V II input current pad IO1, IO2 or IO3 - ±15.0 mA IO output current pad IO1, IO2 or IO3 - ±15.0 mA Ilu latch-up current VI < 0 V or VI > VDD - ±100 mA Vesd electrostatic discharge voltage pads VDD, VSS, CLK, RST_N, IO1, IO2, IO3 [1] - ±4.0 kV pads LA, LB [1] - ±2.0 kV - 1 W - - Ptot total power dissipation [2] Tstg storage temperature [3] [1] MIL Standard 883-D method 3015; human body model; C = 100 pF, R = 1.5 kΩ; Tamb = −25 °C to +85 °C. [2] Depending on appropriate thermal resistance of the package. [3] Depending on delivery type, refer to NXP Semiconductors General Specification for 8” Wafer and to NXP Semiconductors Contact & Dual Interface Chip Card Module Specification. 8. Abbreviations Table 6. Abbreviations Acronym Description AES Advanced Encryption Standard API Application Programming Interface ASK Amplitude Shift Keying CIU Contactless Interface Unit CRC Cyclic Redundancy Check CRT Chinese Remainder Theorem DES Digital Encryption Standard DFA Differential Fault Analysis DPA Differential Power Analysis DSS Digital Signature Standard ECC Elliptic Curve Cryptography ECDSA Elliptic Curve Digital Signature Algorithm EEPROM Electrically Erasable Programmable Read-Only Memory GF Galois Function MAC Message Authentication Code MMU Memory Management Unit P5CX012_02X_40_73_80_144_FAM_SDS_3 Objective short data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 24 January 2008 14 of 18 P5Cx012/02x/40/73/80/144 family NXP Semiconductors Secure dual interface and contact PKI smart card controller Table 6. Abbreviations …continued Acronym Description NFC Near Field Communication OS Operating System PKC Public Key Cryptography PKI Public Key Infrastructure PRNG Pseudo-Random Number Generator RNG Random Number Generator RSA Rivest, Shamir and Adleman S2C SigIn-SigOut-Connection SFI Single Fault Injection SHA Secure Hash Algorithm SMD Surface Mounted Device SPA Simple Power Analysis TPM Trusted Platform Module UART Universal Asynchronous Receiver/Transmitter 9. Revision history Table 7. Revision history Document ID Release date Data sheet status P5CX012_02X_40_73_80_ 144_FAM_SDS_3 20080124 Objective short data sheet Modifications: P5CX02X_40_73_80_144_ FAM_SDS_2 • • • Change notice Supersedes P5CX02X_40_73_80_144_ FAM_SDS_2 Type number P5CD012 added Table 3 “Ordering information” corrected and new type number added Figure 2 added 20070424 Objective short data sheet - P5CX02X_40_80_144_FAM _SDS_1 P5CX02X_40_80_144_FAM 20070216 _SDS_1 Objective short data sheet - - P5CX012_02X_40_73_80_144_FAM_SDS_3 Objective short data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 24 January 2008 15 of 18 NXP Semiconductors P5Cx012/02x/40/73/80/144 family Secure dual interface and contact PKI smart card controller 10. Legal information 10.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 10.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 10.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 10.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. MIFARE — is a trademark of NXP B.V. FabKey — is a trademark of NXP B.V. 11. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: [email protected] P5CX012_02X_40_73_80_144_FAM_SDS_3 Objective short data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 24 January 2008 16 of 18 NXP Semiconductors P5Cx012/02x/40/73/80/144 family Secure dual interface and contact PKI smart card controller 12. Tables Table 1. Table 2. Table 3. Table 4. Naming conventions . . . . . . . . . . . . . . . . . . . . . .2 Quick reference data . . . . . . . . . . . . . . . . . . . . .9 Ordering information . . . . . . . . . . . . . . . . . . . . .9 Feature table . . . . . . . . . . . . . . . . . . . . . . . . . .10 Table 5. Table 6. Table 7. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . 14 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15 13. Figures Fig 1. Fig 2. Fig 3. Functional diagram P5CC021/P5CC040/P5CC073/P5CC080/ P5CC144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Functional diagram P5CD012/P5CD020/P5CD040/P5CD080/ P5CD144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Functional diagram P5CN080/P5CN144 . . . . . . .13 continued >> P5CX012_02X_40_73_80_144_FAM_SDS_3 Objective short data sheet © NXP B.V. 2008. All rights reserved. Rev. 03 — 24 January 2008 17 of 18 NXP Semiconductors P5Cx012/02x/40/73/80/144 family Secure dual interface and contact PKI smart card controller 14. Contents 1 1.1 1.2 1.3 1.4 1.4.1 1.4.2 1.4.3 1.5 1.5.1 1.5.2 1.5.3 1.6 1.7 1.8 2 2.1 2.2 2.3 2.4 3 3.1 4 5 6 7 8 9 10 10.1 10.2 10.3 10.4 11 12 13 14 General description . . . . . . . . . . . . . . . . . . . . . . 1 SmartMX family approach . . . . . . . . . . . . . . . . 1 SmartMX family properties . . . . . . . . . . . . . . . . 1 Naming conventions . . . . . . . . . . . . . . . . . . . . . 2 Cryptographic hardware coprocessors . . . . . . . 2 FameXE coprocessor . . . . . . . . . . . . . . . . . . . 2 Triple-DES coprocessor . . . . . . . . . . . . . . . . . . 2 AES coprocessor . . . . . . . . . . . . . . . . . . . . . . . 2 SmartMX interfaces . . . . . . . . . . . . . . . . . . . . . 3 SmartMX contact interface . . . . . . . . . . . . . . . . 3 SmartMX contactless interface . . . . . . . . . . . . 3 SmartMX S2C interface . . . . . . . . . . . . . . . . . . 3 Security features. . . . . . . . . . . . . . . . . . . . . . . . 4 Security evaluation and certificates . . . . . . . . . 4 Optional crypto library. . . . . . . . . . . . . . . . . . . . 4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Standard family features . . . . . . . . . . . . . . . . . . 5 Product specific family features . . . . . . . . . . . . 6 Security features. . . . . . . . . . . . . . . . . . . . . . . . 7 Design-in support . . . . . . . . . . . . . . . . . . . . . . . 8 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Application areas . . . . . . . . . . . . . . . . . . . . . . . 8 Quick reference data . . . . . . . . . . . . . . . . . . . . . 9 Ordering information . . . . . . . . . . . . . . . . . . . . . 9 Functional diagram . . . . . . . . . . . . . . . . . . . . . 11 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 14 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Contact information. . . . . . . . . . . . . . . . . . . . . 16 Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 24 January 2008 Document identifier: P5CX012_02X_40_73_80_144_FAM_SDS_3