PHILIPS PN511

PN511
Transmission Module
Rev. 3.3 — 13 June 2007
Product short data sheet
082733
1. Introduction
This Product short data sheet describes the functionality of the transceiver IC PN511. It
includes functional and electrical specifications. A complete specification is given in the
product data sheet.
2. General description
The PN511 is a highly integrated transceiver IC for contactless communication at
13.56 MHz. This transceiver IC utilizes an outstanding modulation and demodulation
concept completely integrated for different kinds of contactless communication methods
and protocols at 13.56 MHz.
The PN511 transceiver ICs support 3 different operating modes
• Reader/Writer mode supporting ISO 14443A/Mifare and FeliCa scheme
• Card Operation mode supporting ISO 14443A/Mifare and FeliCa scheme
• NFCIP-1 mode
Enabled in Reader/Writer mode for ISO 14443A/Mifare, the PN511’s internal transmitter
part is able to drive a reader/writer antenna designed to communicate with ISO 14443A/
Mifare cards and transponders without additional active circuitry. The receiver part
provides a robust and efficient implementation of a demodulation and decoding circuitry
for signals from ISO 14443A/Mifare compatible cards and transponders. The digital part
handles the complete ISO 14443A framing and error detection (Parity & CRC).
The PN511 supports Mifare Classic (e.g. Mifare Standard) products. The PN511 supports
contactless communication using Mifare higher transfer speeds up to 424 kbit/s in both
directions.
Enabled in Reader/Writer mode for FeliCa, the PN511 transceiver IC supports the FeliCa
communication scheme. The receiver part provides a robust and efficient implementation
of the demodulation and decoding circuitry for FeliCa coded signals. The digital part
handles the FeliCa framing and error detection like CRC. The PN511 supports contactless
communication using FeliCa Higher transfer speeds up to 424 kbit/s in both directions.
In Card Operation mode, the PN511 transceiver IC is able to answer to a reader/writer
command either according to the FeliCa or ISO 14443A/Mifare card interface scheme.
The PN511 generates the digital load modulated signals and in addition with an external
circuit the answer can be sent back to the reader/writer. A complete card functionality is
only possible in combination with a secure core IC using the S2C interface.
PN511
NXP Semiconductors
Transmission Module
Additionally, the PN511 transceiver IC offers the possibility to communicate directly to an
NFCIP-1 device in the NFCIP-1 mode. The NFCIP-1 mode offers different communication
mode and transfer speeds up to 424 kbit/s according to the Ecma 340 and ISO/IEC 18092
NFCIP-1 Standard. The digital part handles the complete NFCIP-1 framing and error
detection.
Various host controller interfaces are implemented:
•
•
•
•
1.
8-bit parallel interface1
SPI interface
serial UART (similar to RS232 with voltage levels according pad voltage supply)
I2C interface.
8-bit parallel Interface only available in HVQFN40 package.
082733
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Rev. 3.3 — 13 June 2007
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PN511
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Transmission Module
3. Features
„ Highly integrated analog circuitry to demodulate and decode responses
„ Buffered output drivers to connect an antenna with minimum number of external
components
„ Integrated RF Level detector
„ Integrated data mode detector
„ ISO 14443A/Mifare support
„ Typical operating distance in Reader/Writer mode for communication to a ISO 14443A/
Mifare or FeliCa card up to 50 mm depending on the antenna size, tuning and power
supply
„ Typical operating distance in NFCIP-1 mode up to 50 mm depending on the antenna
size and tuning and power supply
„ Typical operating distance in ISO 14443A/Mifare card or FeliCa Card Operation mode
of about 100 mm depending on the antenna size and tuning and the external field
strength
„ Mifare Classic encryption in Reader/Writer mode support
„ ISO 14443A higher transfer speed communication at 212 kbit/s and 424 kbit/s
„ Contactless communication according to the FeliCa scheme at 212 kbit/s and
424 kbit/s
„ Integrated RF interface for NFCIP-1 up to 424 kbit/s
„ S2C interface
„ Supported host controller interfaces
‹ SPI interface up to 10 Mbit/s
‹ I2C interface up to 400 kbit/s in Fast mode, up to 3400 kbit/s in High-speed mode
‹ serial UART in different transfer speeds up to 1228.8 kbit/s, framing according to
the RS232 interface with voltage levels according pad voltage supply
‹ 8-bit parallel interface with and without Address Latch Enable
„ Comfortable 64 byte send and receive FIFO-buffer
„ Flexible interrupt modes
„ Hard reset with low power function
„ Power-down mode per software
„ Programmable timer
„ Internal oscillator to connect 27.12 MHz quartz
„ 2.5-3.6 V power supply
„ CRC Co-processor
„ Free programmable I/O pins
„ Internal self test
082733
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PN511
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Transmission Module
4. Quick reference data
Table 1.
Quick reference data
Symbol
Parameter
AVDD
Conditions
Supply Voltage
DVDD
AVSS = DVSS = PVSS= TVSS = 0 V,
[1][2]
PVDD ≤ AVDD = DVDD =TVDD
[1][2]
Min
Typ
Max
Unit
2.5
-
3.6
V
TVDD
[1][2]
PVDD
[3]
1.6
-
3.6
V
IHPD
Hard Power-down Current
AVDD = DVDD =
TVDD = PVDD = 3 V,
NRESET = LOW
[7]
-
-
5
μA
ISPD
Soft Power-down Current
AVDD = DVDD = TVDD = PVDD =
3 V, RF level detector on
[7]
-
-
10
μA
IDVDD
Digital Supply Current
DVDD = 3 V
-
6.5
9
mA
IAVDD
Analog Supply Current
AVDD = 3 V, bit RCVOff = 0
-
7
10
mA
IAVDD,RCVOFF
Analog Supply Current,
receiver switched off
AVDD = 3 V, bit RCVOff = 1
-
3
5
mA
IPVDD
Pad Supply Current
[5]
-
-
40
mA
ITVDD
Transmitter Supply Current
[4][6][8]
-
60
100
mA
Tamb
operating ambient temperature
+85
°C
Continuous Wave
-30
[1]
Supply voltage below 3 V reduces the performance (e.g. the achievable operating distance).
[2]
AVDD, DVDD and TVDD shall always be on the same voltage level.
[3]
PVDD shall always be on the same or lower voltage level than DVDD.
[4]
ITVDD depends on TVDD and the external circuitry connected to Tx1 and Tx2
[5]
IPVDD depends on the overall load at the digital pins.
[6]
During operation with a typical circuitry the overall current is below 100 mA.
[7]
ISPD and IHPD are the total currents over all supplies.
[8]
Typical value using a complementary driver configuration and an antenna matched to 40 Ω between TX1 and TX2 at 13.56 MHz
5. Ordering information
Table 2.
Ordering information
Type number
Package
Name
Description
Version
PN5110A0HN1/C2
HVQFN32
Plastic thermal enhanced very thin quad flat package; no leads;
32 terminals; body 5 × 5 × 0.85 mm
SOT617
PN5110A0HN/C2
HVQFN40
Plastic thermal enhanced very thin quad flat package; no leads;
40 terminals; body 6× 6× 0.85 mm
SOT618
082733
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PN511
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Transmission Module
6. Block diagram
The Analog interface handles the modulation and demodulation of the analog signals
according to the Card Receiving mode, Reader/Writer mode and NFCIP-1 mode
communication scheme.
The RF level detector detects the presence of an external RF-field delivered by the
antenna to the RX pin.
The Data mode detector detects a Mifare, FeliCa or NFCIP-1 mode in order to prepare the
internal receiver to demodulate signals, which are sent to the PN511.
The communication (S2C) interface provides digital signals to support communication for
transfer speeds above 424 kbit/s and digital signals to communicate to a secure smart
card IC.
082733
Product short data sheet
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PN511
NXP Semiconductors
Transmission Module
NWR NRD
NCS
ALE
A0 to A5
D0 to D7
PVSS
PVDD
DVDD
Voltage
Monitor
&
Power On
Detect
8 bit Parallel, SPI, UART, I2C Interface Control
(incl. Automatic Interface Detection & Synchronisation)
FIFO Control
DVSS
AVDD
AVSS
State Machine
Command Register
Reset
Control
Programable Timer
Power Down
Control
64 Byte FIFO
NRSTPD
Control Register Bank
Interrupt Control
IRQ
CRC16
Generation & Check
MIFARE Classic Unit
Parallel/Seriell Converter
Random Number Generator
Bit Counter
Parity Generation & Check
Frame Generation & Check
Bit Decoding
Bit Coding
Card Mode Detector
SIGIN
SIGOUT
Serial Data Switch
LOADMOD
Amplitude
Rating
A/D Converter
Reference
Voltage
Analog Test
MUX and
DAC
I-Channel
Amplifier
Q-Channel
Amplifier
I-Channel
Demodulator
Q-Channel
Demodulator
Clock
Generation,
Filtering and
Distribution
Oscillator
Q-Clock
Generation
Temperature
Sensor
V+
G ND
RF clock
recovery
V+
G ND
AUX1,2
OSCOUT
Transmitter Control
RF Level
Detector
VMID
OSCIN
RX
TVSS
TX1
TX2
TVDD
Fig 1. PN511 Block diagram
082733
Product short data sheet
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PN511
NXP Semiconductors
Transmission Module
7. Pinning information
25 D1
26 D2
27 D3
28 D4
29 D5
30 D6
32 A0
terminal 1
index area
31 D7
7.1 Pinning
A1
1
24 ALE
PVDD
2
23 IRQ
DVDD
3
22 OSCOUT
DVSS
4
PVSS
5
NRSTPD
6
19 AUX1
SIGIN
7
18 AVSS
SIGOUT
8
17 RX
21 OSCIN
VMID 16
AVDD 15
20 AUX2
TVSS 14
TX2 13
TVDD 12
TX1 11
9
LOADMOD
TVSS 10
PN511
SOT617-1
Transparent top view
31 D0
32 D1
33 D2
34 D3
35 D4
36 D5
37 D6
38 D7
40 A1
terminal 1
index area
39 A0
Fig 2. Pinning configuration HVQFN32 (SOT617-1)
A2
1
30 NCS
A3
2
29 ALE
A4
3
28 NRD
A5
4
27 NWR
PVDD
5
DVDD
6
DVSS
7
24 OSCIN
PVSS
8
23 AUX2
NRSTPD
9
22 AUX1
SIGIN 10
21 AVSS
26 IRQ
RX 20
VMID 19
AVDD 18
25 OSCOUT
TVSS 17
TX2 16
TVDD 15
TX1 14
TVSS 13
SIGOUT 11
LOADMOD 12
PN511
SOT618-1
Transparent top view
Fig 3. Pinning configuration HVQFN40 (SOT618)
082733
Product short data sheet
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Rev. 3.3 — 13 June 2007
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PN511
NXP Semiconductors
Transmission Module
7.2 Pin description
Table 3.
Pin description HVQFN32
Symbol
Pin
Type
Description
A1
1
I
Address Line
PVDD
2
PWR
Pad power supply
DVDD
3
PWR
Digital Power Supply
DVSS
4
PWR
Digital Ground
PVSS
5
PWR
Pad power supply ground
NRSTPD
6
I
Not Reset and Power Down: When LOW, internal current sinks are switched off, the
oscillator is inhibited, and the input pads are disconnected from the outside world. With
a positive edge on this pin the internal reset phase starts.
SIGIN
7
I
Communication Interface Input: accepts a digital, serial data stream
SIGOUT
8
O
Communication Interface Output: delivers a serial data stream
LOADMOD
9
O
Load Modulation Output: provides digital signal for FeliCa and Mifare Card Operation
mode
TVSS
10
PWR
Transmitter Ground: supplies the output stage of TX1 and TX2
TX1
11
O
Transmitter 1: delivers the modulated 13.56 MHz energy carrier
TVDD
12
PWR
Transmitter Power Supply: supplies the output stage of TX1 and TX2
TX2
13
O
Transmitter 2: delivers the modulated 13.56 MHz energy carrier
TVSS
14
PWR
Transmitter Ground: supplies the output stage of TX1 and TX2
AVDD
15
PWR
Analog Power Supply
VMID
16
PWR
Internal Reference Voltage: This pin delivers the internal reference voltage.
RX
17
I
Receiver Input
AVSS
18
PWR
Analog Ground
AUX1
19
O
Auxiliary Outputs: These pins are used for testing.
AUX2
20
O
OSCIN
21
I
Crystal Oscillator Input: input to the inverting amplifier of the oscillator. This pin is
also the input for an externally generated clock (fosc = 27.12 MHz).
OSCOUT
22
O
Crystal Oscillator Output: Output of the inverting amplifier of the oscillator.
IRQ
23
O
Interrupt Request: output to signal an interrupt event
ALE
24
I
Address Latch Enable: signal to latch AD0 to AD5 into the internal address latch
when HIGH.
D1 to D7
25 to 31
I/O
8-bit Bi-directional Data Bus.
Remark: An 8-bit parallel interface is not available.
Remark: If the host controller selects I2C as digital host controller interface, these pins
can be used to define the I2C address.
Remark: For serial interfaces this pins can be used for test signals or I/Os.
A0
32
I
Address Line
082733
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PN511
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Transmission Module
Table 4.
Pin description HVQFN40
Symbol
Pin
Type
Description
A2 to A5
1 to 4
I
Address Line
PVDD
5
PWR
Pad power supply
DVDD
6
PWR
Digital Power Supply
DVSS
7
PWR
Digital Ground
PVSS
8
PWR
Pad power supply ground
NRSTPD
9
I
Not Reset and Power Down: When LOW, internal current sinks are switched off, the
oscillator is inhibited, and the input pads are disconnected from the outside world. With
a positive edge on this pin the internal reset phase starts.
SIGIN
10
I
Communication Interface Input: accepts a digital, serial data stream
SIGOUT
11
O
Communication Interface Output: delivers a serial data stream
LOADMOD
12
O
Load Modulation Output: provides digital signal for FeliCa and Mifare Card Operation
mode
TVSS
13
PWR
Transmitter Ground: supplies the output stage of TX1 and TX2
TX1
14
O
Transmitter 1: delivers the modulated 13.56 MHz energy carrier
TVDD
15
PWR
Transmitter Power Supply: supplies the output stage of TX1 and TX2
TX2
16
O
Transmitter 2: delivers the modulated 13.56 MHz energy carrier
TVSS
17
PWR
Transmitter Ground: supplies the output stage of TX1 and TX2
AVDD
18
PWR
Analog Power Supply
VMID
19
PWR
Internal Reference Voltage: This pin delivers the internal reference voltage.
RX
20
I
Receiver Input
AVSS
21
PWR
Analog Ground
AUX1
22
O
Auxiliary Outputs: These pins are used for testing.
AUX2
23
O
OSCIN
24
I
Crystal Oscillator Input: input to the inverting amplifier of the oscillator. This pin is
also the input for an externally generated clock (fosc = 27.12 MHz).
OSCOUT
25
O
Crystal Oscillator Output: Output of the inverting amplifier of the oscillator.
IRQ
26
O
Interrupt Request: output to signal an interrupt event
NWR
27
I
Not Write: strobe to write data (applied on D0 to D7) into the PN511 register
NRD
28
I
Not Read: strobe to read data from the PN511 register (applied on D0 to D7)
ALE
29
I
Address Latch Enable: signal to latch AD0 to AD5 into the internal address latch
when HIGH.
NCS
30
I
Not Chip Select: selects and activates the host controller interface of the PN511
D0 to D7
31 to 38
I/O
8-bit Bi-directional Data Bus.
Remark: For serial interfaces this pins can be used for test signals or I/Os.
Remark: If the host controller selects I2C as digital host controller interface, these pins
can be used to define the I2C address.
A0 to1 A1
39 to 40
I
Address Line
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PN511
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Transmission Module
8. Operating modes
PN511 transceiver IC supports the following operating modes:
• Reader/Writer mode supporting ISO 14443A/Mifare and FeliCa scheme
• Card Operation mode supporting ISO 14443A/ Mifare and FeliCa scheme
• NFCIP-1 mode
The modes support different transfer speeds and modulation schemes. The following
chapters will explain the different modes in detail.
Note: All indicated modulation indices and modes in this chapter are system parameters.
This means that beside the IC settings a suitable antenna tuning is required to achieve the
optimum performance.
8.1 Reader/Writer mode
Generally 2 Reader/Writer modes are supported. The PN511 can act as a reader/writer for
ISO 14443A/Mifare or FeliCa cards.
Battery
ISO14443A or
FeliCa Card
PN511
µC
Contactless Card
Reader / Writer
Fig 4. Reader/Writer mode
In the Reader/Writer mode the PN511 enables the communication to a contactless
ISO 14443A/Mifare or FeliCa card.
8.1.1 ISO 14443A/Mifare reader/writer functionality
The ISO 14443A/Mifare Reader/Writer mode is the general reader to card communication
scheme according to the ISO 14443A/Mifare specification.The following diagram
describes the communication on a physical level, the communication table describes the
physical parameters.
ISO14443A
Reader (PCD)
1. PCD to PICC 100 % ASK ,
Miller Coded,
baudrate 106 to 424 kbaud
ISO14443A
Card (PICC)
PN511
2. PICC to PCD, Subcarrier Loadmodulation,
Manchester Coded or BPSK,
baudrate 106 to 424 kbaud
Fig 5.
ISO 14443A/Mifare Reader/Writer mode communication diagram
082733
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PN511
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Transmission Module
Table 5.
Communication overview for ISO 14443A/Mifare reader/writer
Communication
direction
transfer speed
ISO 14443A/Mifare
Mifare Higher transfer speeds
106 kbit/s
212 kbit/s
424 kbit/s
PN511 → PICC
(send data from
the PN511 to a
card)
Modulation on
reader side
100% ASK
100% ASK
100% ASK
bit coding
Modified Miller coding
Modified Miller
coding
Modified Miller
coding
Bitlength
(128/13.56) μs
(64/13.56) μs
(32/13.56) μs
modulation on
card side
subcarrier load
modulation
subcarrier load
modulation
subcarrier load
modulation
subcarrier
frequency
13.56 MHz/16
13.56 MHz/16
13.56 MHz/16
bit coding
Manchester coding
BPSK
BPSK
PICC → PN511
(receive data
from a card)
The contactless UART of PN511 and a dedicated external host controller are required to
handle the complete Mifare/ISO 14443A/Mifare protocol.
8.1.1.1
Data Coding and framing according to ISO 14443A/Mifare
The internal CRC co-processor calculates the CRC value according to the definitions
given in the ISO 14443A part 3 and handles parity generation internally according to the
transfer speed.
Current ISO14443 Framing for Type A for 106 kBaud
Start
8 bit data
odd
Par.
8 bit data
odd
Par.
8 bit data
odd
Par.
8 bit data
even
Par.
Start Bit is "1"
MIFARE Higher Baudrate Framing for 212, 424 kBaud
Start
8 bit data
odd
Par.
8 bit data
Start Bit is "0"
Even parity at the
end of the frame!
Burst of 32
sub-carrier
clocks
Fig 6.
odd
Par.
Data Coding and framing according to ISO 14443A
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PN511
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Transmission Module
8.1.2 FeliCa reader/writer functionality
The FeliCa mode is the general reader/writer to card communication scheme according to
the FeliCa specification. The following diagram describes the communication on a
physical level, the communication overview describes the physical parameters.
1. PCD to PICC 8-30 % ASK
,Manchester Coded,
baudrate 212 to 424 kbaud
FeliCa Reader
(PCD)
FeliCa Card
(PICC)
PN511
2. PICC to PCD, >12 % ASK Loadmodulation
,
Manchester Coded,
baudrate 212 to 424 kbaud
Fig 7.
FeliCa reader/writer Communication Diagram
Table 6.
Communication overview for FeliCa reader/writer
Communication
direction
PN511 → card
card → PN511
FeliCa
FeliCa Higher
transfer speeds
Transfer speed
212 kbit/s
424 kbit/s
Modulation on reader side
8-30% ASK
8-30% ASK
bit coding
Manchester Coding
Manchester Coding
Bitlength
(64/13.56) μs
(32/13.56) μs
Loadmodulation on card side
>12% ASK
>12% ASK
bit coding
Manchester coding
Manchester coding
The contactless UART of PN511 and a dedicated external host controller are required to
handle the complete FeliCa protocol.
8.1.2.1
FeliCa framing and coding
Table 7.
FeliCa framing and coding
Preamble
00h
00h
00h
Sync
00h
00h
00h
B2h
Len
n-Data
CRC
4Dh
To enable the FeliCa communication a 6 byte preamble (00h, 00h, 00h, 00h, 00h, 00h)
and 2 bytes Sync bytes (B2h, 4Dh) are sent to synchronize the receiver.
The following Len byte indicates the length of the sent data bytes plus the LEN byte itself.
The CRC calculation is done according to the FeliCa definitions with the MSB first.
To transmit data on the RF interface, the host controller has to send the Len- and databytes to the PN511's FIFO buffer. The preamble and the sync bytes are generated by the
PN511 automatically and must not be written to the FIFO by the host controller. The
PN511 performs internally the CRC calculation and adds the result to the data frame.
Example for FeliCa CRC Calculation:
Table 8.
Start Value for the CRC Polynomial: (00h), (00h)
Preamble
00h
00h
00h
00h
Sync
00h
00h
B2h
082733
Product short data sheet
4Dh
Len
03h
2 Data Bytes
ABh
CDh
CRC
90h
35h
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PN511
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Transmission Module
8.2 NFCIP-1 mode
The NFCIP-1 communication differentiates between an active and a Passive
Communication mode.
• Active Communication mode means both the initiator and the target are using their
own RF field to transmit data.
• Passive Communication mode means that the target answers to an initiator command
in a load modulation scheme. The initiator is active in terms of generating the RF field.
• Initiator: generates RF field at 13.56 MHz and starts the NFCIP-1 communication
• Target: responds to initiator command either in a load modulation scheme in Passive
Communication mode or using a self generated and self modulated RF field for Active
Communication mode.
In order to fully support the NFCIP-1 standard the PN511 supports the Active and Passive
Communication mode at the transfer speeds 106 kbit/s, 212 kbit/s and 424 kbit/s as
defined in the NFCIP-1 standard.
Battery
µC
PN511
µC
PN511
Battery
Initiator:Active
Target:
Passive or
Active
Fig 8. NFCIP-1 mode
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PN511
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Transmission Module
8.2.1 Active Communication mode
Active Communication mode means both the initiator and the target are using their own
RF field to transmit data.
Initial Command
Host
Host
NFC Target
NFC Initiator
1. Initiator starts communication at
selected transfer speed
powered to
generate RF field
powered for digital
processing
Response
Host
NFC Initiator
NFC Target
Host
2. Target answers at the
same transfer speed
powered to
generate RF field
powered for digital
processing
Fig 9. Active Communication mode
Table 9.
Communication Overview for Active Communication mode
Communication 106 kbit/s
direction
212 kbit/s
424 kbit/s
848 kbit/s
1.69 Mbit/s,
3.39 Mbit/s
Initiator → Target According to
Target → Initiator ISO 14443A
100% ASK,
Modified
Miller Coded
According to FeliCa, 8-30% digital capability to handle
ASK Manchester Coded
this communication
The contactless UART of PN511 and a dedicated host controller are required to handle
the NFCIP-1 protocol.
Note: Transfer Speeds above 424 kbit/s are not defined in the NFCIP-1 standard. The
PN511 supports these transfer speeds only with dedicated external circuits.
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PN511
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Transmission Module
8.2.2 Passive Communication mode
Passive Communication mode means that the target answers to an initiator command in a
load modulation scheme. The initiator is active meaning generating the RF field.
Fig 10. Passive Communication mode
Table 10.
Communication Overview for Passive Communication mode
Communication 106 kbit/s
direction
212 kbit/s
424 kbit/s
848 kbit/s
1.69 Mbit/s,
3.39 Mbit/s
Initiator → Target According to
ISO 14443A
100% ASK,
Modified
Miller Coded
According to FeliCa, 8-30% digital capability to handle
ASK Manchester Coded
this communication
Target → Initiator According to
According to FeliCa, >12%
ISO 14443A
ASK Manchester Coded
subcarrier load
modulation,
Manchester Coded
The contactless UART of PN511 and a dedicated host controller are required to handle
the NFCIP-1 protocol.
Note: Transfer Speeds above 424 kbit/s are not defined in the NFCIP-1 standard. The
PN511 supports these transfer speeds only with dedicated external circuits.
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8.2.3 NFCIP-1 framing and coding
The NFCIP-1 framing and coding in Active and Passive Communication mode is defined
in the NFCIP-1 standard.
Table 11.
Framing and Coding Overview
Transfer speed
Framing and Coding
106 kbit/s
According to the ISO 14443A/Mifare scheme
212 kbit/s
According to the FeliCa scheme
424 kbit/s
According to the FeliCa scheme
8.2.4 NFCIP-1 Protocol Support
The NFCIP-1 protocol is not completely described in this document. For detailed
explanation of the protocol refer to the NFCIP-1 standard. However the datalink layer is
according to the following policy:
• Speed shall not be changed while continuum data exchange in a transaction.
• Transaction includes initialization and anticollision methods and data exchange (in
continuous way, meaning no interruption by another transaction).
In order not to disturb current infrastructure based on 13.56 MHz general rules to start
NFCIP-1 communication are defined in the following way.
1. Per default NFCIP-1 device is in Target mode meaning its RF field is switched off.
2. The RF level detector is active.
3. Only if application requires the NFCIP-1 device shall switch to Initiator mode.
4. Initiator shall only switch on its RF field if no external RF field is detected by RF Level
detector during a time of TIDT.
5. The initiator performs initialization according to the selected mode.
8.3 Card Operation mode
The PN511 can be addressed like a FeliCa or ISO 14443A/Mifare card. This means that
the PN511 can generate an answer in a load modulation scheme according to the
ISO 14443A/Mifare or FeliCa interface description.
Note: The PN511 does not support a complete card protocol. This has to be handled by a
dedicated card SAM or a host controller. The card-SAM is optional.
Reader/ Writer for FeliCa
or MIFARE
Generates RF
field
PN511
µC and
Sam (opt.)
Battery
Answers in
Loadmodulation
scheme
Fig 11. Card Operation mode
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8.3.1 Mifare Card Operation mode
Table 12.
Mifare Card Operation mode
Communication
ISO 14443A/Mifare
direction
Transfer speed 106 kbit/s
Mifare Higher transfer speeds
212 kbit/s
424 kbit/s
reader / writer → Modulation on
PN511
reader side
100% ASK
100% ASK
100% ASK
bit coding
Modified Miller
Modified Miller
Modified Miller
Bitlength
(128/13.56) μs
(64/13.56) μs
(32/13.56) μs
subcarrier load
modulation
subcarrier load
modulation
subcarrier load
modulation
subcarrier
frequency
13.56 MHz/16
13.56 MHz/16
13.56 MHz/16
bit coding
Manchester coding
BPSK
BPSK
PN511 → reader/ Modulation on
writer
PN511 side
8.3.2 FeliCa Card Operation mode
FeliCa Card Operation mode
Communication
direction
reader/writer →
PN511
FeliCa
FeliCa Higher
transfer speeds
Transfer speed
212 kbit/s
424 kbit/s
Modulation on reader side
8-30% ASK
8-30% ASK
bit coding
Manchester Coding
Manchester Coding
Bitlength
(64/13.56) μs
(32/13.56) μs
>12% ASK load
modulation
>12% ASK load
modulation
Manchester coding
Manchester coding
PN511 → reader/ Load modulation on PN511
writer
side
bit coding
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9. Application design-in information
The figure below shows a typical circuit diagram, using a complementary antenna
connection to the PN511.
The antenna tuning and RF part matching is described in the application note PN511
transceiver IC; Antenna and RF Design Guide
supply
DVDD
AVDD
PVDD
TVDD
CRx
RX
R1
VMID
PVSS
R2
Cvmid
NRSTPD
TX1
Host
Controller
PN511
Interface
C1
L0
C0
RQ
C2
TVSS
Antenna
C0
IRQ
TX2
IRQ
L0
C1
RQ
DVSS
AVSS
OSCIN
C2
OSCOUT
27,12
MHz
Fig 12. Typical Circuit Diagram
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10. Limiting values
Table 13. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
PVDD
Conditions
Min
Max
Unit
Supply voltage
-0.5
+4.0
V
Ptot
Total power dissipation per package (VBUS
and DVDD in short cut mode)
-
200
mW
TJ
Junction temperature range
100
°C
ESDH
ESD Susceptibility (Human Body model)
1500 Ω, 100 pF;
JESD22-A114-B
2000
V
ESDM
ESD Susceptibility (Machine model)
0.75 μH, 200 pF;
JESD22-A114-A
200
V
ESDC
ESD Susceptibility (Charge Device model)
Field induced model;
JESC22-C101-A
1000
V
11. Package information
The PN511 can be delivered in 2 different packages.
Table 14.
Package Information
Package
Remarks
HVQFN32
8-bit parallel interface not supported
HVQFN40
Supports the 8-bit parallel interface
12. Abbreviations
Table 15.
Abbreviations
Acronym
Description
ASK
Amplitude Shift keying
Initiator
Generates RF field at 13.56 MHz and starts the NFCIP-1 communication.
Loadmodulation Index
The load modulation index is defined as the card’s voltage ratio (Vmax - Vmin)/ (Vmax + Vmin)
measured at the card’s coil.
Modulation Index
The modulation index is defined as the voltage ratio (Vmax - Vmin)/ (Vmax + Vmin).
PCD
Proximity Coupling Device. Definition for a Card reader/writer according to the ISO 14443
specification.
PICC
Proximity Cards. Definition for a contactless Smart Card according to the ISO 14443
specification.
PCD → PICC
Communication flow between a PCD and a PICC according to the ISO 14443A/Mifare.
PICC → PCD
Communication flow between a PICC and a PCD according to the ISO 14443A/Mifare.
SAM
Secure Access Module
Target
Responds to initiator command either using load modulation scheme (RF field generated by
Initiator) or using modulation of self generated RF field (no RF field generated by initiator).
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13. Revision history
Table 16.
Revision history
Document ID
Release date
Data sheet status
082733
Juni 2007
Product short data sheet
Modifications:
082732
Modifications:
082731
Modifications:
•
Supersedes
Revision 3.2
Add Section 14.4 “Licenses”
Januar 2007
•
•
Change notice
Product short data sheet
Revision 3.1
Usage of expression “host controller” unified
Order information “Type number” in Table 2 on page 4 updated from PN5110A0HN1/C1 to
PN5110A0HN1/C2
16 October 2006
Product short data sheet
Revision 3.0
•
The format of this data sheet has been redesigned to comply with the new identity guidelines
of NXP Semiconductors.
•
•
Legal texts have been adapted to the new company name where appropriate.
Section 7.2 “Pin description” on page 8:
- corrected in Table 3 “Pin description HVQFN32” Type of Pin 12: 0 -> PWR
- corrected in Table 4 “Pin description HVQFN40” on page 9 Type of Pin 15: 0 -> PWR
•
Section 8.1.2 “FeliCa reader/writer functionality” on page 12:
- Table 6 “Communication overview for FeliCa reader/writer” renamed Table Title
082730
7 July 2006
Product short data sheet
Revision 2.0
082720
1 February 2004
Preliminary short data sheet
Revision 1.0
082710
1 March 2003
Objective short data sheet
-
082733
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PN511
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14. Legal information
14.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
14.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
14.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of a NXP Semiconductors product can reasonably be expected to
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
14.4 Licenses
Purchase of an NXP Semiconductors IC that complies with one of the NFC Standards (ISO/IEC18.092; ISO/IEC21.481) does not convey an implied license under any patent right on that standards.
Purchase of an NXP Semiconductors IC that complies with one of the NFC
Standards (ISO/IEC18.092; ISO/IEC21.481) does not convey an implied
license under any patent right on that standards. A license for the portfolio of
the NFC Standards patents of NXP B.V. needs to be obtained at Via
Licensing, the pool agent of the NFC Patent Pool,
e-mail: [email protected]
14.5 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Mifare — is a trademark of NXP B.V.
15. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: [email protected]
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16. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Quick reference data . . . . . . . . . . . . . . . . . . . . .4
Ordering information . . . . . . . . . . . . . . . . . . . . .4
Pin description HVQFN32 . . . . . . . . . . . . . . . . .8
Pin description HVQFN40 . . . . . . . . . . . . . . . . .9
Communication overview for ISO 14443A/Mifare
reader/writer . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Communication overview for FeliCa
reader/writer . . . . . . . . . . . . . . . . . . . . . . . . . . .12
FeliCa framing and coding . . . . . . . . . . . . . . . .12
Start Value for the CRC Polynomial:
(00h), (00h) . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Communication Overview for Active
Communication mode . . . . . . . . . . . . . . . . . . . 14
Communication Overview for Passive
Communication mode . . . . . . . . . . . . . . . . . . . 15
Framing and Coding Overview . . . . . . . . . . . . 16
Mifare Card Operation mode . . . . . . . . . . . . . . 17
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 19
Package Information . . . . . . . . . . . . . . . . . . . . 19
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 19
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 20
17. Figures
Fig 1.
Fig 2.
Fig 3.
Fig 4.
Fig 5.
PN511 Block diagram . . . . . . . . . . . . . . . . . . . . . .6
Pinning configuration HVQFN32 (SOT617-1) . . . .7
Pinning configuration HVQFN40 (SOT618) . . . . . .7
Reader/Writer mode. . . . . . . . . . . . . . . . . . . . . . .10
ISO 14443A/Mifare Reader/Writer mode
communication diagram. . . . . . . . . . . . . . . . . . . .10
Fig 6.
Data Coding and framing according to
ISO 14443A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Fig 7.
FeliCa reader/writer Communication Diagram . . 12
Fig 8. NFCIP-1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Fig 9. Active Communication mode . . . . . . . . . . . . . . . 14
Fig 10. Passive Communication mode . . . . . . . . . . . . . . 15
Fig 11. Card Operation mode . . . . . . . . . . . . . . . . . . . . . 16
Fig 12. Typical Circuit Diagram . . . . . . . . . . . . . . . . . . . . 18
18. Contents
1
2
3
4
5
6
7
7.1
7.2
8
8.1
8.1.1
8.1.1.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Quick reference data . . . . . . . . . . . . . . . . . . . . . 4
Ordering information . . . . . . . . . . . . . . . . . . . . . 4
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pinning information . . . . . . . . . . . . . . . . . . . . . . 7
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8
Operating modes . . . . . . . . . . . . . . . . . . . . . . . 10
Reader/Writer mode . . . . . . . . . . . . . . . . . . . . 10
ISO 14443A/Mifare reader/writer functionality 10
Data Coding and framing according to
ISO 14443A/Mifare . . . . . . . . . . . . . . . . . . . . . 11
8.1.2
FeliCa reader/writer functionality . . . . . . . . . . 12
8.1.2.1
FeliCa framing and coding . . . . . . . . . . . . . . . 12
8.2
NFCIP-1 mode . . . . . . . . . . . . . . . . . . . . . . . . 13
8.2.1
Active Communication mode . . . . . . . . . . . . . 14
8.2.2
Passive Communication mode . . . . . . . . . . . . 15
8.2.3
NFCIP-1 framing and coding . . . . . . . . . . . . . 16
8.2.4
8.3
8.3.1
8.3.2
9
10
11
12
13
14
14.1
14.2
14.3
14.4
14.5
15
16
17
18
NFCIP-1 Protocol Support . . . . . . . . . . . . . . .
Card Operation mode . . . . . . . . . . . . . . . . . .
Mifare Card Operation mode . . . . . . . . . . . . .
FeliCa Card Operation mode . . . . . . . . . . . . .
Application design-in information . . . . . . . . .
Limiting values . . . . . . . . . . . . . . . . . . . . . . . .
Package information. . . . . . . . . . . . . . . . . . . .
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . .
Legal information . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . .
Licenses. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
16
17
17
18
19
19
19
20
21
21
21
21
21
21
21
22
22
22
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 13 June 2007
Document identifier: 082733