74LVC2G74 Single D-type flip-flop with set and reset; positive edge trigger Rev. 01 — 3 November 2005 Product data sheet 1. General description The 74LVC2G74 is a high-performance, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The 74LVC2G74 is a single positive edge triggered D-type flip-flop with individual data (D) inputs, clock (CP) inputs, set (SD) and (RD) inputs, and complementary Q and Q outputs. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing damaging backflow current through the device when it is powered down. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D inputs must be stable, one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. Schmitt-trigger action at all inputs makes the circuit highly tolerant to slower input rise and fall times. 2. Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant inputs for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: ◆ JESD8-7 (1.65 V to 1.95 V) ◆ JESD8-5 (2.3 V to 2.7 V) ◆ JESD8-B/JESD36 (2.7 V to 3.6 V) ±24 mA output drive (VCC = 3.0 V) ESD protection: ◆ HBM EIA/JESD22-A114-C exceeds 2000 V ◆ MM EIA/JESD22-A115-A exceeds 200 V CMOS low power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels Inputs accept voltages up to 5 V Multiple package options Specified from −40 °C to +85 °C and −40 °C to +125 °C 74LVC2G74 Philips Semiconductors Single D-type flip-flop with set and reset; positive edge trigger 3. Quick reference data Table 1: Quick reference data GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns. Symbol Parameter Conditions Min Typ Max Unit CP to Q, Q CL = 50 pF; VCC = 3.3 V - 3.5 - ns SD to Q, Q CL = 50 pF; VCC = 3.3 V - 3.0 - ns RD to Q, Q CL = 50 pF; VCC = 3.3 V - 3.0 - ns fmax maximum input clock CL = 50 pF; VCC = 3.3 V frequency - 280 - MHz Ci input capacitance - 4.0 - pF - 15 - pF tPHL, tPLH propagation delay power dissipation capacitance CPD [1] [2] VCC = 3.3 V [1] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of the outputs. [2] The condition is VI = GND to VCC. 4. Ordering information Table 2: Ordering information Type number Package Temperature range Name Description Version 74LVC2G74DP −40 °C to +125 °C TSSOP8 plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2 74LVC2G74DC −40 °C to +125 °C VSSOP8 plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1 74LVC2G74GT −40 °C to +125 °C XSON8 plastic extremely thin small outline package; no leads; 8 terminals; body 1 × 1.95 × 0.5 mm SOT833-1 5. Marking Table 3: Marking Type number Marking code 74LVC2G74DP V74 74LVC2G74DC V74 74LVC2G74GT V74 74LVC2G74_1 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 3 November 2005 2 of 20 74LVC2G74 Philips Semiconductors Single D-type flip-flop with set and reset; positive edge trigger 6. Functional diagram 7 SD 2 1 D CP SD Q D Q 7 5 1 2 CP FF Q Q 6 3 S 5 C1 1D 3 R mnb140 RD RD 6 mnb139 Fig 1. Logic symbol Fig 2. IEC logic symbol Q C C C C C C D Q C C RD SD CP mna421 C C Fig 3. Logic diagram 74LVC2G74_1 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 3 November 2005 3 of 20 74LVC2G74 Philips Semiconductors Single D-type flip-flop with set and reset; positive edge trigger 7. Pinning information 7.1 Pinning 74 CP 1 D 2 Q 3 GND 4 74 8 VCC 7 SD 6 RD 5 Q CP 1 8 VCC D 2 7 SD Q 3 6 RD GND 4 5 Q 001aab658 Transparent top view 001aab659 Fig 4. Pin configuration TSSOP8 and VSSOP8 Fig 5. Pin configuration XSON8 7.2 Pin description Table 4: Pin description Symbol Pin Description CP 1 clock input (LOW-to-HIGH, edge-triggered) D 2 data input Q 3 complement flip-flop output GND 4 ground (0 V) Q 5 true flip-flop output RD 6 asynchronous reset-direct input (active LOW) SD 7 asynchronous set-direct input (active LOW) VCC 8 supply voltage 8. Functional description 8.1 Function table Table 5: Function table for asynchronous operation Input Output SD RD CP D Q Q L H X X H L H L X X L H L L X X H H [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care. 74LVC2G74_1 Product data sheet [1] © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 3 November 2005 4 of 20 74LVC2G74 Philips Semiconductors Single D-type flip-flop with set and reset; positive edge trigger Table 6: Function table for synchronous operation [1] Input Output SD RD CP D Qn+1 Qn+1 H H ↑ L L H H H ↑ H H L [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = LOW-to-HIGH CP transition; Qn+1 = state after the next LOW-to-HIGH CP transition. 9. Limiting values Table 7: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions VCC supply voltage IIK input clamping current VI < 0 V VI input voltage output clamping current VO > VCC or VO < 0 V VO output voltage Max Unit −0.5 +6.5 V - −50 mA −0.5 +6.5 V - ±50 mA [1] IOK Min active mode [1] [2] −0.5 VCC + 0.5 V Power-down mode [1] [2] −0.5 +6.5 V IO output current - ±50 mA ICC quiescent supply current - ±100 mA IGND ground current - ±100 mA Tstg storage temperature −65 +150 °C Ptot total power dissipation - 250 mW VO = 0 V to VCC Tamb = −40 °C to +125 °C [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation. 10. Recommended operating conditions Table 8: Recommended operating conditions Symbol Parameter VCC Conditions Min Typ Max Unit supply voltage 1.65 - 5.5 V VI input voltage 0 - 5.5 V VO output voltage active mode 0 - VCC V Power-down mode; VCC = 0 V 0 - 5.5 V −40 - +125 °C VCC = 1.65 V to 2.7 V 0 - 20 ns/V VCC = 2.7 V to 5.5 V 0 - 10 ns/V Tamb ambient temperature ∆t/∆V input transition rise and fall rate 74LVC2G74_1 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 3 November 2005 5 of 20 74LVC2G74 Philips Semiconductors Single D-type flip-flop with set and reset; positive edge trigger 11. Static characteristics Table 9: Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = −40 °C to +85 VIH VIL VOH VOL Conditions Min Typ Max Unit °C [1] 0.65 × VCC - - V VCC = 2.3 V to 2.7 V 1.7 - - V VCC = 2.7 V to 3.6 V 2.0 - - V VCC = 4.5 V to 5.5 V 0.7 × VCC - - V HIGH-state input voltage VCC = 1.65 V to 1.95 V LOW-state input voltage HIGH-state output voltage LOW-state output voltage VCC = 1.65 V to 1.95 V - - 0.35 × VCC V VCC = 2.3 V to 2.7 V - - 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 V VCC = 4.5 V to 5.5 V - - 0.3 × VCC V IO = −100 µA; VCC = 1.65 V to 5.5 V VCC − 0.1 - - V IO = −4 mA; VCC = 1.65 V 1.2 1.54 - V IO = −8 mA; VCC = 2.3 V 1.9 2.15 - V VI = VIH or VIL IO = −12 mA; VCC = 2.7 V 2.2 2.50 - V IO = −24 mA; VCC = 3.0 V 2.3 2.62 - V IO = −32 mA; VCC = 4.5 V 3.8 4.11 - V VI = VIH or VIL IO = 100 µA; VCC = 1.65 V to 5.5 V - - 0.10 V IO = 4 mA; VCC = 1.65 V - 0.07 0.45 V IO = 8 mA; VCC = 2.3 V - 0.12 0.30 V IO = 12 mA; VCC = 2.7 V - 0.17 0.40 V IO = 24 mA; VCC = 3.0 V - 0.33 0.55 V IO = 32 mA; VCC = 4.5 V - 0.39 0.55 V ILI input leakage current VI = 5.5 V or GND; VCC = 5.5 V - ±0.1 ±5 µA IOFF power-off leakage current VI or VO = 5.5 V; VCC = 0 V - ±0.1 ±10 µA ICC quiescent supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - 0.1 10 µA ∆ICC additional quiescent supply current (per pin) VI = VCC − 0.6 V; IO = 0 A; VCC = 2.3 V to 5.5 V - 5 500 µA Ci input capacitance - 4.0 - pF 74LVC2G74_1 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 3 November 2005 6 of 20 74LVC2G74 Philips Semiconductors Single D-type flip-flop with set and reset; positive edge trigger Table 9: Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit 0.65 × VCC - - V Tamb = −40 °C to +125 °C HIGH-state input voltage VCC = 1.65 V to 1.95 V VIH LOW-state input voltage VIL VOH HIGH-state output voltage LOW-state output voltage VOL VCC = 2.3 V to 2.7 V 1.7 - - V VCC = 2.7 V to 3.6 V 2.0 - - V VCC = 4.5 V to 5.5 V 0.7 × VCC - - V VCC = 1.65 V to 1.95 V - - 0.35 × VCC V VCC = 2.3 V to 2.7 V - - 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 V VCC = 4.5 V to 5.5 V - - 0.3 × VCC V IO = −100 µA; VCC = 1.65 V to 5.5 V VCC − 0.1 - - V IO = −4 mA; VCC = 1.65 V 0.95 - - V IO = −8 mA; VCC = 2.3 V 1.7 - - V IO = −12 mA; VCC = 2.7 V 1.9 - - V IO = −24 mA; VCC = 3.0 V 2.0 - - V IO = −32 mA; VCC = 4.5 V 3.4 - - V - - 0.10 V VI = VIH or VIL VI = VIH or VIL IO = 100 µA; VCC = 1.65 V to 5.5 V IO = 4 mA; VCC = 1.65 V - - 0.70 V IO = 8 mA; VCC = 2.3 V - - 0.45 V IO = 12 mA; VCC = 2.7 V - - 0.60 V IO = 24 mA; VCC = 3.0 V - - 0.80 V - - 0.80 V ILI input leakage current VI = 5.5 V or GND; VCC = 5.5 V IO = 32 mA; VCC = 4.5 V - - ±20 µA IOFF power-off leakage current VI or VO = 5.5 V; VCC = 0 V - - ±20 µA ICC quiescent supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 40 µA ∆ICC additional quiescent supply current (per pin) VI = VCC − 0.6 V; IO = 0 A; VCC = 2.3 V to 5.5 V - - 5000 µA [1] All typical values are measured at Tamb = 25 °C. 74LVC2G74_1 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 3 November 2005 7 of 20 74LVC2G74 Philips Semiconductors Single D-type flip-flop with set and reset; positive edge trigger 12. Dynamic characteristics Table 10: Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8. Symbol Parameter Tamb = −40 °C to +85 tPHL, tPLH Min Typ Max Unit VCC = 1.65 V to 1.95 V 1.5 6.0 13.4 ns VCC = 2.3 V to 2.7 V 1.0 3.5 7.1 ns VCC = 2.7 V 1.0 3.5 7.1 ns VCC = 3.0 V to 3.6 V 1.0 3.5 [2] 5.9 ns VCC = 4.5 V to 5.5 V 1.0 2.5 4.1 ns propagation delay CP to Q, Q SD to Q, Q RD to Q, Q tW Conditions °C [1] see Figure 6 see Figure 7 VCC = 1.65 V to 1.95 V 1.5 6.0 12.9 ns VCC = 2.3 V to 2.7 V 1.0 3.5 7.0 ns VCC = 2.7 V 1.0 3.5 7.0 ns VCC = 3.0 V to 3.6 V 1.0 3.0 [2] 5.9 ns VCC = 4.5 V to 5.5 V 1.0 2.5 4.1 ns VCC = 1.65 V to 1.95 V 1.5 5.0 12.9 ns VCC = 2.3 V to 2.7 V 1.0 3.5 7.0 ns VCC = 2.7 V 1.0 3.5 7.0 ns VCC = 3.0 V to 3.6 V 1.0 3.0 [2] 5.9 ns VCC = 4.5 V to 5.5 V 1.0 2.5 4.1 ns VCC = 1.65 V to 1.95 V 6.2 - - ns VCC = 2.3 V to 2.7 V 2.7 - - ns VCC = 2.7 V 2.7 - - ns VCC = 3.0 V to 3.6 V 2.7 1.3 [2] - ns VCC = 4.5 V to 5.5 V 2.0 - - ns 6.2 - - ns see Figure 7 pulse width clock CP HIGH or LOW set SD (LOW) and reset RD (LOW) see Figure 6 see Figure 7 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V 2.7 - - ns VCC = 2.7 V 2.7 - - ns VCC = 3.0 V to 3.6 V 2.7 1.6 [2] - ns VCC = 4.5 V to 5.5 V 2.0 - - ns 74LVC2G74_1 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 3 November 2005 8 of 20 74LVC2G74 Philips Semiconductors Single D-type flip-flop with set and reset; positive edge trigger Table 10: Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8. Symbol Parameter trec recovery time set SD or reset RD tsu Conditions Max Unit see Figure 7 VCC = 1.65 V to 1.95 V 1.9 - - ns VCC = 2.3 V to 2.7 V 1.4 - - ns VCC = 2.7 V 1.3 - - ns VCC = 3.0 V to 3.6 V 1.2 −3.0 [2] - ns VCC = 4.5 V to 5.5 V 1.0 - - ns 2.9 - - ns see Figure 6 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V 1.7 - - ns VCC = 2.7 V 1.7 - - ns VCC = 3.0 V to 3.6 V 1.3 0.5 [2] - ns VCC = 4.5 V to 5.5 V 1.1 - - ns VCC = 1.65 V to 1.95 V 0.0 - - ns VCC = 2.3 V to 2.7 V 0.3 - - ns VCC = 2.7 V 0.5 - - ns VCC = 3.0 V to 3.6 V 1.2 0.6 [2] - ns VCC = 4.5 V to 5.5 V 0.5 - - ns hold time D to CP fmax Typ setup time D to CP th Min maximum input clock frequency see Figure 6 see Figure 6 VCC = 1.65 V to 1.95 V 80 - - MHz VCC = 2.3 V to 2.7 V 175 - - MHz VCC = 2.7 V 175 - - MHz VCC = 3.0 V to 3.6 V 175 280 [2] - MHz VCC = 4.5 V to 5.5 V 200 - - MHz 74LVC2G74_1 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 3 November 2005 9 of 20 74LVC2G74 Philips Semiconductors Single D-type flip-flop with set and reset; positive edge trigger Table 10: Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8. Symbol Parameter Conditions Min Typ Max Unit VCC = 1.65 V to 1.95 V 1.5 - 13.4 ns VCC = 2.3 V to 2.7 V 1.0 - 7.1 ns VCC = 2.7 V 1.0 - 7.1 ns VCC = 3.0 V to 3.6 V 1.0 - 5.9 ns VCC = 4.5 V to 5.5 V 1.0 - 4.1 ns 1.5 - 12.9 ns Tamb = −40 °C to +125 °C tPHL, tPLH propagation delay CP to Q, Q SD to Q, Q see Figure 6 see Figure 7 VCC = 1.65 V to 1.95 V RD to Q, Q tW 1.0 - 7.0 ns VCC = 2.7 V 1.0 - 7.0 ns VCC = 3.0 V to 3.6 V 1.0 - 5.9 ns VCC = 4.5 V to 5.5 V 1.0 - 4.1 ns VCC = 1.65 V to 1.95 V 1.5 - 12.9 ns VCC = 2.3 V to 2.7 V 1.0 - 7.0 ns VCC = 2.7 V 1.0 - 7.0 ns VCC = 3.0 V to 3.6 V 1.0 - 5.9 ns VCC = 4.5 V to 5.5 V 1.0 - 4.1 ns see Figure 7 pulse width clock CP HIGH or LOW set SD (LOW) and reset RD (LOW) trec VCC = 2.3 V to 2.7 V see Figure 6 VCC = 1.65 V to 1.95 V 6.2 - - ns VCC = 2.3 V to 2.7 V 2.7 - - ns VCC = 2.7 V 2.7 - - ns VCC = 3.0 V to 3.6 V 2.7 - - ns VCC = 4.5 V to 5.5 V 2.0 - - ns VCC = 1.65 V to 1.95 V 6.2 - - ns VCC = 2.3 V to 2.7 V 2.7 - - ns VCC = 2.7 V 2.7 - - ns VCC = 3.0 V to 3.6 V 2.7 - - ns VCC = 4.5 V to 5.5 V 2.0 - - ns VCC = 1.65 V to 1.95 V 1.9 - - ns VCC = 2.3 V to 2.7 V 1.4 - - ns VCC = 2.7 V 1.3 - - ns VCC = 3.0 V to 3.6 V 1.2 - - ns VCC = 4.5 V to 5.5 V 1.0 - - ns see Figure 7 recovery time set SD or reset RD see Figure 7 74LVC2G74_1 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 3 November 2005 10 of 20 74LVC2G74 Philips Semiconductors Single D-type flip-flop with set and reset; positive edge trigger Table 10: Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8. Symbol Parameter tsu setup time D to CP Conditions Min Typ Max Unit see Figure 6 VCC = 1.65 V to 1.95 V 2.9 - - ns VCC = 2.3 V to 2.7 V 1.7 - - ns VCC = 2.7 V 1.7 - - ns VCC = 3.0 V to 3.6 V 1.3 - - ns VCC = 4.5 V to 5.5 V 1.1 - - ns 0.0 - - ns hold time th D to CP see Figure 6 VCC = 1.65 V to 1.95 V maximum input clock frequency fmax VCC = 2.3 V to 2.7 V 0.3 - - ns VCC = 2.7 V 0.5 - - ns VCC = 3.0 V to 3.6 V 1.2 - - ns VCC = 4.5 V to 5.5 V 0.5 - - ns VCC = 1.65 V to 1.95 V 80 - - MHz VCC = 2.3 V to 2.7 V 175 - - MHz VCC = 2.7 V 175 - - MHz VCC = 3.0 V to 3.6 V 175 - - MHz VCC = 4.5 V to 5.5 V 200 - - MHz see Figure 6 [1] All typical values are measured at Tamb = 25 °C. [2] These typical values are measured at VCC = 3.3 V. 74LVC2G74_1 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 3 November 2005 11 of 20 74LVC2G74 Philips Semiconductors Single D-type flip-flop with set and reset; positive edge trigger 13. Waveforms VI VM CP input GND tW 1/fmax VI VM D input GND th th t su t su t PHL t PLH VOH VM Q output VOL VOH Q output VM VOL t PLH t PHL mnb141 Measurement points are given in Table 11. The shaded areas indicate when the input is permitted to change for predictable output performance. VOL and VOH are typical output voltage drop that occur with the output load. Fig 6. The clock input (CP) to output (Q, Q) propagation delays, the clock pulse width, the D to CP set-up, the CP to D hold times and the maximum clock pulse frequency Table 11: Measurement points Supply voltage Input Output VCC VM VM 1.65 V to 1.95 V 0.5 × VCC 0.5 × VCC 2.3 V to 2.7 V 0.5 × VCC 0.5 × VCC 2.7 V 1.5 V 1.5 V 3.0 V to 3.6 V 1.5 V 1.5 V 4.5 V to 5.5 V 0.5 × VCC 0.5 × VCC 74LVC2G74_1 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 3 November 2005 12 of 20 74LVC2G74 Philips Semiconductors Single D-type flip-flop with set and reset; positive edge trigger VI VM CP input GND t rec VI VM SD input GND tW tW VI VM RD input GND t PHL t PLH VOH Q output VM VOL VOH VM Q output VOL t PHL t PLH mnb142 Measurement points are given in Table 11. VOL and VOH are typical output voltage drop that occur with the output load. Fig 7. The set (SD) and reset (RD) input to output (Q, Q) propagation delays, the set and reset pulse widths and the RD to CP removal time VEXT VCC PULSE GENERATOR VI RL VO DUT RT CL RL mna616 Test data is given in Table 12. Definitions for test circuit: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = Test voltage for switching times. Fig 8. Load circuitry for switching times 74LVC2G74_1 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 3 November 2005 13 of 20 74LVC2G74 Philips Semiconductors Single D-type flip-flop with set and reset; positive edge trigger Table 12: Test data Supply voltage Input Load VCC VI tr = tf CL RL tPLH, tPHL tPZH, tPHZ tPZL, tPLZ 1.65 V to 1.95 V VCC ≤ 2.0 ns 30 pF 1 kΩ open GND 2 × VCC 2.3 V to 2.7 V VCC ≤ 2.0 ns 30 pF 500 Ω open GND 2 × VCC 2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open GND 6V 3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open GND 6V 4.5 V to 5.5 V VCC ≤ 2.5 ns 50 pF 500 Ω open GND 2 × VCC 74LVC2G74_1 Product data sheet VEXT © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 3 November 2005 14 of 20 74LVC2G74 Philips Semiconductors Single D-type flip-flop with set and reset; positive edge trigger 14. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm D E A SOT505-2 X c HE y v M A Z 5 8 A A2 (A3) A1 pin 1 index θ Lp L 1 4 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(1) e HE L Lp v w y Z(1) θ mm 1.1 0.15 0.00 0.95 0.75 0.25 0.38 0.22 0.18 0.08 3.1 2.9 3.1 2.9 0.65 4.1 3.9 0.5 0.47 0.33 0.2 0.13 0.1 0.70 0.35 8° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT505-2 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 02-01-16 --- Fig 9. Package outline SOT505-2 (TSSOP8) 74LVC2G74_1 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 3 November 2005 15 of 20 74LVC2G74 Philips Semiconductors Single D-type flip-flop with set and reset; positive edge trigger VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm D E SOT765-1 A X c y HE v M A Z 5 8 Q A A2 A1 pin 1 index (A3) θ Lp 1 4 e L detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(2) e HE L Lp Q v w y Z(1) θ mm 1 0.15 0.00 0.85 0.60 0.12 0.27 0.17 0.23 0.08 2.1 1.9 2.4 2.2 0.5 3.2 3.0 0.4 0.40 0.15 0.21 0.19 0.2 0.13 0.1 0.4 0.1 8° 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT765-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 02-06-07 MO-187 Fig 10. Package outline SOT765-1 (VSSOP8) 74LVC2G74_1 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 3 November 2005 16 of 20 74LVC2G74 Philips Semiconductors Single D-type flip-flop with set and reset; positive edge trigger XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm 1 2 SOT833-1 b 4 3 4× (2) L L1 e 8 7 6 e1 5 e1 e1 8× A (2) A1 D E terminal 1 index area 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A (1) max A1 max b D E e e1 L L1 mm 0.5 0.04 0.25 0.17 2.0 1.9 1.05 0.95 0.6 0.5 0.35 0.27 0.40 0.32 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT833-1 --- MO-252 --- EUROPEAN PROJECTION ISSUE DATE 04-07-22 04-11-09 Fig 11. Package outline SOT833-1 (XSON8) 74LVC2G74_1 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 3 November 2005 17 of 20 74LVC2G74 Philips Semiconductors Single D-type flip-flop with set and reset; positive edge trigger 15. Abbreviations Table 13: Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor TTL Transistor Transistor Logic HBM Human Body Model ESD ElectroStatic Discharge MM Machine Model CDM Charged Device Model DUT Device Under Test 16. Revision history Table 14: Revision history Document ID Release date Data sheet status Change notice Doc. number Supersedes 74LVC2G74_1 20051103 Product data sheet - - - 74LVC2G74_1 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 3 November 2005 18 of 20 74LVC2G74 Philips Semiconductors Single D-type flip-flop with set and reset; positive edge trigger 17. Data sheet status Level Data sheet status [1] Product status [2] [3] Definition I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 18. Definitions customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Right to make changes — Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 20. Trademarks 19. Disclaimers Notice — All referenced brands, product names, service names and trademarks are the property of their respective owners. Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors 21. Contact information For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: [email protected] 74LVC2G74_1 Product data sheet © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Rev. 01 — 3 November 2005 19 of 20 74LVC2G74 Philips Semiconductors Single D-type flip-flop with set and reset; positive edge trigger 22. Contents 1 2 3 4 5 6 7 7.1 7.2 8 8.1 9 10 11 12 13 14 15 16 17 18 19 20 21 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 18 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 19 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Contact information . . . . . . . . . . . . . . . . . . . . 19 © Koninklijke Philips Electronics N.V. 2005 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 3 November 2005 Document number: 74LVC2G74_1 Published in The Netherlands