74LVC1G175 Single D-type flip-flop with reset; positive-edge trigger Rev. 01 — 18 October 2004 Product data sheet 1. General description The 74LVC1G175 is a high-performance, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using Ioff. The Ioff circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. The 74LVC1G175 is a single positive edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q output. The master reset (MR) is an asynchronous active LOW input and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock transition, for predictable operation. Schmitt-trigger action at all inputs makes the circuit highly tolerant to slower input rise and fall times. 2. Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant inputs for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: ◆ JESD8-7 (1.65 V to 1.95 V) ◆ JESD8-5 (2.3 V to 2.7 V) ◆ JESD8B/JESD36 (2.7 V to 3.6 V). ±24 mA output drive (VCC = 3.0 V) ESD protection: ◆ HBM EIA/JESD22-A114-B exceeds 2000 V ◆ MM EIA/JESD22-A115-A exceeds 200 V. CMOS low power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels Inputs accept voltages up to 5 V Multiple package options Specified from −40 °C to +85 °C and −40 °C to +125 °C. 74LVC1G175 Philips Semiconductors Single D-type flip-flop with reset; positive-edge trigger 3. Quick reference data Table 1: Quick reference data GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns. Symbol Parameter Conditions Min Typ Max Unit tPHL, tPLH propagation delay CP to Q CL = 50 pF; VCC = 3.3 V 1.0 3.1 5.7 ns propagation delay MR to Q CL = 50 pF; VCC = 3.3 V 1.0 2.5 5.8 ns fmax maximum clock frequency CL = 50 pF; VCC = 3.3 V 175 300 - MHz CI input capacitance - 2.5 - pF - 14 - pF power dissipation capacitance CPD VCC = 3.3 V [1] [2] [1] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of the outputs. [2] The condition is VI = GND to VCC. 4. Ordering information Table 2: Ordering information Type number Package Temperature range Name Description Version 74LVC1G175GW −40 °C to +125 °C SC-88 plastic surface mounted package; 6 leads SOT363 74LVC1G175GV −40 °C to +125 °C SC-74 plastic surface mounted package; 6 leads SOT457 74LVC1G175GM −40 °C to +125 °C XSON6 plastic extremely thin small outline package; no leads; 6 terminals; body 1 × 1.45 × 0.5 mm SOT886 5. Functional diagram 6 1 3 MR D FF 1 3 Q 4 6 C1 4 1D R CP 001aaa469 001aaa468 Fig 1. Logic symbol. 9397 750 13762 Product data sheet Fig 2. IEC logic symbol. © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 01 — 18 October 2004 2 of 17 74LVC1G175 Philips Semiconductors Single D-type flip-flop with reset; positive-edge trigger CP Q C C C C C C C C D C C MR 001aaa466 Fig 3. Logic diagram. 6. Pinning information 6.1 Pinning 175 CP 1 GND 2 D 3 175 6 MR 5 VCC 4 Q CP 1 6 MR GND 2 5 VCC D 3 4 Q 001aaa467 001aab657 Transparent top view Fig 4. Pin configuration SC-88 and SC-74. Fig 5. Pin configuration XSON6. 6.2 Pin description Table 3: Pin description Symbol Pin Description CP 1 clock input (LOW-to-HIGH, edge-triggered) GND 2 ground (0 V) D 3 data input Q 4 flip-flop output VCC 5 supply voltage MR 6 master reset input (active LOW) 9397 750 13762 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 01 — 18 October 2004 3 of 17 74LVC1G175 Philips Semiconductors Single D-type flip-flop with reset; positive-edge trigger 7. Functional description 7.1 Function table Table 4: Function table [1] Operating mode Input Output MR CP D Q Reset (clear) L X X L Load ‘1’ H ↑ h H Load ‘0’ H ↑ l L [1] H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition; ↑ = LOW-to-HIGH CP transition; X = don’t care. 8. Limiting values Table 5: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions VCC supply voltage IIK input diode current VI input voltage IOK output diode current output voltage VO VI < 0 V [1] Min Max Unit −0.5 +6.5 V - −50 mA −0.5 +6.5 V mA - ±50 active mode [1] [2] −0.5 VCC + 0.5 V Power-down mode [1] [2] −0.5 +6.5 V - ±50 mA VO > VCC or VO < 0 V IO output diode current VO = 0 V to VCC ICC, IGND VCC or GND current - ±100 mA Tstg storage temperature −65 +150 °C Ptot power dissipation - 250 mW Tamb = −40 °C to +125 °C [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation. 9. Recommended operating conditions Table 6: Recommended operating conditions Symbol Parameter Min Max Unit VCC supply voltage Conditions 1.65 5.5 V VI input voltage 0 5.5 V VO output voltage active mode 0 VCC V Power-down mode; VCC = 0 V 0 5.5 V 9397 750 13762 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 01 — 18 October 2004 4 of 17 74LVC1G175 Philips Semiconductors Single D-type flip-flop with reset; positive-edge trigger Table 6: Recommended operating conditions …continued Symbol Parameter Tamb ambient temperature tr, tf input rise and fall times Conditions Min Max Unit −40 +125 °C VCC = 1.65 V to 2.7 V 0 20 ns/V VCC = 2.7 V to 5.5 V 0 10 ns/V 10. Static characteristics Table 7: Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = −40 °C to +85 VIH VIL VOH VOL Conditions Min Typ Max Unit 0.65 × VCC - - V °C [1] HIGH-level input voltage VCC = 1.65 V to 1.95 V LOW-level input voltage HIGH-level output voltage LOW-level output voltage VCC = 2.3 V to 2.7 V 1.7 - - V VCC = 2.7 V to 3.6 V 2.0 - - V VCC = 4.5 V to 5.5 V 0.7 × VCC - - V VCC = 1.65 V to 1.95 V - - 0.35 × VCC V VCC = 2.3 V to 2.7 V - - 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 V VCC = 4.5 V to 5.5 V - - 0.3 × VCC V IO = −100 µA; VCC = 1.65 V to 5.5 V VCC − 0.1 - - V IO = −4 mA; VCC = 1.65 V 1.2 1.54 - V IO = −8 mA; VCC = 2.3 V 1.9 2.15 - V IO = −12 mA; VCC = 2.7 V 2.2 2.50 - V IO = −24 mA; VCC = 3.0 V 2.3 2.62 - V IO = −32 mA; VCC = 4.5 V 3.8 4.11 - V - - 0.10 V VI = VIH or VIL VI = VIH or VIL IO = 100 µA; VCC = 1.65 V to 5.5 V IO = 4 mA; VCC = 1.65 V - 0.07 0.45 V IO = 8 mA; VCC = 2.3 V - 0.12 0.30 V IO = 12 mA; VCC = 2.7 V - 0.17 0.40 V IO = 24 mA; VCC = 3.0 V - 0.33 0.55 V - 0.39 0.55 V ILI input leakage current VI = 5.5 V or GND; VCC = 5.5 V IO = 32 mA; VCC = 4.5 V - ±0.1 ±5 µA Ioff power OFF leakage current VI or VO = 5.5 V; VCC = 0 V - ±0.1 ±10 µA ICC quiescent supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - 0.1 10 µA ∆ICC additional quiescent supply current per pin VI = VCC − 0.6 V; IO = 0 A; VCC = 2.3 V to 5.5 V - 5 500 µA CI input capacitance - 2.5 - pF 9397 750 13762 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 01 — 18 October 2004 5 of 17 74LVC1G175 Philips Semiconductors Single D-type flip-flop with reset; positive-edge trigger Table 7: Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit 0.65 × VCC - - V Tamb = −40 °C to +125 °C HIGH-level input voltage VCC = 1.65 V to 1.95 V VIH LOW-level input voltage VIL VOH HIGH-level output voltage LOW-level output voltage VOL VCC = 2.3 V to 2.7 V 1.7 - - V VCC = 2.7 V to 3.6 V 2.0 - - V VCC = 4.5 V to 5.5 V 0.7 × VCC - - V VCC = 1.65 V to 1.95 V - - 0.35 × VCC V VCC = 2.3 V to 2.7 V - - 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 V VCC = 4.5 V to 5.5 V - - 0.3 × VCC V IO = −100 µA; VCC = 1.65 V to 5.5 V VCC − 0.1 - - V IO = −4 mA; VCC = 1.65 V 0.95 - - V IO = −8 mA; VCC = 2.3 V 1.7 - - V IO = −12 mA; VCC = 2.7 V 1.9 - - V IO = −24 mA; VCC = 3.0 V 2.0 - - V IO = −32 mA; VCC = 4.5 V 3.4 - - V - - 0.10 V VI = VIH or VIL VI = VIH or VIL IO = 100 µA; VCC = 1.65 V to 5.5 V IO = 4 mA; VCC = 1.65 V - - 0.70 V IO = 8 mA; VCC = 2.3 V - - 0.45 V IO = 12 mA; VCC = 2.7 V - - 0.60 V IO = 24 mA; VCC = 3.0 V - - 0.80 V - - 0.80 V ILI input leakage current VI = 5.5 V or GND; VCC = 5.5 V IO = 32 mA; VCC = 4.5 V - - ±20 µA Ioff power OFF leakage current VI or VO = 5.5 V; VCC = 0 V - - ±20 µA ICC quiescent supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 40 µA ∆ICC additional quiescent supply current per pin VI = VCC − 0.6 V; IO = 0 A; VCC = 2.3 V to 5.5 V - - 5000 µA [1] All typical values are measured at Tamb = 25 °C. 9397 750 13762 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 01 — 18 October 2004 6 of 17 74LVC1G175 Philips Semiconductors Single D-type flip-flop with reset; positive-edge trigger 11. Dynamic characteristics Table 8: Dynamic characteristics GND = 0 V; see Figure 8 Symbol Parameter Tamb = −40 °C to +85 tPHL, tPLH Conditions Min Typ Max Unit VCC = 1.65 V to 1.95 V 1.5 4.9 13.4 ns VCC = 2.3 V to 2.7 V 1.0 3.1 7.1 ns 1.0 3.2 7.1 ns 1.0 3.1 5.7 ns 1.0 2.2 4.0 ns 1.5 4.3 12.9 ns VCC = 2.3 V to 2.7 V 1.0 2.8 7.0 ns VCC = 2.7 V 1.0 3.0 7.0 ns 1.0 2.5 5.8 ns 1.0 2.0 4.1 ns VCC = 1.65 V to 1.95 V 6.2 - - ns VCC = 2.3 V to 2.7 V 2.7 - - ns 2.7 - - ns 2.7 1.3 - ns 2.0 - - ns 6.2 - - ns VCC = 2.3 V to 2.7 V 2.7 - - ns VCC = 2.7 V 2.7 - - ns 2.7 1.6 - ns 2.0 - - ns VCC = 1.65 V to 1.95 V 1.9 - - ns VCC = 2.3 V to 2.7 V 1.4 - - ns 1.3 - - ns 1.2 0.4 - ns 1.0 - - ns 2.9 - - ns VCC = 2.3 V to 2.7 V 1.7 - - ns VCC = 2.7 V 1.7 - - ns 1.3 0.5 - ns 1.1 - - ns °C [1] propagation delay CP to Q see Figure 6 VCC = 2.7 V VCC = 3.0 V to 3.6 V [2] VCC = 4.5 V to 5.5 V propagation delay MR to Q see Figure 7 VCC = 1.65 V to 1.95 V VCC = 3.0 V to 3.6 V [2] VCC = 4.5 V to 5.5 V tW clock pulse width HIGH or LOW see Figure 6 VCC = 2.7 V VCC = 3.0 V to 3.6 V [2] VCC = 4.5 V to 5.5 V master reset pulse width LOW see Figure 7 VCC = 1.65 V to 1.95 V VCC = 3.0 V to 3.6 V [2] VCC = 4.5 V to 5.5 V trem removal time master reset see Figure 7 VCC = 2.7 V VCC = 3.0 V to 3.6 V [2] VCC = 4.5 V to 5.5 V tsu set-up time D to CP see Figure 6 VCC = 1.65 V to 1.95 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V 9397 750 13762 Product data sheet [2] © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 01 — 18 October 2004 7 of 17 74LVC1G175 Philips Semiconductors Single D-type flip-flop with reset; positive-edge trigger Table 8: Dynamic characteristics …continued GND = 0 V; see Figure 8 Symbol Parameter Conditions Min Typ Max Unit th hold time D to CP see Figure 6 0.0 - - ns VCC = 2.3 V to 2.7 V 0.3 - - ns VCC = 2.7 V 0.5 - - ns 1.2 0.2 - ns 0.5 - - ns VCC = 1.65 V to 1.95 V 80 125 - MHz VCC = 2.3 V to 2.7 V 175 - - MHz 175 - - MHz 175 300 - MHz 200 - - MHz - 14 - pF VCC = 1.65 V to 1.95 V 1.5 - 17 ns VCC = 2.3 V to 2.7 V 1.0 - 9.0 ns VCC = 2.7 V 1.0 - 9.0 ns VCC = 3.0 V to 3.6 V 0.5 - 7.5 ns VCC = 4.5 V to 5.5 V 0.5 - 5.5 ns VCC = 1.65 V to 1.95 V VCC = 3.0 V to 3.6 V [2] VCC = 4.5 V to 5.5 V fmax maximum clock pulse frequency see Figure 6 VCC = 2.7 V VCC = 3.0 V to 3.6 V [2] VCC = 4.5 V to 5.5 V CPD power dissipation capacitance VCC = 3.3 V [3] [4] Tamb = −40 °C to +125 °C tPHL, tPLH propagation delay CP to Q propagation delay MR to Q tW clock pulse width HIGH or LOW master reset pulse width LOW see Figure 6 see Figure 7 VCC = 1.65 V to 1.95 V 1.5 - 17 ns VCC = 2.3 V to 2.7 V 1.0 - 9.0 ns VCC = 2.7 V 1.0 - 9.0 ns VCC = 3.0 V to 3.6 V 0.5 - 7.5 ns VCC = 4.5 V to 5.5 V 0.5 - 5.5 ns VCC = 1.65 V to 1.95 V 6.2 - - ns VCC = 2.3 V to 2.7 V 2.7 - - ns VCC = 2.7 V 2.7 - - ns VCC = 3.0 V to 3.6 V 2.7 - - ns VCC = 4.5 V to 5.5 V 2.0 - - ns see Figure 6 see Figure 7 VCC = 1.65 V to 1.95 V 6.2 - - ns VCC = 2.3 V to 2.7 V 2.7 - - ns VCC = 2.7 V 2.7 - - ns VCC = 3.0 V to 3.6 V 2.7 - - ns VCC = 4.5 V to 5.5 V 2.0 - - ns 9397 750 13762 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 01 — 18 October 2004 8 of 17 74LVC1G175 Philips Semiconductors Single D-type flip-flop with reset; positive-edge trigger Table 8: Dynamic characteristics …continued GND = 0 V; see Figure 8 Symbol Parameter Conditions Min Typ Max Unit trem removal time master reset see Figure 7 1.9 - - ns VCC = 2.3 V to 2.7 V 1.4 - - ns VCC = 2.7 V 1.3 - - ns VCC = 3.0 V to 3.6 V 1.2 - - ns VCC = 4.5 V to 5.5 V 1.0 - - ns VCC = 1.65 V to 1.95 V 2.9 - - ns VCC = 2.3 V to 2.7 V 1.7 - - ns VCC = 2.7 V 1.7 - - ns VCC = 3.0 V to 3.6 V 1.3 - - ns VCC = 4.5 V to 5.5 V 1.1 - - ns 0.0 - - ns VCC = 2.3 V to 2.7 V 0.3 - - ns VCC = 2.7 V 0.5 - - ns VCC = 3.0 V to 3.6 V 1.2 - - ns VCC = 4.5 V to 5.5 V 0.5 - - ns VCC = 1.65 V to 1.95 V 80 - - MHz VCC = 2.3 V to 2.7 V 175 - - MHz VCC = 2.7 V 175 - - MHz VCC = 3.0 V to 3.6 V 175 - - MHz VCC = 4.5 V to 5.5 V 200 - - MHz VCC = 1.65 V to 1.95 V set-up time D to CP tsu hold time D to CP th see Figure 6 see Figure 6 VCC = 1.65 V to 1.95 V maximum clock pulse frequency fmax [1] see Figure 6 All typical values are measured at Tamb = 25 °C. [2] These typical values are measured at VCC = 3.3 V. [3] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of the outputs. [4] The condition is VI = GND to VCC. 9397 750 13762 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 01 — 18 October 2004 9 of 17 74LVC1G175 Philips Semiconductors Single D-type flip-flop with reset; positive-edge trigger 12. Waveforms VI VM D input GND th th tsu tsu 1/fmax VI CP input VM GND tW tPHL tPLH VOH VM Q output VOL 001aaa465 Measurement points are given in Table 9. The shaded areas indicate when the input is permitted to change for predictable output performance. VOL and VOH are typical output voltage drop that occur with the output load. Fig 6. The clock input (CP) to output (Q) propagation delays, the clock pulse width, the D to CP set-up, the CP to D hold times and the maximum clock pulse frequency. Table 9: Measurement points Supply voltage Output Input VCC VM VM VI tr = tf 1.65 V to 1.95 V 0.5 × VCC 0.5 × VCC VCC ≤ 2.0 ns 2.3 V to 2.7 V 0.5 × VCC 0.5 × VCC VCC ≤ 2.0 ns 2.7 V 1.5 V 1.5 V 2.7 V ≤ 2.5 ns 3.0 V to 3.6 V 1.5 V 1.5 V 2.7 V ≤ 2.5 ns 4.5 V to 5.5 V 0.5 × VCC 0.5 × VCC VCC ≤ 2.5 ns 9397 750 13762 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 01 — 18 October 2004 10 of 17 74LVC1G175 Philips Semiconductors Single D-type flip-flop with reset; positive-edge trigger VI VM MR input GND tW t rem VI CP input VM GND t PHL VOH VM Q output VOL 001aaa464 Measurement points are given in Table 9. VOL and VOH are typical output voltage drop that occur with the output load. Fig 7. The master reset (MR) input to output (Q) propagation delays, the master reset pulse width and the MR to CP removal time. VEXT VCC PULSE GENERATOR VI RL VO D.U.T. CL RT RL mna616 Test data is given in Table 10. Definitions for test circuit: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. Fig 8. Load circuitry for switching times. Table 10: Test data Supply voltage Input Load VEXT VCC VI CL RL tPLH, tPHL tPZH, tPHZ tPZL, tPLZ 1.65 V to 1.95 V VCC 30 pF 1 kΩ open GND 2 × VCC 2.3 V to 2.7 V VCC 30 pF 500 Ω open GND 2 × VCC 2.7 V 2.7 V 50 pF 500 Ω open GND 6V 3.0 V to 3.6 V 2.7 V 50 pF 500 Ω open GND 6V 4.5 V to 5.5 V VCC 50 pF 500 Ω open GND 2 × VCC 9397 750 13762 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 01 — 18 October 2004 11 of 17 74LVC1G175 Philips Semiconductors Single D-type flip-flop with reset; positive-edge trigger 13. Package outline Plastic surface mounted package; 6 leads SOT363 D E B y X A HE 6 5 v M A 4 Q pin 1 index A A1 1 2 e1 3 c bp Lp w M B e detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 max bp c D E e e1 HE Lp Q v w y mm 1.1 0.8 0.1 0.30 0.20 0.25 0.10 2.2 1.8 1.35 1.15 1.3 0.65 2.2 2.0 0.45 0.15 0.25 0.15 0.2 0.2 0.1 OUTLINE VERSION REFERENCES IEC SOT363 JEDEC EIAJ SC-88 EUROPEAN PROJECTION ISSUE DATE 97-02-28 Fig 9. Package outline SOT363 (SC-88). 9397 750 13762 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 01 — 18 October 2004 12 of 17 74LVC1G175 Philips Semiconductors Single D-type flip-flop with reset; positive-edge trigger Plastic surface mounted package; 6 leads SOT457 D E B y A HE 6 5 X v M A 4 Q pin 1 index A A1 c 1 2 3 Lp bp e w M B detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 bp c D E e HE Lp Q v w y mm 1.1 0.9 0.1 0.013 0.40 0.25 0.26 0.10 3.1 2.7 1.7 1.3 0.95 3.0 2.5 0.6 0.2 0.33 0.23 0.2 0.2 0.1 OUTLINE VERSION REFERENCES IEC JEDEC SOT457 EIAJ SC-74 EUROPEAN PROJECTION ISSUE DATE 97-02-28 01-05-04 Fig 10. Package outline SOT457 (SC-74). 9397 750 13762 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 01 — 18 October 2004 13 of 17 74LVC1G175 Philips Semiconductors Single D-type flip-flop with reset; positive-edge trigger XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm SOT886 b 1 2 3 4× (2) L L1 e 6 5 e1 4 e1 6× A (2) A1 D E terminal 1 index area 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A (1) max A1 max b D E e e1 L L1 mm 0.5 0.04 0.25 0.17 1.5 1.4 1.05 0.95 0.6 0.5 0.35 0.27 0.40 0.32 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION SOT886 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 04-07-15 04-07-22 MO-252 Fig 11. Package outline SOT886 (XSON6). 9397 750 13762 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 01 — 18 October 2004 14 of 17 74LVC1G175 Philips Semiconductors Single D-type flip-flop with reset; positive-edge trigger 14. Revision history Table 11: Revision history Document ID Release date Data sheet status Change notice Doc. number Supersedes 74LVC1G175_2 20041018 Product data sheet - 9397 750 13762 74LVC1G175_1 9397 750 12973 - Modifications 74LVC1G175_1 • Package outline. Marking code and ESD data added. 20040318 Product data sheet - 9397 750 13762 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 01 — 18 October 2004 15 of 17 74LVC1G175 Philips Semiconductors Single D-type flip-flop with reset; positive-edge trigger 15. Data sheet status Level Data sheet status [1] Product status [2] [3] Definition I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 16. Definitions 17. Disclaimers Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Right to make changes — Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 18. Contact information For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: [email protected] 9397 750 13762 Product data sheet © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Rev. 01 — 18 October 2004 16 of 17 74LVC1G175 Philips Semiconductors Single D-type flip-flop with reset; positive-edge trigger 19. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 8 9 10 11 12 13 14 15 16 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 16 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Contact information . . . . . . . . . . . . . . . . . . . . 16 © Koninklijke Philips Electronics N.V. 2004 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 18 October 2004 Document number: 9397 750 13762 Published in The Netherlands