74LVC595A 8-bit serial-in/serial-out or parallel-out shift register; 3-state Rev. 01 — 29 May 2007 Product data sheet 1. General description The 74LVC595A is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. Data is shifted on the positive-going transitions of the SHCP input. The data in the shift register is transferred to the storage register on a positive-going transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. The shift register has a serial input (DS) and a serial output (Q7S) for cascading purposes. It is also provided with asynchronous reset input MR (active LOW) for all 8 shift register stages. The storage register has 8 parallel 3-state bus driver outputs. Data in the storage register appears at the output whenever the output enable input (OE) is LOW. 2. Features ■ ■ ■ ■ ■ ■ ■ ■ 5 V tolerant inputs/outputs for interfacing with 5 V logic Wide supply voltage range from 1.2 V to 3.6 V CMOS low-power consumption Direct interface with TTL levels Balanced propagation delays All inputs have Schmitt-trigger action Complies with JEDEC standard JESD8-B/JESD36 ESD protection: ◆ HBM JESD22-A114-D exceeds 2000 V ◆ CDM JESD22-C101-C exceeds 1000 V ■ Specified from −40 °C to +85 °C and −40 °C to +125 °C. 3. Applications ■ Serial-to-parallel data conversion ■ Remote control holding register 74LVC595A NXP Semiconductors 8-bit serial-in/serial-out or parallel-out shift register; 3-state 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC595AD −40 °C to +125 °C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 74LVC595APW −40 °C to +125 °C TSSOP16 plastic thin shrink small outline package; 16 leads; SOT403-1 body width 4.4 mm 74LVC595ABQ −40 °C to +125 °C DHVQFN16 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 × 3.5 × 0.85 mm SOT763-1 5. Functional diagram 11 12 SHCP STCP Q 7S Q0 Q1 Q2 14 Q3 DS Q4 Q5 Q6 Q7 MR 10 Fig 1. Logic symbol 9 15 1 14 DS 11 SHCP 10 MR Q7S 2 3 12 STCP 4 8-BIT STORAGE REGISTER 6 7 13 OE 3-STATE OUTPUTS Q 0 Q 1 Q 2 Q3 Q4 Q5 Q6 Q 7 15 1 mna552 2 3 4 5 6 7 mna554 Fig 2. Functional diagram 74LVC595A_1 Product data sheet 9 5 OE 13 8-STAGE SHIFT REGISTER © NXP B.V. 2007. All rights reserved. Rev. 01 — 29 May 2007 2 of 19 74LVC595A NXP Semiconductors 8-bit serial-in/serial-out or parallel-out shift register; 3-state STAGE 0 DS D Q STAGES 1 TO 6 D STAGE 7 Q D FF7 FF0 CP Q 7S Q CP R R SHCP MR D Q D Q LATCH LATCH CP CP STCP OE mna555 Q0 Q 1 Q2 Q3 Q4 Q5 Q6 Q7 Fig 3. Logic diagram SHCP DS STCP MR OE Z-state Q0 Z-state Q1 Z-state Q6 Z-state Q7 Q7 S mna556 Fig 4. Timing diagram 74LVC595A_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 29 May 2007 3 of 19 74LVC595A NXP Semiconductors 8-bit serial-in/serial-out or parallel-out shift register; 3-state 6. Pinning information 6.1 Pinning 1 terminal 1 index area 74LVC595A 16 VCC Q1 74LVC595A Q2 2 15 Q0 3 14 DS 2 15 Q0 Q4 4 13 OE Q3 3 14 DS Q5 5 12 STCP Q4 4 13 OE Q6 6 11 SHCP Q5 5 12 STCP Q7 7 10 MR Q6 6 11 SHCP Q7 7 10 MR GND 8 9 Q7S 9 Q2 Q7S 16 VCC 8 1 GND Q1 Q3 001aaf570 Transparent top view 001aaf569 Fig 5. Pin configuration SO16 and TSSOP16 Fig 6. Pin configuration DHVQFN16 6.2 Pin description Table 2. Pin description Symbol Pin Description Q[0:7] 15, 1, 2, 3, 4, 5, 6, 7 parallel data output GND 8 ground (0 V) Q7S 9 serial data output MR 10 master reset (active LOW) SHCP 11 shift register clock input STCP 12 storage register clock input OE 13 output enable input (active LOW) DS 14 serial data input VCC 16 supply voltage 74LVC595A_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 29 May 2007 4 of 19 74LVC595A NXP Semiconductors 8-bit serial-in/serial-out or parallel-out shift register; 3-state 7. Functional description Function table[1] Table 3. Input Output Function SHCP STCP OE MR DS Q7S Qn X L X L NC X L a LOW-state on MR only affects the shift register X ↑ L L X L L empty shift register loaded into storage register X X H L X L Z shift register clear; parallel outputs in high impedance OFF-state ↑ X L H H Q6S NC logic HIGH-state shifted into shift register stage 0. Contents of all shift register stages shifted through, e.g. previous state of stage 6 (internal Q6S) appears on the serial output (Q7S). X ↑ L H X NC QnS contents of shift register stages (internal QnS) are transferred to the storage register and parallel output stages ↑ ↑ L H X Q6S QnS contents of shift register shifted through; previous contents of the shift register is transferred to the storage register and the parallel output stages [1] H = HIGH voltage state; L = LOW voltage state; ↑ = LOW-to-HIGH transition; X = don’t care; NC = no change; Z = high-impedance OFF-state. 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current output voltage VO Conditions VI < 0 V [1] Min Max Unit −0.5 +6.5 V −50 - mA −0.5 +6.5 V - ±50 mA 3-state [1] −0.5 6.5 V output HIGH or LOW state [1] −0.5 VCC + 0.5 V - ±50 mA VO > VCC or VO < 0 V IO output current VO = 0 V to VCC ICC supply current - 100 mA IGND ground current −100 - mA Tstg storage temperature −65 +150 °C Ptot total power dissipation - 500 mW Tamb = −40 °C to +125 °C [2] [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For SO16 packages: above 70 °C the value of Ptot derates linearly with 8 mW/K. For TSSOP16 packages: above 60 °C the value of Ptot derates linearly with 5.5 mW/K. For DHVQFN16 packages: above 60 °C the value of Ptot derates linearly with 4.5 mW/K. 74LVC595A_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 29 May 2007 5 of 19 74LVC595A NXP Semiconductors 8-bit serial-in/serial-out or parallel-out shift register; 3-state 9. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VCC supply voltage Conditions functional VI input voltage VO output voltage Tamb ambient temperature ∆t/∆V input transition rise and fall rate Min Typ Max Unit 1.65 - 3.6 V 1.2 - - V 0 - 5.5 V 3-state 0 - 5.5 V output HIGH or LOW state 0 - VCC V −40 - +125 °C VCC = 1.65 V to 2.7 V 0 - 20 ns/V VCC = 2.7 V to 3.6 V 0 - 10 ns/V 10. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output voltage −40 °C to +85 °C Conditions VCC = 1.2 V II LOW-level output voltage Min Max Max 1.08 - - 1.08 - V - - 0.65 × VCC - V VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V 0.12 V VCC = 1.2 V - - 0.12 - VCC = 1.65 V to 1.95 V - - 0.35 × VCC - VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V VCC − 0.2 - - VCC − 0.3 - V 1.2 - - 1.05 - V 0.35 × VCC V VI = VIH or VIL IO = −100 µA; VCC = 1.65 V to 3.6 V IO = −8 mA; VCC = 2.3 V 1.8 - - 1.65 - V IO = −12 mA; VCC = 2.7 V 2.2 - - 2.05 - V IO = −18 mA; VCC = 3.0 V 2.4 - - 2.25 - V IO = −24 mA; VCC = 3.0 V 2.2 - - 2.0 - V IO = 100 µA; VCC = 1.65 V to 3.6 V - - 0.2 - 0.3 V IO = 4 mA; VCC = 1.65 V - - 0.45 - 0.65 V VI = VIH or VIL IO = 8 mA; VCC = 2.3 V - - 0.6 - 0.8 V IO = 12 mA; VCC = 2.7 V - - 0.4 - 0.6 V IO = 24 mA; VCC = 3.0 V - - 0.55 - 0.8 V - ±0.1 ±5 - ±20 µA input leakage VCC = 3.6 V; current VI = 5.5 V or GND 74LVC595A_1 Product data sheet Min Unit 0.65 × VCC VCC = 1.65 V to 1.95 V IO = −4 mA; VCC = 1.65 V VOL −40 °C to +125 °C Typ[1] © NXP B.V. 2007. All rights reserved. Rev. 01 — 29 May 2007 6 of 19 74LVC595A NXP Semiconductors 8-bit serial-in/serial-out or parallel-out shift register; 3-state Table 6. Static characteristics …continued At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter −40 °C to +85 °C Conditions [2] −40 °C to +125 °C Unit Min Typ[1] Max Min Max - 0.1 ±10 - ±20 µA IOZ OFF-state output current VI = VIH or VIL; VO = 5.5 V or GND; VCC = 3.6 V IOFF power-off leakage current VCC = 0 V; VI or VO = 5.5 V - 0.1 10 - 20 µA ICC supply current VCC = 3.6 V; VI = VCC or GND; IO = 0 A - 0.1 10 - 40 µA ∆ICC additional supply current per input pin; VCC = 1.65 V to 3.6 V; VI = VCC − 0.6 V; IO = 0 A - 5 500 - 5000 µA CI input capacitance VCC = 0 V to 3.6 V; VI = GND to VCC - 5.0 - - - pF [1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 °C. [2] For transceivers, the parameter IOZ includes the input leaking current. 11. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 13. Symbol Parameter tpd −40 °C to +85 °C Conditions Min Max Min Max - 17.5 - - - ns VCC = 1.65 V to 1.95 V 2.0 6.6 15.8 2.0 18.2 ns VCC = 2.3 V to 2.7 V 1.5 4.2 8.1 1.5 9.3 ns VCC = 2.7 V 1.5 4.7 7.6 1.5 8.7 ns VCC = 3.0 V to 3.6 V 1.5 4.0 6.7 1.5 7.7 ns - 16.8 - - - ns VCC = 1.65 V to 1.95 V 2.0 5.8 15.8 2.0 18.2 ns VCC = 2.3 V to 2.7 V 1.5 3.7 8.1 1.5 9.3 ns VCC = 2.7 V 1.5 4.0 7.6 1.5 8.7 ns VCC = 3.0 V to 3.6 V 1.2 3.3 6.7 1.2 7.7 ns - 17.3 - - - ns VCC = 1.65 V to 1.95 V 2.0 6.9 15.8 2.0 18.2 ns VCC = 2.3 V to 2.7 V 1.5 4.3 8.1 1.5 9.3 ns VCC = 2.7 V 1.5 4.5 7.6 1.5 8.7 ns VCC = 3.0 V to 3.6 V 1.2 3.8 6.7 1.2 7.7 ns propagation delay SHCP to Q7S; see Figure 7 STCP to Qn; see Figure 8 VCC = 1.2 V HIGH to LOW MR to Q7S; see Figure 11 propagation delay VCC = 1.2 V [2] 74LVC595A_1 Product data sheet Unit [2] VCC = 1.2 V tPHL −40 °C to +125 °C Typ[1] © NXP B.V. 2007. All rights reserved. Rev. 01 — 29 May 2007 7 of 19 74LVC595A NXP Semiconductors 8-bit serial-in/serial-out or parallel-out shift register; 3-state Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 13. Symbol Parameter ten enable time −40 °C to +85 °C Conditions OE to Qn; see Figure 12 Max - 17.9 - - - ns 6.4 14.1 2.0 16.2 ns VCC = 2.3 V to 2.7 V 1.5 4.2 8.0 1.5 9.2 ns VCC = 2.7 V 1.5 4.5 7.6 1.5 8.7 ns 1.2 3.8 6.7 1.2 7.7 ns - 9.6 - - - ns 2.0 4.9 9.8 2.0 11.2 ns OE to Qn; see Figure 12 VCC = 1.65 V to 1.95 V pulse width Min 2.0 VCC = 1.2 V tW Max Unit VCC = 1.65 V to 1.95 V VCC = 3.0 V to 3.6 V disable time −40 °C to +125 °C [3] VCC = 1.2 V tdis Min Typ[1] [4] VCC = 2.3 V to 2.7 V 1.2 2.8 5.8 1.2 6.6 ns VCC = 2.7 V 1.5 3.7 6.2 1.5 7.1 ns VCC = 3.0 V to 3.6 V 1.2 3.5 5.7 1.2 6.5 ns VCC = 1.65 V to 1.95 V 6.0 2.5 - 7.0 - ns VCC = 2.3 V to 2.7 V 5.0 2.0 - 5.5 - ns VCC = 2.7 V 4.5 1.5 - 5.0 - ns VCC = 3.0 V to 3.6 V 4.0 1.5 - 4.5 - ns VCC = 1.65 V to 1.95 V 5.0 2.0 - 5.5 - ns VCC = 2.3 V to 2.7 V 4.0 1.5 - 4.5 - ns VCC = 2.7 V 2.5 1.0 - 3.0 - ns VCC = 3.0 V to 3.6 V 2.5 1.0 - 3.0 - ns 5.0 0.4 - 5.5 - ns VCC = 2.3 V to 2.7 V 4.0 0.1 - 4.5 - ns VCC = 2.7 V 2.0 0 - 2.5 - ns VCC = 3.0 V to 3.6 V 2.0 −0.1 - 2.5 - ns SHCP, STCP HIGH or LOW; see Figure 7 and Figure 8 MR LOW; see Figure 11 tsu set-up time DS to SHCP; see Figure 9 VCC = 1.65 V to 1.95 V MR to STCP; see Figure 10 VCC = 1.65 V to 1.95 V 8.0 3.5 - 8.5 - ns VCC = 2.3 V to 2.7 V 5.0 2.1 - 5.5 - ns VCC = 2.7 V 4.0 1.8 - 4.5 - ns VCC = 3.0 V to 3.6 V 4.0 1.7 - 4.5 - ns VCC = 1.65 V to 1.95 V 8.0 3.5 - 8.5 - ns VCC = 2.3 V to 2.7 V 5.0 2.1 - 5.5 - ns VCC = 2.7 V 4.0 1.8 - 4.5 - ns VCC = 3.0 V to 3.6 V 4.0 1.7 - 4.5 - ns SHCP to STCP; see Figure 8 74LVC595A_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 29 May 2007 8 of 19 74LVC595A NXP Semiconductors 8-bit serial-in/serial-out or parallel-out shift register; 3-state Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 13. Symbol Parameter th hold time recovery time trec maximum frequency fmax −40 °C to +85 °C Conditions output skew time power dissipation capacitance CPD Min Max Min Max VCC = 1.65 V to 1.95 V 1.5 0.2 - 2.0 - ns VCC = 2.3 V to 2.7 V 1.5 0.1 - 2.0 - ns VCC = 2.7 V 1.5 −0.1 - 2.0 - ns VCC = 3.0 V to 3.6 V 1.0 −0.2 - 1.5 - ns VCC = 1.65 V to 1.95 V 5.0 −2.7 - 5.5 - ns VCC = 2.3 V to 2.7 V 4.0 −1.5 - 4.5 - ns VCC = 2.7 V 2.0 −1.0 - 2.5 - ns VCC = 3.0 V to 3.6 V 2.0 −1.0 - 2.5 - ns VCC = 1.65 V to 1.95 V 80 130 - 70 - MHz VCC = 2.3 V to 2.7 V 100 140 - 90 - MHz VCC = 2.7 V 110 150 - 100 - MHz 130 180 - 115 - MHz - - 1.0 - 1.5 ns VCC = 1.65 V to 1.95 V - 50 - - - pF VCC = 2.3 V to 2.7 V - 45 - - - pF VCC = 3.0 V to 3.6 V - 44 - - - pF MR to SHCP; see Figure 11 SHCP or STCP; see Figure 7 and Figure 8 VCC = 3.0 V to 3.6 V [5] VI = GND to VCC [6] [1] Typical values are measured at Tamb = 25 °C and VCC = 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively. [2] tpd is the same as tPLH and tPHL. [3] ten is the same as tPZH and tPZL. [4] tdis is the same as tPHZ and tPLZ. [5] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. [6] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; ∑(CL × VCC2 × fo) = sum of outputs. 74LVC595A_1 Product data sheet Unit DS to SHCP; see Figure 9 VCC = 3.0 V to 3.6 V tsk(o) −40 °C to +125 °C Typ[1] © NXP B.V. 2007. All rights reserved. Rev. 01 — 29 May 2007 9 of 19 74LVC595A NXP Semiconductors 8-bit serial-in/serial-out or parallel-out shift register; 3-state 12. Waveforms 1/fmax VI SHCP input VM GND tW t PHL t PLH VOH VM Q 7S output VOL mna557 Measurement points are given in Table 8. VOL and VOH are typical output voltage drops that occur with the output load. Fig 7. The shift clock (SHCP) to serial data output (Q7S) propagation delays, the shift clock pulse width and maximum shift clock frequency VI SHCP input VM GND 1/fmax t su VI STCP input VM GND tW t PHL t PLH VOH VM Q n output VOL mna558 Measurement points are given in Table 8. VOL and VOH are typical output voltage drops that occur with the output load. Fig 8. The storage clock (STCP) to parallel data output (Qn) propagation delays, the storage clock pulse width and the shift clock to storage clock set-up time 74LVC595A_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 29 May 2007 10 of 19 74LVC595A NXP Semiconductors 8-bit serial-in/serial-out or parallel-out shift register; 3-state VI VM SHCP input GND t su t su th th VI VM DS input GND VOH VM Q 7S output VOL mna560 Measurement points are given in Table 8. The shaded areas indicate when the input is permitted to change for predictable output performance. VOL and VOH are typical output voltage drops that occur with the output load. Fig 9. The data set-up and hold times for the serial data input (DS) VI MR input VM GND tsu VI STCP input VM GND VOH Qn outputs VM VOL 001aaf571 Measurement points are given in Table 8. VOL and VOH are typical output voltage drops that occur with the output load. Fig 10. The master reset (MR) to storage clock (STCP) set-up times 74LVC595A_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 29 May 2007 11 of 19 74LVC595A NXP Semiconductors 8-bit serial-in/serial-out or parallel-out shift register; 3-state VI VM MR input GND tW t rec VI SHCP input VM GND t PHL VOH VM Q 7S output VOL mna561 Measurement points are given in Table 8. VOL and VOH are typical output voltage drops that occur with the output load. Fig 11. The master reset (MR) pulse width, the master reset to serial data output (Q7S) propagation delays and the master reset to shift clock (SHCP) recovery time VI VM OE input GND tPLZ tPZL VCC output LOW-to-OFF OFF-to-LOW VM VX VOL tPHZ VOH tPZH VY output HIGH-to-OFF OFF-to-HIGH VM GND outputs enabled outputs disabled outputs enabled 001aae821 Measurement points are given in Table 8. VOL and VOH are typical output voltage drops that occur with the output load. Fig 12. 3-state enable and disable times Table 8. Measurement points Supply voltage Input Output VCC VM VM VX VY VCC < 2.7 V 0.5 × VCC 0.5 × VCC VOL + 0.15 V VOH − 0.15 V VCC ≥ 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH − 0.3 V 74LVC595A_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 29 May 2007 12 of 19 74LVC595A NXP Semiconductors 8-bit serial-in/serial-out or parallel-out shift register; 3-state VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VEXT VCC PULSE GENERATOR VI RL VO DUT RT CL RL 001aae331 Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 13. Load circuitry for switching times Table 9. Test data Supply voltage Input Load VEXT VI tr, tf CL RL tPLH, tPHL tPLZ, tPZL tPHZ, tPZH 1.2 V VCC ≤ 2 ns 30 pF 1 kΩ open 2 × VCC GND 1.65 V to 1.95 V VCC ≤ 2 ns 30 pF 1 kΩ open 2 × VCC GND 2.3 V to 2.7 V VCC ≤ 2 ns 30 pF 500 Ω open 2 × VCC GND 2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 2 × VCC GND 3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 2 × VCC GND 74LVC595A_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 29 May 2007 13 of 19 74LVC595A NXP Semiconductors 8-bit serial-in/serial-out or parallel-out shift register; 3-state 13. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.16 0.15 0.05 0.244 0.041 0.228 0.01 0.01 0.028 0.004 0.012 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 14. Package outline SOT109-1 (SO16) 74LVC595A_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 29 May 2007 14 of 19 74LVC595A NXP Semiconductors 8-bit serial-in/serial-out or parallel-out shift register; 3-state TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 E D A X c y HE v M A Z 9 16 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 8 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig 15. Package outline SOT403-1 (TSSOP16) 74LVC595A_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 29 May 2007 15 of 19 74LVC595A NXP Semiconductors 8-bit serial-in/serial-out or parallel-out shift register; 3-state DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT763-1 16 terminals; body 2.5 x 3.5 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 7 y y1 C v M C A B w M C b L 1 8 Eh e 16 9 15 10 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. A1 b 1 0.05 0.00 0.30 0.18 c D (1) Dh E (1) Eh 0.2 3.6 3.4 2.15 1.85 2.6 2.4 1.15 0.85 e 0.5 e1 L v w y y1 2.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT763-1 --- MO-241 --- EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 16. Package outline SOT763-1 (DHVQFN16) 74LVC595A_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 29 May 2007 16 of 19 74LVC595A NXP Semiconductors 8-bit serial-in/serial-out or parallel-out shift register; 3-state 14. Abbreviations Table 10. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model TTL Transistor-Transistor Logic 15. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC595A_1 20070529 Product data sheet - - 74LVC595A_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 29 May 2007 17 of 19 74LVC595A NXP Semiconductors 8-bit serial-in/serial-out or parallel-out shift register; 3-state 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 16.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: [email protected] 74LVC595A_1 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 01 — 29 May 2007 18 of 19 74LVC595A NXP Semiconductors 8-bit serial-in/serial-out or parallel-out shift register; 3-state 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 18 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Contact information. . . . . . . . . . . . . . . . . . . . . 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 29 May 2007 Document identifier: 74LVC595A_1