HEF4517B Dual 64-bit static shift register Rev. 06 — 10 December 2009 Product data sheet 1. General description The HEF4517B consists of two identical, independent 64-bit static shift registers. Each register has separate clock (nCP), data input (nD), parallel input-enable/output-enable (nPE/OE) and four 3-state outputs of the 16th, 32nd, 48th, and 64th bit positions (nQ16 to nQ64). Data at the nD input is entered into the first bit on the LOW-to-HIGH transition of the clock, regardless of the state of nPE/OE. When nPE/OE is LOW, the outputs are enabled and it is in the 64-bit serial mode. When nPE/OE is HIGH, the outputs are disabled (high-impedance OFF-state), the 64-bit shift register is divided into four 16-bit shift registers with nD, nQ16, nQ32 and nQ48 as data inputs of the 1st, 17th, 33rd, and 49th bit respectively. Schmitt-trigger action in the clock input makes the circuit highly tolerant of slower clock rise and fall times. It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input. It is also suitable for use over the full industrial (−40 °C to +85 °C) temperature range. 2. Features Tolerant of slow clock rise and fall times Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Operates across the full industrial temperature range −40 °C to +85 °C Complies with JEDEC standard JESD 13-B 3. Applications Industrial 4. Ordering information Table 1. Ordering information All types operate from −40 °C to +85 °C Type number Package Name Description Version HEF4517BP DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 HEF4517BT SO16 plastic small outline package; 16 leads; body width 7.5 mm SOT162-1 HEF4517B NXP Semiconductors Dual 64-bit static shift register 5. Functional diagram 7 4 3 1D 1CP 1PE/OE 64-BIT STATIC SHIFT REGISTER INPUT/3-STATE-OUTPUT CIRCUITRY 1Q64 1Q48 1Q32 1Q16 9 12 13 5 2 6 1 2D 2CP 2PE/OE 64-BIT STATIC SHIFT REGISTER INPUT/3-STATE-OUTPUT CIRCUITRY 2Q64 2Q48 2Q32 2Q16 11 14 10 15 001aae694 Fig 1. Functional diagram HEF4517B_6 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 06 — 10 December 2009 2 of 15 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx D O CP D O CP FF 1 D O O CP CP FF 16 D FF 17 D O O CP CP FF 32 D FF 33 D O CP FF 48 D NXP Semiconductors HEF4517B_6 Product data sheet 1D O CP FF 49 FF 64 1CP 1PE/OE Rev. 06 — 10 December 2009 2D D O CP FF 1 D O CP FF 16 1Q48 1Q32 1Q16 D O CP FF 17 D O CP FF 32 D O CP FF 33 D O CP FF 48 1Q64 D O CP FF 49 D O CP FF 64 2CP 2Q32 2Q48 2Q64 001aae696 Fig 2. Logic diagram HEF4517B 3 of 15 © NXP B.V. 2009. All rights reserved. 2Q16 Dual 64-bit static shift register 2PE/OE HEF4517B NXP Semiconductors Dual 64-bit static shift register 6. Pinning information 6.1 Pinning HEF4517B 1Q16 1 16 VDD 1Q48 2 15 2Q16 1PE/OE 3 14 2Q48 1CP 4 13 2PE/OE 1Q64 5 12 2CP 1Q32 6 11 2Q64 1D 7 10 2Q32 VSS 8 9 2D 001aae695 Fig 3. Pin configuration 6.2 Pin description Table 2. Pin description Symbol Pin Description 1Q16, 2Q16 1, 15 3-state input/output 1Q48, 2Q48 2, 14 3-state input/output 1PE/OE, 2PE/OE 3, 13 parallel input-enable/output-enable input 1CP, 2CP 4, 12 clock input 1Q64, 2Q64 5, 11 3-state input/output 1Q32, 2Q32 6, 10 3-state input/output 1D, 2D 7, 9 data input VSS 8 ground supply voltage VDD 16 supply voltage HEF4517B_6 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 06 — 10 December 2009 4 of 15 HEF4517B NXP Semiconductors Dual 64-bit static shift register 7. Functional description Table 3. Function table[1] Inputs Inputs/outputs nCP nD nPE/OE Mode nQ16 nQ32 nQ48 nQ64 ↑ data entered L into 1st bit content of 16th bit displayed content of 32nd bit displayed content of 48th bit displayed content of 64th bit displayed ↑ data entered H into 1st bit data at nQ16 entered into 17th bit data at nQ32 entered into 33rd bit data at nQ48 entered into 49th bit remains in ‘Z’ Four 16-bit shift register. The state content of the shift registers is shifted over one stage ↓ X L no change no change no change no change no change ↓ X H Z Z Z Z no change [1] One 64-bit shift register. The content of the shift register is shifted over one stage H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance state; ↑ = positive-going transition; ↓ = negative-going transition. 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDD supply voltage IIK input clamping current VI input voltage IOK output clamping current - ±10 mA II/O input/output current - ±10 mA IDD supply current - 50 mA Tstg storage temperature −65 +150 Tamb ambient temperature Ptot total power dissipation P power dissipation Conditions VI < −0.5 V or VI > VDD + 0.5 V Max −0.5 +18 V - ±10 mA −0.5 VO < −0.5 V or VO > VDD + 0.5 V VDD + 0.5 Unit V °C −40 +85 °C DIP16 package [1] - 750 mW SO16 package [2] - 500 mW - 100 mW per output [1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 °C. [2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 °C. HEF4517B_6 Product data sheet Min © NXP B.V. 2009. All rights reserved. Rev. 06 — 10 December 2009 5 of 15 HEF4517B NXP Semiconductors Dual 64-bit static shift register 9. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VDD supply voltage Conditions Min Typ Max Unit 3 - 15 V VI input voltage 0 - VDD V Tamb ambient temperature in free air −40 - +85 °C Δt/ΔV input transition rise and fall rate VDD = 5 V - - 3.75 μs/V VDD= 10 V - - 0.5 μs/V VDD= 15 V - - 0.08 μs/V 10. Static characteristics Table 6. Static characteristics VSS = 0 V; VI = VSS or VDD unless otherwise specified. Symbol Parameter VIH VIL VOH VOL IOH IOL HIGH-level input voltage LOW-level input voltage VDD |IO| < 1 μA 5V LOW-level output voltage input leakage current IDD supply current input capacitance Tamb = 85 °C Min Max Min Max Min Max 3.5 - 3.5 - 3.5 - Unit V 7.0 - 7.0 - 7.0 - V 11.0 - 11.0 - 11.0 - V 5V - 1.5 - 1.5 - 1.5 V 10 V - 3.0 - 3.0 - 3.0 V 15 V - 4.0 - 4.0 - 4.0 V 5V 4.95 - 4.95 - 4.95 - V 10 V 9.95 - 9.95 - 9.95 - V 15 V 14.95 - 14.95 - 14.95 - V |IO| < 1 μA |IO| < 1 μA 5V - 0.05 - 0.05 - 0.05 V 10 V - 0.05 - 0.05 - 0.05 V 15 V - 0.05 - 0.05 - 0.05 V 5V −1.7 - −1.4 - −1.1 - VO = 4.6 V 5V −0.52 - −0.44 - −0.36 - mA VO = 9.5 V 10 V −1.3 - −1.1 - −0.9 - mA VO = 13.5 V 15 V −3.6 - −3.0 - −2.4 - mA VO = 0.4 V 5V 0.52 - 0.44 - 0.36 - mA VO = 0.5 V 10 V 1.3 - 1.1 - 0.9 - mA VO = 1.5 V 15 V 3.6 - 3.0 - 2.4 - mA 15 V - ±0.3 - ±0.3 - ±1.0 μA 5V - 50 - 50 - 375 μA 10 V - 100 - 100 - 750 μA 15 V - 200 - 200 - 1500 μA - - - - 7.5 - - pF IO = 0 A HEF4517B_6 Product data sheet Tamb = 25 °C 15 V HIGH-level output current VO = 2.5 V LOW-level output current Tamb = −40 °C 10 V HIGH-level output voltage |IO| < 1 μA II CI Conditions mA © NXP B.V. 2009. All rights reserved. Rev. 06 — 10 December 2009 6 of 15 HEF4517B NXP Semiconductors Dual 64-bit static shift register 11. Dynamic characteristics Table 7. Dynamic characteristics VSS = 0 V; Tamb = 25 °C; for test circuit see Figure 8; unless otherwise specified. Symbol Parameter HIGH to LOW propagation delay tPHL Conditions VDD nCP to nQn; see Figure 4 Extrapolation formula Min Typ Max Unit 193 ns + (0.55 ns/pF)CL - 220 440 ns 74 ns + (0.23 ns/pF)CL - 85 170 ns 52 ns + (0.16 ns/pF)CL - 60 120 ns 163 ns + (0.55 ns/pF)CL - 190 380 ns 10 V 64 ns + (0.23 ns/pF)CL - 75 150 ns 15 V 42 ns + (0.16 ns/pF)CL - 50 100 ns 5V - 40 80 ns 10 V - 30 60 ns 15 V - 25 50 ns 5V - 45 90 ns 10 V - 25 50 ns 15 V - 20 40 ns 5V [1] 10 V 15 V LOW to HIGH propagation delay tPLH tPHZ tPZH OFF-state to HIGH propagation delay nPE/OE to nQn; see Figure 5 transition time tt set-up time tsu hold time th pulse width tW maximum frequency fmax [1] nPE/OE to nQn; see Figure 5 OFF-state to LOW propagation delay tPZL 5V HIGH to OFF-state propagation delay LOW to OFF-state propagation delay tPLZ nCP to nQn; see Figure 4 nPE/OE to nQn; see Figure 5 nPE/OE to nQn; see Figure 5 nQn; see Figure 6 nQn, nD to nCP; see Figure 7 nQn, nD to nCP; see Figure 7 see Figure 7 5V - 50 100 ns 10 V - 30 60 ns 15 V - 25 50 ns 5V - 60 120 ns 10 V - 30 60 ns 15 V - 25 50 ns 10 ns + (1.00 ns/pF)CL - 60 120 ns 10 V 9 ns + (0.42 ns/pF)CL - 30 60 ns 15 V 6 ns + (0.28 ns/pF)CL 40 ns 5V nQn, nD to nCP; see Figure 7 [1] [1] - 20 5V 30 10 - ns 10 V 25 5 - ns 15 V 20 5 - ns 5V 45 15 - ns 10 V 30 10 - ns 15 V 25 10 - ns 5V - 95 190 ns 10 V - 40 80 ns 15 V - 30 60 ns 5V 2 5 - MHz 10 V 6 12 - MHz 15 V 8 16 - MHz The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF). HEF4517B_6 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 06 — 10 December 2009 7 of 15 HEF4517B NXP Semiconductors Dual 64-bit static shift register Table 8. Dynamic power dissipation PD PD can be calculated from the formulas shown. VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C. Symbol Parameter PD dynamic power dissipation VDD Typical formula for PD (μW) where: 5V PD = 7000 × fi + Σ(fo × CL) × VDD2 fi = input frequency in MHz, 10 V PD = 28000 × fi + Σ(fo × CL) × VDD2 fo = output frequency in MHz, 15 V PD = 70000 × fi + Σ(fo × CL) × CL = output load capacitance in pF, VDD2 VDD = supply voltage in V, Σ(fo × CL) = sum of the outputs. 12. Waveforms VI nCP input VM 0V tPLH tPHL VOH nQn output VM 001aaj914 VOL Measurement points are given in Table 9 The logic levels VOH and VOL are typical voltage output levels that occur with the output load. Fig 4. Table 9. Propagation delays for nCP to nQn Measurement points Input Output VM VM VX VY 0.5VI 0.5VDD 0.1VDD 0.9VDD HEF4517B_6 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 06 — 10 December 2009 8 of 15 HEF4517B NXP Semiconductors Dual 64-bit static shift register VI VM nPE/OE input 0V tPLZ tPZL VDD nQn output LOW-to-OFF OFF-to-LOW VM VX VOL tPHZ VOH tPZH VY nQn output HIGH-to-OFF OFF-to-HIGH VM GND outputs enabled outputs enabled outputs disabled 001aaj913 Measurement points are given in Table 9 The logic levels VOH and VOL are typical voltage output levels that occur with the output load. Fig 5. Enable and disable times and 3-state propagation delays tt VOH tt 90 % nQn output VOL 10 % 001aaj916 The logic levels VOH and VOL are typical voltage output levels that occur with the output load. Fig 6. Transition times for nQn 1/fmax VI VM nCP input 0V tsu th tW VI nQn, nD input VM 0V 001aae697 The shading indicates where the data (nQn and nD) is permitted to change for predictable output changes. Measurement points are given in Table 9 The logic levels VOH and VOL are typical voltage output levels that occur with the output load. Fig 7. Waveforms showing minimum clock pulse width and maximum frequency and set-up and hold times for nQn (as data input) or nD to nCP HEF4517B_6 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 06 — 10 December 2009 9 of 15 HEF4517B NXP Semiconductors Dual 64-bit static shift register tW VI 90 % negative pulse VM VM 10 % 0V tf tr tr tf VI 90 % positive pulse VM VM 10 % 0V tW 001aaj781 a. Input waveforms VEXT VDD VI RL VO G DUT RT CL 001aaj915 b. Test circuit Test data is given in Table 10. Definitions for test circuit: RL = Load resistance; CL = Load capacitance including jig and probe capacitance; RT = Termination resistance should be equal to output impedance Zo of the pulse generator. Fig 8. Test circuit for switching times Table 10. Test data Supply voltage Input Load VEXT VI tr, tf CL RL tPLH, tPHL tPLZ, tPZL tPHZ, tPZH 5 V to 15 V VDD ≤ 20 ns 50 pF 1 kΩ open 2VDD GND HEF4517B_6 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 06 — 10 December 2009 10 of 15 HEF4517B NXP Semiconductors Dual 64-bit static shift register 13. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b b2 MH 9 16 pin 1 index E 1 8 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 b2 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.30 0.53 0.38 1.25 0.85 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 0.76 inches 0.17 0.02 0.13 0.068 0.051 0.021 0.015 0.049 0.033 0.014 0.009 0.77 0.73 0.26 0.24 0.1 0.3 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.03 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA ISSUE DATE 95-01-14 03-02-13 SOT38-4 Fig 9. EUROPEAN PROJECTION Package outline SOT38-4 (DIP16) HEF4517B_6 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 06 — 10 December 2009 11 of 15 HEF4517B NXP Semiconductors Dual 64-bit static shift register SO16: plastic small outline package; 16 leads; body width 7.5 mm SOT162-1 D E A X c HE y v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index Lp L 8 1 e detail X w M bp 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 10.5 10.1 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.01 0.019 0.013 0.014 0.009 0.41 0.40 0.30 0.29 0.05 0.419 0.043 0.055 0.394 0.016 inches 0.1 0.012 0.096 0.004 0.089 0.043 0.039 0.01 0.01 Z (1) 0.9 0.4 0.035 0.004 0.016 o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT162-1 075E03 MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 10. Package outline SOT162-1 (SO16) HEF4517B_6 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 06 — 10 December 2009 12 of 15 HEF4517B NXP Semiconductors Dual 64-bit static shift register 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes HEF4517B_6 20091210 Product data sheet - HEF4517B_5 Modifications: • Section 9 “Recommended operating conditions” Δt/ΔV values updated. HEF4517B_5 20090728 Product data sheet - HEF4517B_4 HEF4517B_4 20090406 Product data sheet - HEF4517B_CNV_3 HEF4517B_CNV_3 19950101 Product specification - HEF4517B_CNV_2 HEF4517B_CNV_2 19950101 Product specification - - HEF4517B_6 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 06 — 10 December 2009 13 of 15 HEF4517B NXP Semiconductors Dual 64-bit static shift register 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. Definition [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 15.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] HEF4517B_6 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 06 — 10 December 2009 14 of 15 HEF4517B NXP Semiconductors Dual 64-bit static shift register 17. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 13 Legal information. . . . . . . . . . . . . . . . . . . . . . . 14 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Contact information. . . . . . . . . . . . . . . . . . . . . 14 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 10 December 2009 Document identifier: HEF4517B_6