74AUP2G00 Low-power dual 2-input NAND gate Rev. 01 — 25 August 2006 Product data sheet 1. General description The 74AUP2G00 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. The 74AUP2G00 provides the dual 2-input NAND function. 2. Features ■ Wide supply voltage range from 0.8 V to 3.6 V ■ High noise immunity ■ Complies with JEDEC standards: ◆ JESD8-12 (0.8 V to 1.3 V) ◆ JESD8-11 (0.9 V to 1.65 V) ◆ JESD8-7 (1.2 V to 1.95 V) ◆ JESD8-5 (1.8 V to 2.7 V) ◆ JESD8-B (2.7 V to 3.6 V) ■ ESD protection: ◆ HBM JESD22-A114-D Class 3A exceeds 4000 V ◆ MM JESD22-A115-A exceeds 200 V ◆ CDM JESD22-C101-C exceeds 1000 V ■ Low static power consumption; ICC = 0.9 µA (maximum) ■ Latch-up performance exceeds 100 mA per JESD 78 Class II ■ Inputs accept voltages up to 3.6 V ■ Low noise overshoot and undershoot < 10 % of VCC ■ IOFF circuitry provides partial Power-down mode operation ■ Multiple package options ■ Specified from −40 °C to +85 °C and −40 °C to +125 °C 74AUP2G00 Philips Semiconductors Low-power dual 2-input NAND gate 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP2G00DC −40 °C to +125 °C VSSOP8 plastic very thin shrink small outline package; 8 leads; SOT765-1 body width 2.3 mm 74AUP2G00GT −40 °C to +125 °C XSON8 plastic extremely thin small outline package; no leads; SOT833-1 8 terminals; body 1 × 1.95 × 0.5 mm 74AUP2G00GM −40 °C to +125 °C XQFN8 plastic extremely thin quad flat package; no leads; 8 terminals; body 1.6 × 1.6 × 0.5 mm SOT902-1 4. Marking Table 2. Marking Type number Marking code 74AUP2G00DC p00 74AUP2G00GT p00 74AUP2G00GM p00 5. Functional diagram 1 1 1A 2 1B 5 2A 6 2B & 7 2 1Y 7 2Y 3 B 5 & 3 Y 6 A mna712 Fig 1. Logic symbol mna713 Fig 2. IEC logic symbol mna099 Fig 3. Logic diagram (one gate) 6. Pinning information 6.1 Pinning 74AUP2G00 1A 1 8 VCC 1B 2 7 1Y 2Y 3 6 2B GND 4 5 2A 001aae362 Fig 4. Pin configuration SOT765-1 (VSSOP8) 74AUP2G00_1 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01 — 25 August 2006 2 of 16 74AUP2G00 Philips Semiconductors Low-power dual 2-input NAND gate 74AUP2G00 1 8 VCC 1B 2 7 1Y 2Y 3 6 2B 1Y 1 2B 2A 7 1A 2 6 1B 3 5 2Y 4 1A 8 74AUP2G00 VCC terminal 1 index area 4 5 2A GND GND 001aae363 001aae364 Transparent top view Transparent top view Fig 5. Pin configuration SOT833-1 (XSON8) Fig 6. Pin configuration SOT902-1 (XQFN8) 6.2 Pin description Table 3. Symbol Pin description Pin Description SOT765-1 and SOT833-1 SOT902-1 1A 1 7 data input 1A 1B 2 6 data input 1B 2Y 3 5 data output 2Y GND 4 4 ground (0 V) 2A 5 3 data input 2A 2B 6 2 data input 2B 1Y 7 1 data output 1Y VCC 8 8 supply voltage 7. Functional description Table 4. Function table[1] Input Output nA nB nY L L H L H H H L H H H L [1] H = HIGH voltage level; L = LOW voltage level. 74AUP2G00_1 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01 — 25 August 2006 3 of 16 74AUP2G00 Philips Semiconductors Low-power dual 2-input NAND gate 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current Conditions VI < 0 V [1] VO < 0 V [1] Min Max Unit −0.5 +4.6 V - −50 mA −0.5 +4.6 V - −50 mA −0.5 +4.6 V VO output voltage Active mode and Power-down mode IO output current VO = 0 V to VCC - ±20 mA ICC supply current - +50 mA IGND ground current - −50 mA Tstg storage temperature −65 +150 °C - 250 mW total power dissipation Ptot Tamb = −40 °C to +125 °C [2] [1] The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For VSSOP8 packages: above 110 °C the value of Ptot derates linearly with 8.0 mW/K. For XSON8 and XQFN8 packages: above 45 °C the value of Ptot derates linearly with 2.4 mW/K. 9. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter VCC supply voltage VI input voltage VO output voltage Tamb ambient temperature ∆t/∆V input transition rise and fall rate Conditions Max Unit 0.8 3.6 V 0 3.6 V Active mode 0 VCC V Power-down mode; VCC = 0 V 0 3.6 V −40 +125 °C 0 200 ns/V VCC = 0.8 V to 3.6 V 74AUP2G00_1 Product data sheet Min © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01 — 25 August 2006 4 of 16 74AUP2G00 Philips Semiconductors Low-power dual 2-input NAND gate 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit Tamb = 25 °C VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VCC = 0.8 V 0.70 × VCC - - V VCC = 0.9 V to 1.95 V 0.65 × VCC - - V VCC = 2.3 V to 2.7 V 1.6 - - V VCC = 3.0 V to 3.6 V 2.0 - - V VCC = 0.8 V - - 0.30 × VCC V VCC = 0.9 V to 1.95 V - - 0.35 × VCC V VCC = 2.3 V to 2.7 V - - 0.7 V VCC = 3.0 V to 3.6 V - - 0.9 V IO = −20 µA; VCC = 0.8 V to 3.6 V VCC − 0.1 - - V IO = −1.1 mA; VCC = 1.1 V 0.75 × VCC - - V IO = −1.7 mA; VCC = 1.4 V 1.11 - V VI = VIH or VIL - IO = −1.9 mA; VCC = 1.65 V 1.32 - - V IO = −2.3 mA; VCC = 2.3 V 2.05 - - V IO = −3.1 mA; VCC = 2.3 V 1.9 - - V IO = −2.7 mA; VCC = 3.0 V 2.72 - - V IO = −4.0 mA; VCC = 3.0 V 2.6 - - V IO = 20 µA; VCC = 0.8 V to 3.6 V - - 0.1 V IO = 1.1 mA; VCC = 1.1 V - - 0.3 × VCC V VI = VIH or VIL IO = 1.7 mA; VCC = 1.4 V - - 0.31 V IO = 1.9 mA; VCC = 1.65 V - - 0.31 V IO = 2.3 mA; VCC = 2.3 V - - 0.31 V IO = 3.1 mA; VCC = 2.3 V - - 0.44 V IO = 2.7 mA; VCC = 3.0 V - - 0.31 V IO = 4.0 mA; VCC = 3.0 V - - 0.44 V II input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - ±0.1 µA IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - ±0.2 µA ∆IOFF additional power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V - - ±0.2 µA ICC supply current VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V - - 0.5 µA ∆ICC additional supply current VI = VCC − 0.6 V; IO = 0 A; VCC = 3.3 V - - 40 µA CI input capacitance VCC = 0 V to 3.6 V; VI = GND or VCC - 0.8 - pF CO output capacitance VO = GND; VCC = 0 V - 1.7 - pF 74AUP2G00_1 Product data sheet [1] © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01 — 25 August 2006 5 of 16 74AUP2G00 Philips Semiconductors Low-power dual 2-input NAND gate Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min VCC = 0.8 V Typ Max Unit 0.70 × VCC - - V VCC = 0.9 V to 1.95 V 0.65 × VCC - - V VCC = 2.3 V to 2.7 V 1.6 - - V VCC = 3.0 V to 3.6 V 2.0 - - V VCC = 0.8 V - - 0.30 × VCC V VCC = 0.9 V to 1.95 V - - 0.35 × VCC V VCC = 2.3 V to 2.7 V - - 0.7 V VCC = 3.0 V to 3.6 V - - 0.9 V Tamb = −40 °C to +85 °C VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VI = VIH or VIL IO = −20 µA; VCC = 0.8 V to 3.6 V VCC − 0.1 - - V IO = −1.1 mA; VCC = 1.1 V 0.7 × VCC - - V IO = −1.7 mA; VCC = 1.4 V 1.03 - - V IO = −1.9 mA; VCC = 1.65 V 1.30 - - V IO = −2.3 mA; VCC = 2.3 V 1.97 - - V IO = −3.1 mA; VCC = 2.3 V 1.85 - - V IO = −2.7 mA; VCC = 3.0 V 2.67 - - V IO = −4.0 mA; VCC = 3.0 V 2.55 - - V IO = 20 µA; VCC = 0.8 V to 3.6 V - - 0.1 V IO = 1.1 mA; VCC = 1.1 V - - 0.3 × VCC V IO = 1.7 mA; VCC = 1.4 V - - 0.37 V VI = VIH or VIL IO = 1.9 mA; VCC = 1.65 V - - 0.35 V IO = 2.3 mA; VCC = 2.3 V - - 0.33 V IO = 3.1 mA; VCC = 2.3 V - - 0.45 V IO = 2.7 mA; VCC = 3.0 V - - 0.33 V - - 0.45 V II input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V IO = 4.0 mA; VCC = 3.0 V - - ±0.5 µA IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - ±0.5 µA ∆IOFF additional power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V - - ±0.6 µA ICC supply current VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V - - 0.9 µA ∆ICC additional supply current VI = VCC − 0.6 V; IO = 0 A; VCC = 3.3 V - - 50 µA 74AUP2G00_1 Product data sheet [1] © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01 — 25 August 2006 6 of 16 74AUP2G00 Philips Semiconductors Low-power dual 2-input NAND gate Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min VCC = 0.8 V Typ Max Unit 0.75 × VCC - - V VCC = 0.9 V to 1.95 V 0.70 × VCC - - V VCC = 2.3 V to 2.7 V 1.6 - - V VCC = 3.0 V to 3.6 V 2.0 - - V VCC = 0.8 V - - 0.25 × VCC V VCC = 0.9 V to 1.95 V - - 0.30 × VCC V VCC = 2.3 V to 2.7 V - - 0.7 V VCC = 3.0 V to 3.6 V - - 0.9 V Tamb = −40 °C to +125 °C HIGH-level input voltage VIH LOW-level input voltage VIL VOH HIGH-level output voltage LOW-level output voltage VOL VI = VIH or VIL IO = −20 µA; VCC = 0.8 V to 3.6 V VCC − 0.11 - - V IO = −1.1 mA; VCC = 1.1 V 0.6 × VCC - - V IO = −1.7 mA; VCC = 1.4 V 0.93 - - V IO = −1.9 mA; VCC = 1.65 V 1.17 - - V IO = −2.3 mA; VCC = 2.3 V 1.77 - - V IO = −3.1 mA; VCC = 2.3 V 1.67 - - V IO = −2.7 mA; VCC = 3.0 V 2.40 - - V IO = −4.0 mA; VCC = 3.0 V 2.30 - - V IO = 20 µA; VCC = 0.8 V to 3.6 V - - 0.11 V IO = 1.1 mA; VCC = 1.1 V - - 0.33 × VCC V IO = 1.7 mA; VCC = 1.4 V - - 0.41 VI = VIH or VIL V IO = 1.9 mA; VCC = 1.65 V - - 0.39 V IO = 2.3 mA; VCC = 2.3 V - - 0.36 V IO = 3.1 mA; VCC = 2.3 V - - 0.50 V IO = 2.7 mA; VCC = 3.0 V - - 0.36 V - - 0.50 V II input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V IO = 4.0 mA; VCC = 3.0 V - - ±0.75 µA IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - ±0.75 µA ∆IOFF additional power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V - - ±0.75 µA ICC supply current VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V - - 1.4 µA ∆ICC additional supply current VI = VCC − 0.6 V; IO = 0 A; VCC = 3.3 V - - 75 µA [1] [1] One input at VCC − 0.6 V, other input at VCC or GND. 74AUP2G00_1 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01 — 25 August 2006 7 of 16 74AUP2G00 Philips Semiconductors Low-power dual 2-input NAND gate 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8. Symbol Parameter 25 °C Conditions −40 °C to +125 °C Unit Min Typ[1] Max Min Max (85 °C) Max (125 °C) - 17.5 - - - - ns VCC = 1.1 V to 1.3 V 2.5 5.3 11.0 2.1 12.2 13.5 ns VCC = 1.4 V to 1.6 V 2.0 3.8 6.8 1.8 7.8 8.6 ns VCC = 1.65 V to 1.95 V 1.6 3.1 5.3 1.4 6.2 6.9 ns VCC = 2.3 V to 2.7 V 1.3 2.5 4.0 1.1 4.7 5.2 ns VCC = 3.0 V to 3.6 V 1.0 2.2 3.6 1.0 4.2 4.7 ns - 21.0 - - - - ns VCC = 1.1 V to 1.3 V 2.4 6.1 13.0 2.2 14.4 15.9 ns VCC = 1.4 V to 1.6 V 2.4 4.4 7.9 2.2 9.2 10.2 ns VCC = 1.65 V to 1.95 V 2.0 3.7 6.2 1.9 7.3 8.1 ns VCC = 2.3 V to 2.7 V 1.4 3.0 4.7 1.3 5.6 6.2 ns VCC = 3.0 V to 3.6 V 1.3 2.8 4.3 1.2 4.9 5.4 ns - 24.5 - - - - ns VCC = 1.1 V to 1.3 V 3.4 6.9 14.8 3.1 16.5 18.2 ns VCC = 1.4 V to 1.6 V 2.8 5.0 8.9 2.5 10.5 11.6 ns VCC = 1.65 V to 1.95 V 2.0 4.1 7.0 2.0 8.3 9.2 ns VCC = 2.3 V to 2.7 V 1.7 3.5 5.3 1.5 6.4 7.1 ns VCC = 3.0 V to 3.6 V 1.6 3.2 4.9 1.4 5.7 6.3 ns - 34.8 - - - - ns VCC = 1.1 V to 1.3 V 4.6 9.2 20.1 4.1 22.6 24.9 ns VCC = 1.4 V to 1.6 V 3.0 6.5 11.8 2.9 14.0 15.4 ns VCC = 1.65 V to 1.95 V 2.6 5.4 9.3 2.3 11.1 12.3 ns VCC = 2.3 V to 2.7 V 2.4 4.6 7.1 2.1 8.5 9.4 ns VCC = 3.0 V to 3.6 V 2.3 4.3 6.5 2.1 7.6 8.4 ns CL = 5 pF tpd propagation delay nA, nB to nY; see Figure 7 [2] VCC = 0.8 V CL = 10 pF tpd propagation delay nA, nB to nY; see Figure 7 [2] VCC = 0.8 V CL = 15 pF tpd propagation delay nA, nB to nY; see Figure 7 [2] VCC = 0.8 V CL = 30 pF tpd propagation delay nA, nB to nY; see Figure 7 VCC = 0.8 V [2] 74AUP2G00_1 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01 — 25 August 2006 8 of 16 74AUP2G00 Philips Semiconductors Low-power dual 2-input NAND gate Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8. Symbol Parameter 25 °C Conditions −40 °C to +125 °C Unit Min Typ[1] Max Min Max (85 °C) Max (125 °C) VCC = 0.8 V - 2.8 - - - - pF VCC = 1.1 V to 1.3 V - 2.9 - - - - pF VCC = 1.4 V to 1.6 V - 3.0 - - - - pF VCC = 1.65 V to 1.95 V - 3.0 - - - - pF VCC = 2.3 V to 2.7 V - 3.4 - - - - pF VCC = 3.0 V to 3.6 V - 3.9 - - - - pF CL = 5 pF, 10 pF, 15 pF and 30 pF power dissipation capacitance CPD [3] fi = 1 MHz; VI = GND to VCC [1] All typical values are measured at nominal VCC. [2] tpd is the same as tPLH and tPHL. [3] CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; Σ(CL × VCC2 × fo) = sum of the outputs. 12. Waveforms nA, nB input VM tPHL tPLH VM nY output mna213 Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage drop that occur with the output load. Fig 7. The data input (nA or nB) to output (nY) propagation delays Table 9. Measurement points Supply voltage Output Input VCC VM VM VI tr = tf 0.8 V to 3.6 V 0.5 × VCC 0.5 × VCC VCC ≤ 3.0 ns 74AUP2G00_1 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01 — 25 August 2006 9 of 16 74AUP2G00 Philips Semiconductors Low-power dual 2-input NAND gate VCC VEXT 5 kΩ PULSE GENERATOR VI VO DUT RT CL RL 001aac521 Test data is given in Table 10. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 8. Load circuitry for switching times Table 10. Test data Supply voltage Load VEXT RL[1] VCC CL 0.8 V to 3.6 V 5 pF, 10 pF, 15 pF and 30 pF 5 kΩ or 1 MΩ [1] tPLH, tPHL tPZH, tPHZ tPZL, tPLZ open GND 2 × VCC For measuring enable and disable times RL = 5 kΩ, for measuring propagation delays, setup and hold times and pulse width RL = 1 MΩ. 74AUP2G00_1 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01 — 25 August 2006 10 of 16 74AUP2G00 Philips Semiconductors Low-power dual 2-input NAND gate 13. Package outline VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm D E SOT765-1 A X c y HE v M A Z 5 8 Q A A2 A1 pin 1 index (A3) θ Lp 1 4 e L detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(2) e HE L Lp Q v w y Z(1) θ mm 1 0.15 0.00 0.85 0.60 0.12 0.27 0.17 0.23 0.08 2.1 1.9 2.4 2.2 0.5 3.2 3.0 0.4 0.40 0.15 0.21 0.19 0.2 0.13 0.1 0.4 0.1 8° 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT765-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 02-06-07 MO-187 Fig 9. Package outline SOT765-1 (VSSOP8) 74AUP2G00_1 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01 — 25 August 2006 11 of 16 74AUP2G00 Philips Semiconductors Low-power dual 2-input NAND gate XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm 1 2 SOT833-1 b 4 3 4× (2) L L1 e 8 7 6 e1 5 e1 e1 8× A (2) A1 D E terminal 1 index area 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A (1) max A1 max b D E e e1 L L1 mm 0.5 0.04 0.25 0.17 2.0 1.9 1.05 0.95 0.6 0.5 0.35 0.27 0.40 0.32 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT833-1 --- MO-252 --- EUROPEAN PROJECTION ISSUE DATE 04-07-22 04-11-09 Fig 10. Package outline SOT833-1 (XSON8) 74AUP2G00_1 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01 — 25 August 2006 12 of 16 74AUP2G00 Philips Semiconductors Low-power dual 2-input NAND gate XQFN8: plastic extremely thin quad flat package; no leads; 8 terminals; body 1.6 x 1.6 x 0.5 mm B D SOT902-1 A terminal 1 index area E A A1 detail X L1 e e C ∅v M C A B ∅w M C L 4 y1 C y 5 3 metal area not for soldering e1 b 2 6 e1 7 1 terminal 1 index area 8 X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max A1 b D E e e1 L L1 v w y y1 mm 0.5 0.05 0.00 0.25 0.15 1.65 1.55 1.65 1.55 0.55 0.5 0.35 0.25 0.15 0.05 0.1 0.05 0.05 0.05 REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT902-1 --- MO-255 --- EUROPEAN PROJECTION ISSUE DATE 05-11-16 05-11-25 Fig 11. Package outline SOT902-1 (XQFN8) 74AUP2G00_1 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01 — 25 August 2006 13 of 16 74AUP2G00 Philips Semiconductors Low-power dual 2-input NAND gate 14. Abbreviations Table 11. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 15. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes 74AUP2G00_1 20060825 Product data sheet - - 74AUP2G00_1 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01 — 25 August 2006 14 of 16 74AUP2G00 Philips Semiconductors Low-power dual 2-input NAND gate 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. 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Terms and conditions of sale — Philips Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.semiconductors.philips.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by Philips Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: [email protected] 74AUP2G00_1 Product data sheet © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Rev. 01 — 25 August 2006 15 of 16 Philips Semiconductors 74AUP2G00 Low-power dual 2-input NAND gate 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Contact information. . . . . . . . . . . . . . . . . . . . . 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © Koninklijke Philips Electronics N.V. 2006. All rights reserved. For more information, please visit: http://www.semiconductors.philips.com. For sales office addresses, email to: [email protected]. Date of release: 25 August 2006 Document identifier: 74AUP2G00_1