INTEGRATED CIRCUITS 74F219A 64-bit TTL bipolar RAM, non-inverting (3-State) Product specification IC15 Data Handbook 1996 Jan 05 Philips Semiconductors Product specification 64-bit TTL bipolar RAM, non-inverting (3-State) FEATURES 74F219A APPLICATIONS • High speed performance • Replaces 74F219 • Address access time: 8ns max vs 28ns for 74F219 • Power dissipation: 4.3mW/bit typ • Schottky clamp TTL • One chip enable • Non–Inverting outputs (for inverting outputs see 74F189A) • 3–state outputs • 74F219A in 150 mil wide SO is preferred options for new designs • C3F219A in 300 mil wide SOL replaces 74F219 in existing • Scratch pad memory • Buffer memory • Push down stacks • Control store PIN CONFIGURATION designs DESCRIPTION The 74F219A is a high speed, 64–bit RAM organized as a 16–word by 4–bit array. Address inputs are buffered to minimize loading and are fully decoded on chip. The outputs are in high impedance state whenever the chip enable (CE) is high. The outputs are active only in the READ mode (WE = high) and the output data is the complement of the stored data. A0 1 16 VCC CE 2 15 A1 WE 3 14 A2 D0 4 13 A3 Q0 5 12 D3 D1 6 11 Q3 Q1 7 10 D2 GND 8 9 Q2 SF00307 TYPE TYPICAL ACCESS TIME TYPICAL SUPPLY CURRENT(TOTAL) 74F219A 5.0ns 55mA ORDERING INFORMATION ORDER CODE DESCRIPTION COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C DRAWING NUMBER 16-pin plastic Dual In-line Package N74F219AN SOT38-4 16-pin plastic Small Outline (150mil) N74F219AD SOT109-1 16-pin plastic Small Outline Large (300mil) C3F219AD SOT162–1 INPUT AND OUTPUT LOADING AND FAN OUT TABLE PINS DESCRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW D0 – D3 Data inputs 1.0/1.0 20µA/0.6mA A0 – A3 Address inputs 1.0/1.0 20µA/0.6mA CE Chip enable input (active low) 1.0/2.0 20µA/1.2mA WE Write enable input (active low) 1.0/2.0 20µA/1.2mA Data outputs 150/40 3mA/24mA Q0 – Q3 NOTE: One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state. 1996 Jan 05 2 853-1308 16196 Philips Semiconductors Product specification 64-bit TTL bipolar RAM, non-inverting (3-State) LOGIC SYMBOL 74F219A IEC/IEEE SYMBOL 4 6 10 12 5 7 9 A 13 A0 A1 A2 A3 CE WE Q0 Q1 Q2 Q3 VCC = pin 16 GND = pin 8 0 14 D0 D1 D2 D3 1 15 14 13 2 3 RAM 16X4 1 15 0 15 1 2 3 G1 1 EN [READ] 1 C2 [WRITE] 4 A,2D 7 9 12 11 11 SF00301 LOGIC DIAGRAM D0 D1 D2 D3 4 6 10 12 3 2 Data buffers A1 A2 A3 WE CE 1 15 14 Decoder Drivers Address Decoder 16–word x 4–bit memory cell array 13 Output buffers 5 7 9 VCC = Pin 16 GND = Pin 8 SF00309 FUNCTION TABLE OUTPUT OPERATING Qn MODE CE WE Dn L H X Stored data Read L L L High impedance Write “0” L L H High impedance Write “1” H X X High impedance Disable input NOTES: H = High voltage level L = Low voltage level X = Don’t care 1996 Jan 05 11 Q0 Q1 Q2 Q3 INPUTS 5 10 SF00308 A0 A 6 3 Philips Semiconductors Product specification 64-bit TTL bipolar RAM, non-inverting (3-State) 74F219A ABSOLUTE MAXIMUM RATINGS (Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL PARAMETER RATING UNIT VCC Supply voltage –0.5 to +7.0 V VIN Input voltage –0.5 to +7.0 V IIN Input current VOUT Voltage applied to output in high output state IOUT Current applied to output in low output state Tamb Operating free-air temperature range Tstg Storage temperature range –30 to +5 mA –0.5 to VCC V 48 mA 0 to +70 °C –65 to +150 °C RECOMMENDED OPERATING CONDITIONS SYMBOL LIMITS PARAMETER MIN NOM MAX 5.0 5.5 UNIT VCC Supply voltage 4.5 V VIH High–level input voltage 2.0 VIL Low–level input voltage 0.8 V IIk Input clamp current –18 mA IOH High–level output current –3 mA IOL Low–level output current 24 mA Tamb Operating free-air temperature range +70 °C V 0 DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL TEST CONDITIONS1 PARAMETER LIMITS MIN VOH High-level output voltage VOL Low-level output voltage VCC = MIN, VIL = MAX ±10%VCC 2.4 VIH = MIN, IOH = MAX ±5%VCC 2.7 VCC = MIN, VIL = MAX VIH = MIN, IOL = MAX TYP2 UNIT MAX V 3.4 V ±10%VCC 0.35 0.50 V ±5%VCC 0.35 0.50 V -0.73 -1.2 V 100 µA VIK Input clamp voltage VCC = MIN, II = IIK II Input current at maximum input voltage VCC = MAX, VI = 7.0V IIH High–level input current VCC = MAX, VI = 2.7V 20 µA IIL Low–level input current VCC = MAX, VI = 0.5V -0.6 mA -1.2 mA IOZH Offset output current, high–level voltage applied VCC = MAX, VI = 2.7V 50 µA IOZL Offset output current, low–level voltage applied VCC = MAX, VI = 0.5V –50 µA IOS Short-circuit output current3 VCC = MAX -150 mA ICC Supply current (total) VCC = MAX, CE = WE = GND 55 80 mA CIN Input capacitance VCC = 5V, VIN = 2.0V 4 others CE, WE -60 pF COUT Output capacitance VCC = 5V, VOUT = 2.0V 7 pF NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5V, Tamb = 25°C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. 1996 Jan 05 4 Philips Semiconductors Product specification 64-bit TTL bipolar RAM, non-inverting (3-State) 74F219A AC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL tPLH tPHL PARAMETER Access time tPZH tPZL tPHZ tPLZ Disable time CE to Qn tPZH tPZL Write recovery time tPHZ tPLZ Disable time WE to Qn Propagation delay An to Qn Enable time CE to Qn Enable time WE to Qn TEST CONDITION Tamb = +25°C VCC = +5.0V CL = 50pF, RL = 500Ω Tamb = 0°C to +70°C VCC = +5.0V ± 10% CL = 50pF, RL = 500Ω UNIT MIN TYP MAX MIN MAX Waveform 1 2.5 2.0 5.0 4.5 8.0 8.0 2.5 2.0 8.0 8.0 ns Waveform 2 1.5 2.5 3.0 4.0 6.0 7.0 1.5 2.0 7.0 7.5 ns Waveform 3 2.5 1.5 4.5 3.0 7.0 5.5 2.0 1.0 8.0 6.0 ns Waveform 4 2.0 3.0 3.5 4.5 6.5 7.5 1.5 2.5 7.0 8.0 ns Waveform 4 3.0 1.5 5.0 3.5 8.0 6.0 2.5 1.5 9.0 7.0 ns AC SETUP REQUIREMENT LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25°C VCC = +5.0V CL = 50pF, RL = 500Ω MIN tsu(H) tsu(L) Setup time, high or low An to WE th(H) th(L) TYP MAX Tamb = 0°C to +70°C VCC = +5.0V ± 10% CL = 50pF, RL = 500Ω MIN UNIT MAX Waveform 4 4.5 4.5 5.0 5.0 ns Hold time, high or low An to WE Waveform 4 0 0 0 0 ns tsu(H) tsu(L) Setup time, high or low Dn to WE Waveform 4 8.0 7.5 9.0 8.5 ns th(H) th(L) Hold time, high or low Dn to WE Waveform 4 0 0 0 0 ns tsu(L) Setup time, low CE (falling edge) to WE (falling edge) Waveform 4 0 0 ns th(L) Hold time, low WE (falling edge) to WE (rising edge) Waveform 4 6.5 7.5 ns tw(L) Pulse width, low WE Waveform 4 7.0 8.0 ns 1996 Jan 05 5 Philips Semiconductors Product specification 64-bit TTL bipolar RAM, non-inverting (3-State) 74F219A AC WAVEFORMS FOR READ CYCLES For all waveforms, VM = 1.5V. An VM tPHL Qn VM tPLH SP000310 Waveform 1. Read cycle, address access time CE VM tPZH VM Qn tPZL SP000311 Waveform 2. Read cycle, chip enable access time CE VM tPHZ Qn VM tPLZ SP000312 Waveform 3. Read cycle, chip disable time 1996 Jan 05 6 Philips Semiconductors Product specification 64-bit TTL bipolar RAM, non-inverting (3-State) 74F219A AC WAVEFORMS FOR WRITE CYCLE An VM VM tsu (H or L) th (H or L) VM Dn VM tsu ( L) VM th (H or L) VM VM CE tsu (H or L) th ( L) tw ( L) VM WE VM tPHZ tPZH Hi–Z Qn VM VM tPLZ tPZL NOTE: For all waveforms, VM = 1.5V. SP000313 Waveform 4. Write cycle TEST CIRCUIT AND WAVEFORM VCC VIN tw 90% NEGATIVE PULSE VM D.U.T. RT CL RL AMP (V) VM 10% VOUT PULSE GENERATOR 90% 10% tTHL (tf ) tTLH (tr ) tTLH (tr ) tTHL (tf ) 0V AMP (V) 90% 90% POSITIVE PULSE DEFINITIONS: RL = Load resistor; see AC ELECTRICAL CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC ELECTRICAL CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. VM VM 10% Test Circuit for Totem-Pole Outputs 10% tw 0V Input Pulse Definition INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0V 1.5V rep. rate tw tTLH tTHL 1MHz 500ns 2.5ns 2.5ns SF00006 1996 Jan 05 7 Philips Semiconductors Product specification 64-Bit TTL bipolar RAM, non-inverting (3-State) DIP16: plastic dual in-line package; 16 leads (300 mil); long body 1996 Jan 05 8 74F219A SOT38-1 Philips Semiconductors Product specification 64-Bit TTL bipolar RAM, non-inverting (3-State) SO16: plastic small outline package; 16 leads; body width 3.9 mm 1996 Jan 05 9 74F219A SOT109-1 Philips Semiconductors Product specification 64-Bit TTL bipolar RAM, non-inverting (3-State) SO16: plastic small outline package; 16 leads; body width 7.5 mm 1996 Jan 05 10 74F219A SOT162-1 Philips Semiconductors Product specification 64-Bit TTL bipolar RAM, non-inverting (3-State) NOTES 1996 Jan 05 11 74F219A Philips Semiconductors Product specification 64-bit TTL bipolar RAM, non-inverting (3-State) 74F219A DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Formative or in Design This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. Preliminary Specification Preproduction Product This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product Specification Full Production This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381 Philips Semiconductors and Philips Electronics North America Corporation register eligible circuits under the Semiconductor Chip Protection Act. Copyright Philips Electronics North America Corporation 1996 All rights reserved. Printed in U.S.A. (print code) Document order number: Date of release: July 1994 9397-750-05098